Backport patch allowing to set the MDIO bus clock frequency.
By default the MDIO bus clock runs on 2.5 MHz, allow increasing it
up to 25 MHz.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
--- /dev/null
+From c0a440031d4314d1023c1b87f43a4233634eebdb Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 19 Mar 2023 12:57:15 +0000
+Subject: [PATCH] net: ethernet: mtk_eth_soc: set MDIO bus clock frequency
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Set MDIO bus clock frequency and allow setting a custom maximum
+frequency from device tree.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Tested-by: Bjørn Mork <bjorn@mork.no>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 21 +++++++++++++++++++++
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 7 +++++++
+ 2 files changed, 28 insertions(+)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -704,8 +704,10 @@ static const struct phylink_mac_ops mtk_
+
+ static int mtk_mdio_init(struct mtk_eth *eth)
+ {
++ unsigned int max_clk = 2500000, divider;
+ struct device_node *mii_np;
+ int ret;
++ u32 val;
+
+ mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
+ if (!mii_np) {
+@@ -731,6 +733,25 @@ static int mtk_mdio_init(struct mtk_eth
+ eth->mii_bus->parent = eth->dev;
+
+ snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
++
++ if (!of_property_read_u32(mii_np, "clock-frequency", &val)) {
++ if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) {
++ dev_err(eth->dev, "MDIO clock frequency out of range");
++ ret = -EINVAL;
++ goto err_put_node;
++ }
++ max_clk = val;
++ }
++ divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
++
++ /* Configure MDC Divider */
++ val = mtk_r32(eth, MTK_PPSC);
++ val &= ~PPSC_MDC_CFG;
++ val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO;
++ mtk_w32(eth, val, MTK_PPSC);
++
++ dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
++
+ ret = of_mdiobus_register(eth->mii_bus, mii_np);
+
+ err_put_node:
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -363,6 +363,13 @@
+ #define RX_DMA_VTAG_V2 BIT(0)
+ #define RX_DMA_L4_VALID_V2 BIT(2)
+
++/* PHY Polling and SMI Master Control registers */
++#define MTK_PPSC 0x10000
++#define PPSC_MDC_CFG GENMASK(29, 24)
++#define PPSC_MDC_TURBO BIT(20)
++#define MDC_MAX_FREQ 25000000
++#define MDC_MAX_DIVIDER 63
++
+ /* PHY Indirect Access Control registers */
+ #define MTK_PHY_IAC 0x10004
+ #define PHY_IAC_ACCESS BIT(31)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -2972,8 +2972,8 @@ static irqreturn_t mtk_handle_irq_rx(int
+@@ -2993,8 +2993,8 @@ static irqreturn_t mtk_handle_irq_rx(int
eth->rx_events++;
if (likely(napi_schedule_prep(ð->rx_napi))) {
}
return IRQ_HANDLED;
-@@ -2985,8 +2985,8 @@ static irqreturn_t mtk_handle_irq_tx(int
+@@ -3006,8 +3006,8 @@ static irqreturn_t mtk_handle_irq_tx(int
eth->tx_events++;
if (likely(napi_schedule_prep(ð->tx_napi))) {
}
return IRQ_HANDLED;
-@@ -4617,6 +4617,8 @@ static int mtk_probe(struct platform_dev
+@@ -4638,6 +4638,8 @@ static int mtk_probe(struct platform_dev
* for NAPI to work
*/
init_dummy_netdev(ð->dummy_dev);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2341,6 +2341,10 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2342,6 +2342,10 @@ mt7531_setup(struct dsa_switch *ds)
return -ENODEV;
}
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4586,8 +4586,8 @@ static int mtk_probe(struct platform_dev
+@@ -4607,8 +4607,8 @@ static int mtk_probe(struct platform_dev
for (i = 0; i < num_ppe; i++) {
u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
if (!eth->ppe[i]) {
err = -ENOMEM;
goto err_free_dev;
-@@ -4712,6 +4712,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4733,6 +4733,7 @@ static const struct mtk_soc_data mt7622_
.required_pctl = false,
.offload_version = 2,
.hash_offset = 2,
.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
-@@ -4749,6 +4750,7 @@ static const struct mtk_soc_data mt7629_
+@@ -4770,6 +4771,7 @@ static const struct mtk_soc_data mt7629_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7629_CLKS_BITMAP,
.required_pctl = false,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4769,6 +4771,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4790,6 +4792,7 @@ static const struct mtk_soc_data mt7986_
.offload_version = 2,
.hash_offset = 4,
.foe_entry_size = sizeof(struct mtk_foe_entry),
.rxd_size = sizeof(struct mtk_rx_dma_v2),
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1037,6 +1037,8 @@ struct mtk_reg_map {
+@@ -1044,6 +1044,8 @@ struct mtk_reg_map {
* the extra setup for those pins used by GMAC.
* @hash_offset Flow table hash offset.
* @foe_entry_size Foe table entry size.
* @txd_size Tx DMA descriptor size.
* @rxd_size Rx DMA descriptor size.
* @rx_irq_done_mask Rx irq done register mask.
-@@ -1054,6 +1056,7 @@ struct mtk_soc_data {
+@@ -1061,6 +1063,7 @@ struct mtk_soc_data {
u8 hash_offset;
u16 foe_entry_size;
netdev_features_t hw_features;
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1830,9 +1830,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1851,9 +1851,7 @@ static int mtk_poll_rx(struct napi_struc
while (done < budget) {
unsigned int pktlen, *rxdcsum;
dma_addr_t dma_addr;
u32 hash, reason;
int mac = 0;
-@@ -1967,36 +1965,21 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1988,36 +1986,21 @@ static int mtk_poll_rx(struct napi_struc
skb_checksum_none_assert(skb);
skb->protocol = eth_type_trans(skb, netdev);
skb_record_rx_queue(skb, 0);
napi_gro_receive(napi, skb);
-@@ -2811,29 +2794,11 @@ static netdev_features_t mtk_fix_feature
+@@ -2832,29 +2815,11 @@ static netdev_features_t mtk_fix_feature
static int mtk_set_features(struct net_device *dev, netdev_features_t features)
{
return 0;
}
-@@ -3147,30 +3112,6 @@ static int mtk_open(struct net_device *d
+@@ -3168,30 +3133,6 @@ static int mtk_open(struct net_device *d
struct mtk_eth *eth = mac->hw;
int i, err;
err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
if (err) {
netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
-@@ -3211,6 +3152,35 @@ static int mtk_open(struct net_device *d
+@@ -3232,6 +3173,35 @@ static int mtk_open(struct net_device *d
phylink_start(mac->phylink);
netif_tx_start_all_queues(dev);
return 0;
}
-@@ -3695,10 +3665,9 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3716,10 +3686,9 @@ static int mtk_hw_init(struct mtk_eth *e
if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
/* set interrupt delays based on current Net DIM sample */
mtk_dim_rx(ð->rx_dim.work);
-@@ -4336,7 +4305,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4357,7 +4326,7 @@ static int mtk_add_mac(struct mtk_eth *e
eth->netdev[id]->hw_features |= NETIF_F_LRO;
eth->netdev[id]->vlan_features = eth->soc->hw_features &
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1403,12 +1403,28 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1424,12 +1424,28 @@ static void mtk_wake_queue(struct mtk_et
}
}
bool gso = false;
int tx_num;
-@@ -1430,6 +1446,18 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1451,6 +1467,18 @@ static netdev_tx_t mtk_start_xmit(struct
return NETDEV_TX_BUSY;
}
/* TSO: fill MSS info in tcp checksum field */
if (skb_is_gso(skb)) {
if (skb_cow_head(skb, 0)) {
-@@ -1445,8 +1473,14 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1466,8 +1494,14 @@ static netdev_tx_t mtk_start_xmit(struct
}
}
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1357,6 +1357,9 @@ int mtk_gmac_rgmii_path_setup(struct mtk
+@@ -1364,6 +1364,9 @@ int mtk_gmac_rgmii_path_setup(struct mtk
int mtk_eth_offload_init(struct mtk_eth *eth);
int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
void *type_data);
ret = mtk_mdio_busy_wait(eth);
if (ret < 0)
-@@ -727,6 +770,7 @@ static int mtk_mdio_init(struct mtk_eth
+@@ -729,6 +772,7 @@ static int mtk_mdio_init(struct mtk_eth
eth->mii_bus->name = "mdio";
eth->mii_bus->read = mtk_mdio_read;
eth->mii_bus->write = mtk_mdio_write;
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -369,9 +369,12 @@
+@@ -376,9 +376,12 @@
#define PHY_IAC_ADDR_MASK GENMASK(24, 20)
#define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x))
#define PHY_IAC_CMD_MASK GENMASK(19, 18)
projects / openwrt / staging / dedeckeh.git / commitdiff