--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Xiaomi AX9000";
+ compatible = "xiaomi,ax9000", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ led-boot = &led_system_yellow;
+ led-failsafe = &led_system_yellow;
+ led-running = &led_system_blue;
+ led-upgrade = &led_system_yellow;
+ label-mac-device = &dp5;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " root=/dev/ubiblock0_0";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps {
+ label = "wps"; /* Labeled Mesh on the device */
+ gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_system_blue: system-blue {
+ label = "blue:system";
+ gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+
+ led_system_yellow: system-yellow {
+ label = "yellow:system";
+ gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_YELLOW>;
+ };
+
+ network-yellow {
+ label = "yellow:network";
+ gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_YELLOW>;
+ };
+
+ network-blue {
+ label = "blue:network";
+ gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+
+ top-red {
+ label = "red:top";
+ gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ default-state = "keep";
+ };
+
+ top-green {
+ label = "green:top";
+ gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "keep";
+ };
+
+ top-blue {
+ label = "blue:top";
+ gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "keep";
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ i2c_pins: i2c-pins {
+ pins = "gpio0", "gpio2";
+ function = "blsp5_i2c";
+ drive-strength = <8>;
+ bias-disable;
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&blsp1_i2c6 {
+ status = "okay";
+
+ pinctrl-0 = <&i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&prng {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ /*
+ * Bootloader will find the NAND DT node by the compatible and
+ * then "fixup" it by adding the partitions from the SMEM table
+ * using the legacy bindings thus making it impossible for us
+ * to change the partition table or utilize NVMEM for calibration.
+ * So add a dummy partitions node that bootloader will populate
+ * and set it as disabled so the kernel ignores it instead of
+ * printing warnings due to the broken way bootloader adds the
+ * partitions.
+ */
+ partitions {
+ status = "disabled";
+ };
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:sbl1";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "0:mibib";
+ reg = <0x100000 0x100000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "0:bootconfig";
+ reg = <0x200000 0x80000>;
+ read-only;
+ };
+
+ partition@280000 {
+ label = "0:bootconfig1";
+ reg = <0x280000 0x80000>;
+ read-only;
+ };
+
+ partition@300000 {
+ label = "0:qsee";
+ reg = <0x300000 0x300000>;
+ read-only;
+ };
+
+ partition@600000 {
+ label = "0:qsee_1";
+ reg = <0x600000 0x300000>;
+ read-only;
+ };
+
+ partition@900000 {
+ label = "0:devcfg";
+ reg = <0x900000 0x80000>;
+ read-only;
+ };
+
+ partition@980000 {
+ label = "0:devcfg_1";
+ reg = <0x980000 0x80000>;
+ read-only;
+ };
+
+ partition@a00000 {
+ label = "0:apdp";
+ reg = <0xa00000 0x80000>;
+ read-only;
+ };
+
+ partition@a80000 {
+ label = "0:apdp_1";
+ reg = <0xa80000 0x80000>;
+ read-only;
+ };
+
+ partition@b00000 {
+ label = "0:rpm";
+ reg = <0xb00000 0x80000>;
+ read-only;
+ };
+
+ partition@b80000 {
+ label = "0:rpm_1";
+ reg = <0xb80000 0x80000>;
+ read-only;
+ };
+
+ partition@c00000 {
+ label = "0:cdt";
+ reg = <0xc00000 0x80000>;
+ read-only;
+ };
+
+ partition@c80000 {
+ label = "0:cdt_1";
+ reg = <0xc80000 0x80000>;
+ read-only;
+ };
+
+ partition@d00000 {
+ label = "0:appsblenv";
+ reg = <0xd00000 0x80000>;
+ };
+
+ partition@d80000 {
+ label = "0:appsbl";
+ reg = <0xd80000 0x100000>;
+ read-only;
+ };
+
+ partition@e80000 {
+ label = "0:appsbl_1";
+ reg = <0xe80000 0x100000>;
+ read-only;
+ };
+
+ partition@f80000 {
+ label = "0:art";
+ reg = <0xf80000 0x80000>;
+ read-only;
+
+ compatible = "nvmem-cells";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_dp1: macaddr@0 {
+ reg = <0x0 0x6>;
+ };
+
+ macaddr_dp2: macaddr@6 {
+ reg = <0x6 0x6>;
+ };
+
+ macaddr_dp3: macaddr@c {
+ reg = <0xc 0x6>;
+ };
+
+ macaddr_dp4: macaddr@12 {
+ reg = <0x12 0x6>;
+ };
+
+ macaddr_dp5: macaddr@18 {
+ reg = <0x18 0x6>;
+ };
+
+ caldata_qca9889: caldata@4d000 {
+ reg = <0x4d000 0x844>;
+ };
+ };
+
+ partition@1000000 {
+ label = "bdata";
+ reg = <0x1000000 0x80000>;
+ };
+
+ partition@1080000 {
+ /* This is crash + crash_syslog parts combined */
+ label = "pstore";
+ reg = <0x1080000 0x100000>;
+ };
+
+ partition@1180000 {
+ label = "ubi_kernel";
+ reg = <0x1180000 0x3800000>;
+ };
+
+ partition@4980000 {
+ label = "rootfs";
+ reg = <0x4980000 0xb680000>;
+ };
+ };
+ };
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+ qca8075_0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ qca8075_1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+
+ qca8081: ethernet-phy@24 {
+ compatible = "ethernet-phy-id004d.d101";
+ reg = <24>;
+ reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&switch {
+ status = "okay";
+
+ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
+ switch_lan_bmp = <0x1e>; /* lan port bitmap */
+ switch_wan_bmp = <0x20>; /* wan port bitmap */
+ switch_mac_mode = <0xb>; /* mac mode for uniphy instance0*/
+ switch_mac_mode1 = <0xc>; /* mac mode for uniphy instance1*/
+ switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
+ bm_tick_mode = <0>; /* bm tick mode */
+ tm_tick_mode = <0>; /* tm tick mode */
+
+ qcom,port_phyinfo {
+ port@0 {
+ port_id = <1>;
+ phy_address = <0>;
+ };
+ port@1 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+ port@2 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+ port@3 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+ port@4 {
+ port_id = <5>;
+ phy_address = <24>;
+ port_mac_sel = "QGMAC_PORT";
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp1 {
+ status = "okay";
+ phy-handle = <&qca8075_0>;
+ label = "lan4";
+ nvmem-cells = <&macaddr_dp1>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp2 {
+ status = "okay";
+ phy-handle = <&qca8075_1>;
+ label = "lan3";
+ nvmem-cells = <&macaddr_dp2>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp3 {
+ status = "okay";
+ phy-handle = <&qca8075_2>;
+ label = "lan2";
+ nvmem-cells = <&macaddr_dp3>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp4 {
+ status = "okay";
+ phy-handle = <&qca8075_3>;
+ label = "lan1";
+ nvmem-cells = <&macaddr_dp4>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp5 {
+ status = "okay";
+ phy-handle = <&qca8081>;
+ label = "wan";
+ nvmem-cells = <&macaddr_dp5>;
+ nvmem-cell-names = "mac-address";
+};
+
+&pcie_qmp0 {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
+
+ bridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi@1,0 {
+ status = "okay";
+
+ /* ath11k has no DT compatible for PCI cards */
+ compatible = "pci17cb,1104";
+ reg = <0x00010000 0 0 0 0>;
+
+ qcom,ath11k-calibration-variant = "Xiaomi-AX9000";
+ };
+ };
+};
+
+&pcie_qmp1 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>;
+
+ bridge@1,0 {
+ reg = <0x00010000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi@1,0 {
+ status = "okay";
+
+ compatible = "qcom,ath10k";
+ reg = <0x00010000 0 0 0 0>;
+
+ qcom,ath10k-calibration-variant = "Xiaomi-AX9000";
+ nvmem-cell-names = "calibration";
+ nvmem-cells = <&caldata_qca9889>;
+ };
+ };
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "Xiaomi-AX9000";
+};
projects / openwrt / staging / dedeckeh.git / commitdiff