f98d7ec3da68f223b4e34f7a92562f919412f34a
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
15 #include <linux/module.h>
17 #include <asm/mach-ralink/ralink_regs.h>
19 #include "mtk_eth_soc.h"
20 #include "mdio_rt2880.h"
22 static const u16 rt5350_reg_table
[FE_REG_COUNT
] = {
23 [FE_REG_PDMA_GLO_CFG
] = RT5350_PDMA_GLO_CFG
,
24 [FE_REG_PDMA_RST_CFG
] = RT5350_PDMA_RST_CFG
,
25 [FE_REG_DLY_INT_CFG
] = RT5350_DLY_INT_CFG
,
26 [FE_REG_TX_BASE_PTR0
] = RT5350_TX_BASE_PTR0
,
27 [FE_REG_TX_MAX_CNT0
] = RT5350_TX_MAX_CNT0
,
28 [FE_REG_TX_CTX_IDX0
] = RT5350_TX_CTX_IDX0
,
29 [FE_REG_TX_DTX_IDX0
] = RT5350_TX_DTX_IDX0
,
30 [FE_REG_RX_BASE_PTR0
] = RT5350_RX_BASE_PTR0
,
31 [FE_REG_RX_MAX_CNT0
] = RT5350_RX_MAX_CNT0
,
32 [FE_REG_RX_CALC_IDX0
] = RT5350_RX_CALC_IDX0
,
33 [FE_REG_RX_DRX_IDX0
] = RT5350_RX_DRX_IDX0
,
34 [FE_REG_FE_INT_ENABLE
] = RT5350_FE_INT_ENABLE
,
35 [FE_REG_FE_INT_STATUS
] = RT5350_FE_INT_STATUS
,
36 [FE_REG_FE_RST_GL
] = 0,
37 [FE_REG_FE_DMA_VID_BASE
] = 0,
40 static void rt305x_init_data(struct fe_soc_data
*data
,
41 struct net_device
*netdev
)
43 struct fe_priv
*priv
= netdev_priv(netdev
);
45 priv
->flags
= FE_FLAG_PADDING_64B
| FE_FLAG_PADDING_BUG
|
46 FE_FLAG_CALIBRATE_CLK
| FE_FLAG_HAS_SWITCH
;
47 netdev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
|
48 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_TX
;
51 static int rt3050_fwd_config(struct fe_priv
*priv
)
55 if (ralink_soc
!= RT305X_SOC_RT3052
) {
56 ret
= fe_set_clock_cycle(priv
);
62 if (ralink_soc
!= RT305X_SOC_RT3352
)
63 fe_w32(FE_PSE_FQFC_CFG_INIT
, FE_PSE_FQ_CFG
);
69 static void rt5350_init_data(struct fe_soc_data
*data
,
70 struct net_device
*netdev
)
72 struct fe_priv
*priv
= netdev_priv(netdev
);
74 priv
->flags
= FE_FLAG_HAS_SWITCH
;
75 netdev
->hw_features
= NETIF_F_SG
| NETIF_F_RXCSUM
;
78 static void rt5350_set_mac(struct fe_priv
*priv
, unsigned char *mac
)
82 spin_lock_irqsave(&priv
->page_lock
, flags
);
83 fe_w32((mac
[0] << 8) | mac
[1], RT5350_SDM_MAC_ADRH
);
84 fe_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
86 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
89 static void rt5350_rxcsum_config(bool enable
)
92 fe_w32(fe_r32(RT5350_SDM_CFG
) | (RT5350_SDM_ICS_EN
|
93 RT5350_SDM_TCS_EN
| RT5350_SDM_UCS_EN
),
96 fe_w32(fe_r32(RT5350_SDM_CFG
) & ~(RT5350_SDM_ICS_EN
|
97 RT5350_SDM_TCS_EN
| RT5350_SDM_UCS_EN
),
101 static int rt5350_fwd_config(struct fe_priv
*priv
)
103 struct net_device
*dev
= priv_netdev(priv
);
105 rt5350_rxcsum_config((dev
->features
& NETIF_F_RXCSUM
));
110 static void rt5350_tx_dma(struct fe_tx_dma
*txd
)
115 static struct fe_soc_data rt3050_data
= {
116 .init_data
= rt305x_init_data
,
117 .fwd_config
= rt3050_fwd_config
,
118 .pdma_glo_cfg
= FE_PDMA_SIZE_8DWORDS
,
119 .checksum_bit
= RX_DMA_L4VALID
,
120 .rx_int
= FE_RX_DONE_INT
,
121 .tx_int
= FE_TX_DONE_INT
,
122 .status_int
= FE_CNT_GDM_AF
,
125 static struct fe_soc_data rt5350_data
= {
126 .init_data
= rt5350_init_data
,
127 .reg_table
= rt5350_reg_table
,
128 .set_mac
= rt5350_set_mac
,
129 .fwd_config
= rt5350_fwd_config
,
130 .tx_dma
= rt5350_tx_dma
,
131 .pdma_glo_cfg
= FE_PDMA_SIZE_8DWORDS
,
132 .checksum_bit
= RX_DMA_L4VALID
,
133 .rx_int
= RT5350_RX_DONE_INT
,
134 .tx_int
= RT5350_TX_DONE_INT
,
137 const struct of_device_id of_fe_match
[] = {
138 { .compatible
= "ralink,rt3050-eth", .data
= &rt3050_data
},
139 { .compatible
= "ralink,rt5350-eth", .data
= &rt5350_data
},
143 MODULE_DEVICE_TABLE(of
, of_fe_match
);