target/linux/layerscape/patches-4.9/812-mmc-layerscape-support.patch

   1 From b31046c51c72232363711f0c623df08bf28c37e4 Mon Sep 17 00:00:00 2001
   2 From: Yangbo Lu <yangbo.lu@nxp.com>
   3 Date: Mon, 25 Sep 2017 12:21:30 +0800
   4 Subject: [PATCH] mmc: layerscape support
   5
   6 This is a integrated patch for layerscape mmc support.
   7
   8 Adrian Hunter <adrian.hunter@intel.com>
   9 Jaehoon Chung <jh80.chung@samsung.com>
  10 Masahiro Yamada <yamada.masahiro@socionext.com>
  11 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  12 ---
  13  drivers/mmc/host/Kconfig          |   1 +
  14  drivers/mmc/host/sdhci-esdhc.h    |  52 +++++---
  15  drivers/mmc/host/sdhci-of-esdhc.c | 251 ++++++++++++++++++++++++++++++++++++--
  16  drivers/mmc/host/sdhci.c          |  45 ++++---
  17  drivers/mmc/host/sdhci.h          |   3 +
  18  5 files changed, 306 insertions(+), 46 deletions(-)
  19
  20 --- a/drivers/mmc/host/Kconfig
  21 +++ b/drivers/mmc/host/Kconfig
  22 @@ -144,6 +144,7 @@ config MMC_SDHCI_OF_ESDHC
  23         depends on MMC_SDHCI_PLTFM
  24         depends on PPC || ARCH_MXC || ARCH_LAYERSCAPE
  25         select MMC_SDHCI_IO_ACCESSORS
  26 +       select FSL_GUTS
  27         help
  28           This selects the Freescale eSDHC controller support.
  29
  30 --- a/drivers/mmc/host/sdhci-esdhc.h
  31 +++ b/drivers/mmc/host/sdhci-esdhc.h
  32 @@ -24,30 +24,46 @@
  33                                 SDHCI_QUIRK_PIO_NEEDS_DELAY | \
  34                                 SDHCI_QUIRK_NO_HISPD_BIT)
  35
  36 -#define ESDHC_PROCTL           0x28
  37 -
  38 -#define ESDHC_SYSTEM_CONTROL   0x2c
  39 -#define ESDHC_CLOCK_MASK       0x0000fff0
  40 -#define ESDHC_PREDIV_SHIFT     8
  41 -#define ESDHC_DIVIDER_SHIFT    4
  42 -#define ESDHC_CLOCK_PEREN      0x00000004
  43 -#define ESDHC_CLOCK_HCKEN      0x00000002
  44 -#define ESDHC_CLOCK_IPGEN      0x00000001
  45 -
  46  /* pltfm-specific */
  47  #define ESDHC_HOST_CONTROL_LE  0x20
  48
  49  /*
  50 - * P2020 interpretation of the SDHCI_HOST_CONTROL register
  51 + * eSDHC register definition
  52   */
  53 -#define ESDHC_CTRL_4BITBUS          (0x1 << 1)
  54 -#define ESDHC_CTRL_8BITBUS          (0x2 << 1)
  55 -#define ESDHC_CTRL_BUSWIDTH_MASK    (0x3 << 1)
  56 -
  57 -/* OF-specific */
  58 -#define ESDHC_DMA_SYSCTL       0x40c
  59 -#define ESDHC_DMA_SNOOP                0x00000040
  60
  61 -#define ESDHC_HOST_CONTROL_RES 0x01
  62 +/* Present State Register */
  63 +#define ESDHC_PRSSTAT                  0x24
  64 +#define ESDHC_CLOCK_STABLE             0x00000008
  65 +
  66 +/* Protocol Control Register */
  67 +#define ESDHC_PROCTL                   0x28
  68 +#define ESDHC_VOLT_SEL                 0x00000400
  69 +#define ESDHC_CTRL_4BITBUS             (0x1 << 1)
  70 +#define ESDHC_CTRL_8BITBUS             (0x2 << 1)
  71 +#define ESDHC_CTRL_BUSWIDTH_MASK       (0x3 << 1)
  72 +#define ESDHC_HOST_CONTROL_RES         0x01
  73 +
  74 +/* System Control Register */
  75 +#define ESDHC_SYSTEM_CONTROL           0x2c
  76 +#define ESDHC_CLOCK_MASK               0x0000fff0
  77 +#define ESDHC_PREDIV_SHIFT             8
  78 +#define ESDHC_DIVIDER_SHIFT            4
  79 +#define ESDHC_CLOCK_SDCLKEN            0x00000008
  80 +#define ESDHC_CLOCK_PEREN              0x00000004
  81 +#define ESDHC_CLOCK_HCKEN              0x00000002
  82 +#define ESDHC_CLOCK_IPGEN              0x00000001
  83 +
  84 +/* Host Controller Capabilities Register 2 */
  85 +#define ESDHC_CAPABILITIES_1           0x114
  86 +
  87 +/* Tuning Block Control Register */
  88 +#define ESDHC_TBCTL                    0x120
  89 +#define ESDHC_TB_EN                    0x00000004
  90 +
  91 +/* Control Register for DMA transfer */
  92 +#define ESDHC_DMA_SYSCTL               0x40c
  93 +#define ESDHC_PERIPHERAL_CLK_SEL       0x00080000
  94 +#define ESDHC_FLUSH_ASYNC_FIFO         0x00040000
  95 +#define ESDHC_DMA_SNOOP                        0x00000040
  96
  97  #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
  98 --- a/drivers/mmc/host/sdhci-of-esdhc.c
  99 +++ b/drivers/mmc/host/sdhci-of-esdhc.c
 100 @@ -16,8 +16,12 @@
 101  #include <linux/err.h>
 102  #include <linux/io.h>
 103  #include <linux/of.h>
 104 +#include <linux/of_address.h>
 105  #include <linux/delay.h>
 106  #include <linux/module.h>
 107 +#include <linux/sys_soc.h>
 108 +#include <linux/clk.h>
 109 +#include <linux/ktime.h>
 110  #include <linux/mmc/host.h>
 111  #include "sdhci-pltfm.h"
 112  #include "sdhci-esdhc.h"
 113 @@ -28,8 +32,12 @@
 114  struct sdhci_esdhc {
 115         u8 vendor_ver;
 116         u8 spec_ver;
 117 +       bool quirk_incorrect_hostver;
 118 +       unsigned int peripheral_clock;
 119  };
 120
 121 +static void esdhc_clock_enable(struct sdhci_host *host, bool enable);
 122 +
 123  /**
 124   * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
 125   *                    to make it compatible with SD spec.
 126 @@ -80,6 +88,17 @@ static u32 esdhc_readl_fixup(struct sdhc
 127                 return ret;
 128         }
 129
 130 +       /*
 131 +        * DTS properties of mmc host are used to enable each speed mode
 132 +        * according to soc and board capability. So clean up
 133 +        * SDR50/SDR104/DDR50 support bits here.
 134 +        */
 135 +       if (spec_reg == SDHCI_CAPABILITIES_1) {
 136 +               ret = value & (~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
 137 +                                SDHCI_SUPPORT_DDR50));
 138 +               return ret;
 139 +       }
 140 +
 141         ret = value;
 142         return ret;
 143  }
 144 @@ -87,6 +106,8 @@ static u32 esdhc_readl_fixup(struct sdhc
 145  static u16 esdhc_readw_fixup(struct sdhci_host *host,
 146                                      int spec_reg, u32 value)
 147  {
 148 +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 149 +       struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
 150         u16 ret;
 151         int shift = (spec_reg & 0x2) * 8;
 152
 153 @@ -94,6 +115,12 @@ static u16 esdhc_readw_fixup(struct sdhc
 154                 ret = value & 0xffff;
 155         else
 156                 ret = (value >> shift) & 0xffff;
 157 +       /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect
 158 +        * vendor version and spec version information.
 159 +        */
 160 +       if ((spec_reg == SDHCI_HOST_VERSION) &&
 161 +           (esdhc->quirk_incorrect_hostver))
 162 +               ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
 163         return ret;
 164  }
 165
 166 @@ -235,7 +262,11 @@ static u32 esdhc_be_readl(struct sdhci_h
 167         u32 ret;
 168         u32 value;
 169
 170 -       value = ioread32be(host->ioaddr + reg);
 171 +       if (reg == SDHCI_CAPABILITIES_1)
 172 +               value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1);
 173 +       else
 174 +               value = ioread32be(host->ioaddr + reg);
 175 +
 176         ret = esdhc_readl_fixup(host, reg, value);
 177
 178         return ret;
 179 @@ -246,7 +277,11 @@ static u32 esdhc_le_readl(struct sdhci_h
 180         u32 ret;
 181         u32 value;
 182
 183 -       value = ioread32(host->ioaddr + reg);
 184 +       if (reg == SDHCI_CAPABILITIES_1)
 185 +               value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1);
 186 +       else
 187 +               value = ioread32(host->ioaddr + reg);
 188 +
 189         ret = esdhc_readl_fixup(host, reg, value);
 190
 191         return ret;
 192 @@ -404,15 +439,25 @@ static int esdhc_of_enable_dma(struct sd
 193  static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
 194  {
 195         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 196 +       struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
 197
 198 -       return pltfm_host->clock;
 199 +       if (esdhc->peripheral_clock)
 200 +               return esdhc->peripheral_clock;
 201 +       else
 202 +               return pltfm_host->clock;
 203  }
 204
 205  static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
 206  {
 207         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 208 +       struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
 209 +       unsigned int clock;
 210
 211 -       return pltfm_host->clock / 256 / 16;
 212 +       if (esdhc->peripheral_clock)
 213 +               clock = esdhc->peripheral_clock;
 214 +       else
 215 +               clock = pltfm_host->clock;
 216 +       return clock / 256 / 16;
 217  }
 218
 219  static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
 220 @@ -421,17 +466,34 @@ static void esdhc_of_set_clock(struct sd
 221         struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
 222         int pre_div = 1;
 223         int div = 1;
 224 +       ktime_t timeout;
 225         u32 temp;
 226
 227         host->mmc->actual_clock = 0;
 228
 229 -       if (clock == 0)
 230 +       if (clock == 0) {
 231 +               esdhc_clock_enable(host, false);
 232                 return;
 233 +       }
 234
 235         /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
 236         if (esdhc->vendor_ver < VENDOR_V_23)
 237                 pre_div = 2;
 238
 239 +       /*
 240 +        * Limit SD clock to 167MHz for ls1046a according to its datasheet
 241 +        */
 242 +       if (clock > 167000000 &&
 243 +           of_find_compatible_node(NULL, NULL, "fsl,ls1046a-esdhc"))
 244 +               clock = 167000000;
 245 +
 246 +       /*
 247 +        * Limit SD clock to 125MHz for ls1012a according to its datasheet
 248 +        */
 249 +       if (clock > 125000000 &&
 250 +           of_find_compatible_node(NULL, NULL, "fsl,ls1012a-esdhc"))
 251 +               clock = 125000000;
 252 +
 253         /* Workaround to reduce the clock frequency for p1010 esdhc */
 254         if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
 255                 if (clock > 20000000)
 256 @@ -441,8 +503,8 @@ static void esdhc_of_set_clock(struct sd
 257         }
 258
 259         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 260 -       temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 261 -               | ESDHC_CLOCK_MASK);
 262 +       temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
 263 +                 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
 264         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 265
 266         while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
 267 @@ -462,7 +524,20 @@ static void esdhc_of_set_clock(struct sd
 268                 | (div << ESDHC_DIVIDER_SHIFT)
 269                 | (pre_div << ESDHC_PREDIV_SHIFT));
 270         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 271 -       mdelay(1);
 272 +
 273 +       /* Wait max 20 ms */
 274 +       timeout = ktime_add_ms(ktime_get(), 20);
 275 +       while (!(sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)) {
 276 +               if (ktime_after(ktime_get(), timeout)) {
 277 +                       pr_err("%s: Internal clock never stabilised.\n",
 278 +                               mmc_hostname(host->mmc));
 279 +                       return;
 280 +               }
 281 +               udelay(10);
 282 +       }
 283 +
 284 +       temp |= ESDHC_CLOCK_SDCLKEN;
 285 +       sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 286  }
 287
 288  static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
 289 @@ -487,6 +562,33 @@ static void esdhc_pltfm_set_bus_width(st
 290         sdhci_writel(host, ctrl, ESDHC_PROCTL);
 291  }
 292
 293 +static void esdhc_clock_enable(struct sdhci_host *host, bool enable)
 294 +{
 295 +       u32 val;
 296 +       ktime_t timeout;
 297 +
 298 +       val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 299 +
 300 +       if (enable)
 301 +               val |= ESDHC_CLOCK_SDCLKEN;
 302 +       else
 303 +               val &= ~ESDHC_CLOCK_SDCLKEN;
 304 +
 305 +       sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
 306 +
 307 +       /* Wait max 20 ms */
 308 +       timeout = ktime_add_ms(ktime_get(), 20);
 309 +       val = ESDHC_CLOCK_STABLE;
 310 +       while (!(sdhci_readl(host, ESDHC_PRSSTAT) & val)) {
 311 +               if (ktime_after(ktime_get(), timeout)) {
 312 +                       pr_err("%s: Internal clock never stabilised.\n",
 313 +                               mmc_hostname(host->mmc));
 314 +                       break;
 315 +               }
 316 +               udelay(10);
 317 +       }
 318 +}
 319 +
 320  static void esdhc_reset(struct sdhci_host *host, u8 mask)
 321  {
 322         sdhci_reset(host, mask);
 323 @@ -495,6 +597,95 @@ static void esdhc_reset(struct sdhci_hos
 324         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 325  }
 326
 327 +/* The SCFG, Supplemental Configuration Unit, provides SoC specific
 328 + * configuration and status registers for the device. There is a
 329 + * SDHC IO VSEL control register on SCFG for some platforms. It's
 330 + * used to support SDHC IO voltage switching.
 331 + */
 332 +static const struct of_device_id scfg_device_ids[] = {
 333 +       { .compatible = "fsl,t1040-scfg", },
 334 +       { .compatible = "fsl,ls1012a-scfg", },
 335 +       { .compatible = "fsl,ls1046a-scfg", },
 336 +       {}
 337 +};
 338 +
 339 +/* SDHC IO VSEL control register definition */
 340 +#define SCFG_SDHCIOVSELCR      0x408
 341 +#define SDHCIOVSELCR_TGLEN     0x80000000
 342 +#define SDHCIOVSELCR_VSELVAL   0x60000000
 343 +#define SDHCIOVSELCR_SDHC_VS   0x00000001
 344 +
 345 +static int esdhc_signal_voltage_switch(struct mmc_host *mmc,
 346 +                                      struct mmc_ios *ios)
 347 +{
 348 +       struct sdhci_host *host = mmc_priv(mmc);
 349 +       struct device_node *scfg_node;
 350 +       void __iomem *scfg_base = NULL;
 351 +       u32 sdhciovselcr;
 352 +       u32 val;
 353 +
 354 +       /*
 355 +        * Signal Voltage Switching is only applicable for Host Controllers
 356 +        * v3.00 and above.
 357 +        */
 358 +       if (host->version < SDHCI_SPEC_300)
 359 +               return 0;
 360 +
 361 +       val = sdhci_readl(host, ESDHC_PROCTL);
 362 +
 363 +       switch (ios->signal_voltage) {
 364 +       case MMC_SIGNAL_VOLTAGE_330:
 365 +               val &= ~ESDHC_VOLT_SEL;
 366 +               sdhci_writel(host, val, ESDHC_PROCTL);
 367 +               return 0;
 368 +       case MMC_SIGNAL_VOLTAGE_180:
 369 +               scfg_node = of_find_matching_node(NULL, scfg_device_ids);
 370 +               if (scfg_node)
 371 +                       scfg_base = of_iomap(scfg_node, 0);
 372 +               if (scfg_base) {
 373 +                       sdhciovselcr = SDHCIOVSELCR_TGLEN |
 374 +                                      SDHCIOVSELCR_VSELVAL;
 375 +                       iowrite32be(sdhciovselcr,
 376 +                               scfg_base + SCFG_SDHCIOVSELCR);
 377 +
 378 +                       val |= ESDHC_VOLT_SEL;
 379 +                       sdhci_writel(host, val, ESDHC_PROCTL);
 380 +                       mdelay(5);
 381 +
 382 +                       sdhciovselcr = SDHCIOVSELCR_TGLEN |
 383 +                                      SDHCIOVSELCR_SDHC_VS;
 384 +                       iowrite32be(sdhciovselcr,
 385 +                               scfg_base + SCFG_SDHCIOVSELCR);
 386 +                       iounmap(scfg_base);
 387 +               } else {
 388 +                       val |= ESDHC_VOLT_SEL;
 389 +                       sdhci_writel(host, val, ESDHC_PROCTL);
 390 +               }
 391 +               return 0;
 392 +       default:
 393 +               return 0;
 394 +       }
 395 +}
 396 +
 397 +static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
 398 +{
 399 +       struct sdhci_host *host = mmc_priv(mmc);
 400 +       u32 val;
 401 +
 402 +       /* Use tuning block for tuning procedure */
 403 +       esdhc_clock_enable(host, false);
 404 +       val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
 405 +       val |= ESDHC_FLUSH_ASYNC_FIFO;
 406 +       sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
 407 +
 408 +       val = sdhci_readl(host, ESDHC_TBCTL);
 409 +       val |= ESDHC_TB_EN;
 410 +       sdhci_writel(host, val, ESDHC_TBCTL);
 411 +       esdhc_clock_enable(host, true);
 412 +
 413 +       return sdhci_execute_tuning(mmc, opcode);
 414 +}
 415 +
 416  #ifdef CONFIG_PM_SLEEP
 417  static u32 esdhc_proctl;
 418  static int esdhc_of_suspend(struct device *dev)
 419 @@ -575,10 +766,19 @@ static const struct sdhci_pltfm_data sdh
 420         .ops = &sdhci_esdhc_le_ops,
 421  };
 422
 423 +static struct soc_device_attribute soc_incorrect_hostver[] = {
 424 +       { .family = "QorIQ T4240", .revision = "1.0", },
 425 +       { .family = "QorIQ T4240", .revision = "2.0", },
 426 +       { },
 427 +};
 428 +
 429  static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
 430  {
 431         struct sdhci_pltfm_host *pltfm_host;
 432         struct sdhci_esdhc *esdhc;
 433 +       struct device_node *np;
 434 +       struct clk *clk;
 435 +       u32 val;
 436         u16 host_ver;
 437
 438         pltfm_host = sdhci_priv(host);
 439 @@ -588,6 +788,36 @@ static void esdhc_init(struct platform_d
 440         esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
 441                              SDHCI_VENDOR_VER_SHIFT;
 442         esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
 443 +       if (soc_device_match(soc_incorrect_hostver))
 444 +               esdhc->quirk_incorrect_hostver = true;
 445 +       else
 446 +               esdhc->quirk_incorrect_hostver = false;
 447 +
 448 +       np = pdev->dev.of_node;
 449 +       clk = of_clk_get(np, 0);
 450 +       if (!IS_ERR(clk)) {
 451 +               /*
 452 +                * esdhc->peripheral_clock would be assigned with a value
 453 +                * which is eSDHC base clock when use periperal clock.
 454 +                * For ls1046a, the clock value got by common clk API is
 455 +                * peripheral clock while the eSDHC base clock is 1/2
 456 +                * peripheral clock.
 457 +                */
 458 +               if (of_device_is_compatible(np, "fsl,ls1046a-esdhc"))
 459 +                       esdhc->peripheral_clock = clk_get_rate(clk) / 2;
 460 +               else
 461 +                       esdhc->peripheral_clock = clk_get_rate(clk);
 462 +
 463 +               clk_put(clk);
 464 +       }
 465 +
 466 +       if (esdhc->peripheral_clock) {
 467 +               esdhc_clock_enable(host, false);
 468 +               val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
 469 +               val |= ESDHC_PERIPHERAL_CLK_SEL;
 470 +               sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
 471 +               esdhc_clock_enable(host, true);
 472 +       }
 473  }
 474
 475  static int sdhci_esdhc_probe(struct platform_device *pdev)
 476 @@ -610,6 +840,11 @@ static int sdhci_esdhc_probe(struct plat
 477         if (IS_ERR(host))
 478                 return PTR_ERR(host);
 479
 480 +       host->mmc_host_ops.start_signal_voltage_switch =
 481 +               esdhc_signal_voltage_switch;
 482 +       host->mmc_host_ops.execute_tuning = esdhc_execute_tuning;
 483 +       host->tuning_delay = 1;
 484 +
 485         esdhc_init(pdev, host);
 486
 487         sdhci_get_of_property(pdev);
 488 --- a/drivers/mmc/host/sdhci.c
 489 +++ b/drivers/mmc/host/sdhci.c
 490 @@ -1624,26 +1624,24 @@ static void sdhci_set_ios(struct mmc_hos
 491
 492         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 493
 494 -       if ((ios->timing == MMC_TIMING_SD_HS ||
 495 -            ios->timing == MMC_TIMING_MMC_HS)
 496 -           && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
 497 -               ctrl |= SDHCI_CTRL_HISPD;
 498 -       else
 499 -               ctrl &= ~SDHCI_CTRL_HISPD;
 500 +       if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
 501 +               if ((ios->timing == MMC_TIMING_SD_HS ||
 502 +                    ios->timing == MMC_TIMING_MMC_HS ||
 503 +                    ios->timing == MMC_TIMING_MMC_HS400 ||
 504 +                    ios->timing == MMC_TIMING_MMC_HS200 ||
 505 +                    ios->timing == MMC_TIMING_MMC_DDR52 ||
 506 +                    ios->timing == MMC_TIMING_UHS_SDR50 ||
 507 +                    ios->timing == MMC_TIMING_UHS_SDR104 ||
 508 +                    ios->timing == MMC_TIMING_UHS_DDR50 ||
 509 +                    ios->timing == MMC_TIMING_UHS_SDR25))
 510 +                       ctrl |= SDHCI_CTRL_HISPD;
 511 +               else
 512 +                       ctrl &= ~SDHCI_CTRL_HISPD;
 513 +       }
 514
 515         if (host->version >= SDHCI_SPEC_300) {
 516                 u16 clk, ctrl_2;
 517
 518 -               /* In case of UHS-I modes, set High Speed Enable */
 519 -               if ((ios->timing == MMC_TIMING_MMC_HS400) ||
 520 -                   (ios->timing == MMC_TIMING_MMC_HS200) ||
 521 -                   (ios->timing == MMC_TIMING_MMC_DDR52) ||
 522 -                   (ios->timing == MMC_TIMING_UHS_SDR50) ||
 523 -                   (ios->timing == MMC_TIMING_UHS_SDR104) ||
 524 -                   (ios->timing == MMC_TIMING_UHS_DDR50) ||
 525 -                   (ios->timing == MMC_TIMING_UHS_SDR25))
 526 -                       ctrl |= SDHCI_CTRL_HISPD;
 527 -
 528                 if (!host->preset_enabled) {
 529                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 530                         /*
 531 @@ -1956,7 +1954,7 @@ static int sdhci_prepare_hs400_tuning(st
 532         return 0;
 533  }
 534
 535 -static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
 536 +int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
 537  {
 538         struct sdhci_host *host = mmc_priv(mmc);
 539         u16 ctrl;
 540 @@ -2015,6 +2013,9 @@ static int sdhci_execute_tuning(struct m
 541                 return err;
 542         }
 543
 544 +       if (host->tuning_delay < 0)
 545 +       host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
 546 +
 547         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 548         ctrl |= SDHCI_CTRL_EXEC_TUNING;
 549         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
 550 @@ -2127,9 +2128,10 @@ static int sdhci_execute_tuning(struct m
 551
 552                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 553
 554 -               /* eMMC spec does not require a delay between tuning cycles */
 555 -               if (opcode == MMC_SEND_TUNING_BLOCK)
 556 -                       mdelay(1);
 557 +               /* Spec does not require a delay between tuning cycles */
 558 +               if (host->tuning_delay > 0)
 559 +               mdelay(host->tuning_delay);
 560 +
 561         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 562
 563         /*
 564 @@ -2165,6 +2167,7 @@ out_unlock:
 565         spin_unlock_irqrestore(&host->lock, flags);
 566         return err;
 567  }
 568 +EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
 569
 570  static int sdhci_select_drive_strength(struct mmc_card *card,
 571                                        unsigned int max_dtr, int host_drv,
 572 @@ -2997,6 +3000,8 @@ struct sdhci_host *sdhci_alloc_host(stru
 573
 574         host->flags = SDHCI_SIGNALING_330;
 575
 576 +       host->tuning_delay = -1;
 577 +
 578         return host;
 579  }
 580
 581 --- a/drivers/mmc/host/sdhci.h
 582 +++ b/drivers/mmc/host/sdhci.h
 583 @@ -524,6 +524,8 @@ struct sdhci_host {
 584  #define SDHCI_TUNING_MODE_1    0
 585  #define SDHCI_TUNING_MODE_2    1
 586  #define SDHCI_TUNING_MODE_3    2
 587 +       /* Delay (ms) between tuning commands */
 588 +       int                     tuning_delay;
 589
 590         unsigned long private[0] ____cacheline_aligned;
 591  };
 592 @@ -689,6 +691,7 @@ void sdhci_set_power_noreg(struct sdhci_
 593  void sdhci_set_bus_width(struct sdhci_host *host, int width);
 594  void sdhci_reset(struct sdhci_host *host, u8 mask);
 595  void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
 596 +int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
 597
 598  #ifdef CONFIG_PM
 599  extern int sdhci_suspend_host(struct sdhci_host *host);