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[openwrt/staging/dedeckeh.git] / target / linux / layerscape / patches-4.9 / 704-fsl-mc-layerscape-support.patch
1 From 464b4d9b8282e0f1e5040e4914505f91ce4d3750 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 12:06:25 +0800
4 Subject: [PATCH] fsl-mc: layerscape support
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 This is a integrated patch for layerscape mc-bus support.
10
11 Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
12 Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
13 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
14 Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
15 Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
16 Signed-off-by: Shiva Kerdel <shiva@exdev.nl>
17 Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
18 Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
19 Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
20 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
21 ---
22 drivers/staging/fsl-mc/bus/Kconfig | 41 +-
23 drivers/staging/fsl-mc/bus/Makefile | 10 +-
24 drivers/staging/fsl-mc/bus/dpbp-cmd.h | 80 ++
25 drivers/staging/fsl-mc/bus/dpbp.c | 450 +--------
26 drivers/staging/fsl-mc/bus/dpcon-cmd.h | 85 ++
27 drivers/staging/fsl-mc/bus/dpcon.c | 317 ++++++
28 drivers/staging/fsl-mc/bus/dpio/Makefile | 11 +
29 .../{include/dpcon-cmd.h => bus/dpio/dpio-cmd.h} | 73 +-
30 drivers/staging/fsl-mc/bus/dpio/dpio-driver.c | 296 ++++++
31 drivers/staging/fsl-mc/bus/dpio/dpio-driver.txt | 135 +++
32 drivers/staging/fsl-mc/bus/dpio/dpio-service.c | 689 +++++++++++++
33 drivers/staging/fsl-mc/bus/dpio/dpio.c | 224 +++++
34 drivers/staging/fsl-mc/bus/dpio/dpio.h | 109 ++
35 drivers/staging/fsl-mc/bus/dpio/qbman-portal.c | 1049 ++++++++++++++++++++
36 drivers/staging/fsl-mc/bus/dpio/qbman-portal.h | 662 ++++++++++++
37 drivers/staging/fsl-mc/bus/dpio/qbman_debug.c | 853 ++++++++++++++++
38 drivers/staging/fsl-mc/bus/dpio/qbman_debug.h | 136 +++
39 drivers/staging/fsl-mc/bus/dpio/qbman_private.h | 171 ++++
40 drivers/staging/fsl-mc/bus/dpmcp-cmd.h | 112 +--
41 drivers/staging/fsl-mc/bus/dpmcp.c | 374 +------
42 drivers/staging/fsl-mc/bus/dpmcp.h | 127 +--
43 drivers/staging/fsl-mc/bus/dpmng-cmd.h | 14 +-
44 drivers/staging/fsl-mc/bus/dpmng.c | 37 +-
45 drivers/staging/fsl-mc/bus/dprc-cmd.h | 82 +-
46 drivers/staging/fsl-mc/bus/dprc-driver.c | 38 +-
47 drivers/staging/fsl-mc/bus/dprc.c | 629 +-----------
48 drivers/staging/fsl-mc/bus/fsl-mc-allocator.c | 78 +-
49 drivers/staging/fsl-mc/bus/fsl-mc-bus.c | 318 +++---
50 drivers/staging/fsl-mc/bus/fsl-mc-iommu.c | 104 ++
51 drivers/staging/fsl-mc/bus/fsl-mc-msi.c | 3 +-
52 drivers/staging/fsl-mc/bus/fsl-mc-private.h | 6 +-
53 .../staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c | 11 +-
54 drivers/staging/fsl-mc/bus/mc-io.c | 4 +-
55 drivers/staging/fsl-mc/bus/mc-ioctl.h | 22 +
56 drivers/staging/fsl-mc/bus/mc-restool.c | 405 ++++++++
57 drivers/staging/fsl-mc/bus/mc-sys.c | 14 +-
58 drivers/staging/fsl-mc/include/dpaa2-fd.h | 706 +++++++++++++
59 drivers/staging/fsl-mc/include/dpaa2-global.h | 202 ++++
60 drivers/staging/fsl-mc/include/dpaa2-io.h | 190 ++++
61 drivers/staging/fsl-mc/include/dpbp-cmd.h | 185 ----
62 drivers/staging/fsl-mc/include/dpbp.h | 158 +--
63 drivers/staging/fsl-mc/include/dpcon.h | 115 +++
64 drivers/staging/fsl-mc/include/dpmng.h | 16 +-
65 drivers/staging/fsl-mc/include/dpopr.h | 110 ++
66 drivers/staging/fsl-mc/include/dprc.h | 470 +++------
67 drivers/staging/fsl-mc/include/mc-bus.h | 7 +-
68 drivers/staging/fsl-mc/include/mc-cmd.h | 44 +-
69 drivers/staging/fsl-mc/include/mc-sys.h | 3 +-
70 drivers/staging/fsl-mc/include/mc.h | 17 +-
71 49 files changed, 7380 insertions(+), 2612 deletions(-)
72 create mode 100644 drivers/staging/fsl-mc/bus/dpbp-cmd.h
73 create mode 100644 drivers/staging/fsl-mc/bus/dpcon-cmd.h
74 create mode 100644 drivers/staging/fsl-mc/bus/dpcon.c
75 create mode 100644 drivers/staging/fsl-mc/bus/dpio/Makefile
76 rename drivers/staging/fsl-mc/{include/dpcon-cmd.h => bus/dpio/dpio-cmd.h} (64%)
77 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
78 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-driver.txt
79 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-service.c
80 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio.c
81 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio.h
82 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman-portal.c
83 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman-portal.h
84 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_debug.c
85 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_debug.h
86 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_private.h
87 create mode 100644 drivers/staging/fsl-mc/bus/fsl-mc-iommu.c
88 create mode 100644 drivers/staging/fsl-mc/bus/mc-ioctl.h
89 create mode 100644 drivers/staging/fsl-mc/bus/mc-restool.c
90 create mode 100644 drivers/staging/fsl-mc/include/dpaa2-fd.h
91 create mode 100644 drivers/staging/fsl-mc/include/dpaa2-global.h
92 create mode 100644 drivers/staging/fsl-mc/include/dpaa2-io.h
93 delete mode 100644 drivers/staging/fsl-mc/include/dpbp-cmd.h
94 create mode 100644 drivers/staging/fsl-mc/include/dpcon.h
95 create mode 100644 drivers/staging/fsl-mc/include/dpopr.h
96
97 diff --git a/drivers/staging/fsl-mc/bus/Kconfig b/drivers/staging/fsl-mc/bus/Kconfig
98 index 1f959339..67847c0e 100644
99 --- a/drivers/staging/fsl-mc/bus/Kconfig
100 +++ b/drivers/staging/fsl-mc/bus/Kconfig
101 @@ -1,25 +1,40 @@
102 #
103 -# Freescale Management Complex (MC) bus drivers
104 +# DPAA2 fsl-mc bus
105 #
106 -# Copyright (C) 2014 Freescale Semiconductor, Inc.
107 +# Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
108 #
109 # This file is released under the GPLv2
110 #
111
112 config FSL_MC_BUS
113 - bool "Freescale Management Complex (MC) bus driver"
114 - depends on OF && ARM64
115 + bool "QorIQ DPAA2 fsl-mc bus driver"
116 + depends on OF && ARCH_LAYERSCAPE
117 select GENERIC_MSI_IRQ_DOMAIN
118 help
119 - Driver to enable the bus infrastructure for the Freescale
120 - QorIQ Management Complex (fsl-mc). The fsl-mc is a hardware
121 - module of the QorIQ LS2 SoCs, that does resource management
122 - for hardware building-blocks in the SoC that can be used
123 - to dynamically create networking hardware objects such as
124 - network interfaces (NICs), crypto accelerator instances,
125 - or L2 switches.
126 + Driver to enable the bus infrastructure for the QorIQ DPAA2
127 + architecture. The fsl-mc bus driver handles discovery of
128 + DPAA2 objects (which are represented as Linux devices) and
129 + binding objects to drivers.
130
131 - Only enable this option when building the kernel for
132 - Freescale QorQIQ LS2xxxx SoCs.
133 +config FSL_MC_DPIO
134 + tristate "QorIQ DPAA2 DPIO driver"
135 + depends on FSL_MC_BUS
136 + help
137 + Driver for the DPAA2 DPIO object. A DPIO provides queue and
138 + buffer management facilities for software to interact with
139 + other DPAA2 objects. This driver does not expose the DPIO
140 + objects individually, but groups them under a service layer
141 + API.
142
143 +config FSL_QBMAN_DEBUG
144 + tristate "Freescale QBMAN Debug APIs"
145 + depends on FSL_MC_DPIO
146 + help
147 + QBMan debug assistant APIs.
148
149 +config FSL_MC_RESTOOL
150 + tristate "Freescale Management Complex (MC) restool driver"
151 + depends on FSL_MC_BUS
152 + help
153 + Driver that provides kernel support for the Freescale Management
154 + Complex resource manager user-space tool.
155 diff --git a/drivers/staging/fsl-mc/bus/Makefile b/drivers/staging/fsl-mc/bus/Makefile
156 index 38716fd5..e7e2239c 100644
157 --- a/drivers/staging/fsl-mc/bus/Makefile
158 +++ b/drivers/staging/fsl-mc/bus/Makefile
159 @@ -17,4 +17,12 @@ mc-bus-driver-objs := fsl-mc-bus.o \
160 fsl-mc-msi.o \
161 irq-gic-v3-its-fsl-mc-msi.o \
162 dpmcp.o \
163 - dpbp.o
164 + dpbp.o \
165 + dpcon.o \
166 + fsl-mc-iommu.o
167 +
168 +# MC DPIO driver
169 +obj-$(CONFIG_FSL_MC_DPIO) += dpio/
170 +
171 +# MC restool kernel support
172 +obj-$(CONFIG_FSL_MC_RESTOOL) += mc-restool.o
173 diff --git a/drivers/staging/fsl-mc/bus/dpbp-cmd.h b/drivers/staging/fsl-mc/bus/dpbp-cmd.h
174 new file mode 100644
175 index 00000000..8aa65452
176 --- /dev/null
177 +++ b/drivers/staging/fsl-mc/bus/dpbp-cmd.h
178 @@ -0,0 +1,80 @@
179 +/*
180 + * Copyright 2013-2016 Freescale Semiconductor Inc.
181 + *
182 + * Redistribution and use in source and binary forms, with or without
183 + * modification, are permitted provided that the following conditions are met:
184 + * * Redistributions of source code must retain the above copyright
185 + * notice, this list of conditions and the following disclaimer.
186 + * * Redistributions in binary form must reproduce the above copyright
187 + * notice, this list of conditions and the following disclaimer in the
188 + * documentation and/or other materials provided with the distribution.
189 + * * Neither the name of the above-listed copyright holders nor the
190 + * names of any contributors may be used to endorse or promote products
191 + * derived from this software without specific prior written permission.
192 + *
193 + * ALTERNATIVELY, this software may be distributed under the terms of the
194 + * GNU General Public License ("GPL") as published by the Free Software
195 + * Foundation, either version 2 of that License or (at your option) any
196 + * later version.
197 + *
198 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
199 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
200 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
201 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
202 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
203 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
204 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
205 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
206 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
207 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
208 + * POSSIBILITY OF SUCH DAMAGE.
209 + */
210 +#ifndef _FSL_DPBP_CMD_H
211 +#define _FSL_DPBP_CMD_H
212 +
213 +/* DPBP Version */
214 +#define DPBP_VER_MAJOR 3
215 +#define DPBP_VER_MINOR 2
216 +
217 +/* Command versioning */
218 +#define DPBP_CMD_BASE_VERSION 1
219 +#define DPBP_CMD_ID_OFFSET 4
220 +
221 +#define DPBP_CMD(id) ((id << DPBP_CMD_ID_OFFSET) | DPBP_CMD_BASE_VERSION)
222 +
223 +/* Command IDs */
224 +#define DPBP_CMDID_CLOSE DPBP_CMD(0x800)
225 +#define DPBP_CMDID_OPEN DPBP_CMD(0x804)
226 +#define DPBP_CMDID_GET_API_VERSION DPBP_CMD(0xa04)
227 +
228 +#define DPBP_CMDID_ENABLE DPBP_CMD(0x002)
229 +#define DPBP_CMDID_DISABLE DPBP_CMD(0x003)
230 +#define DPBP_CMDID_GET_ATTR DPBP_CMD(0x004)
231 +#define DPBP_CMDID_RESET DPBP_CMD(0x005)
232 +#define DPBP_CMDID_IS_ENABLED DPBP_CMD(0x006)
233 +
234 +struct dpbp_cmd_open {
235 + __le32 dpbp_id;
236 +};
237 +
238 +struct dpbp_cmd_destroy {
239 + __le32 object_id;
240 +};
241 +
242 +#define DPBP_ENABLE 0x1
243 +
244 +struct dpbp_rsp_is_enabled {
245 + u8 enabled;
246 +};
247 +
248 +struct dpbp_rsp_get_attributes {
249 + /* response word 0 */
250 + __le16 pad;
251 + __le16 bpid;
252 + __le32 id;
253 + /* response word 1 */
254 + __le16 version_major;
255 + __le16 version_minor;
256 +};
257 +
258 +#endif /* _FSL_DPBP_CMD_H */
259 diff --git a/drivers/staging/fsl-mc/bus/dpbp.c b/drivers/staging/fsl-mc/bus/dpbp.c
260 index 5d4cd812..d9e450a6 100644
261 --- a/drivers/staging/fsl-mc/bus/dpbp.c
262 +++ b/drivers/staging/fsl-mc/bus/dpbp.c
263 @@ -1,4 +1,5 @@
264 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
265 +/*
266 + * Copyright 2013-2016 Freescale Semiconductor Inc.
267 *
268 * Redistribution and use in source and binary forms, with or without
269 * modification, are permitted provided that the following conditions are met:
270 @@ -11,7 +12,6 @@
271 * names of any contributors may be used to endorse or promote products
272 * derived from this software without specific prior written permission.
273 *
274 - *
275 * ALTERNATIVELY, this software may be distributed under the terms of the
276 * GNU General Public License ("GPL") as published by the Free Software
277 * Foundation, either version 2 of that License or (at your option) any
278 @@ -32,7 +32,8 @@
279 #include "../include/mc-sys.h"
280 #include "../include/mc-cmd.h"
281 #include "../include/dpbp.h"
282 -#include "../include/dpbp-cmd.h"
283 +
284 +#include "dpbp-cmd.h"
285
286 /**
287 * dpbp_open() - Open a control session for the specified object.
288 @@ -104,74 +105,6 @@ int dpbp_close(struct fsl_mc_io *mc_io,
289 }
290 EXPORT_SYMBOL(dpbp_close);
291
292 -/**
293 - * dpbp_create() - Create the DPBP object.
294 - * @mc_io: Pointer to MC portal's I/O object
295 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
296 - * @cfg: Configuration structure
297 - * @token: Returned token; use in subsequent API calls
298 - *
299 - * Create the DPBP object, allocate required resources and
300 - * perform required initialization.
301 - *
302 - * The object can be created either by declaring it in the
303 - * DPL file, or by calling this function.
304 - * This function returns a unique authentication token,
305 - * associated with the specific object ID and the specific MC
306 - * portal; this token must be used in all subsequent calls to
307 - * this specific object. For objects that are created using the
308 - * DPL file, call dpbp_open function to get an authentication
309 - * token first.
310 - *
311 - * Return: '0' on Success; Error code otherwise.
312 - */
313 -int dpbp_create(struct fsl_mc_io *mc_io,
314 - u32 cmd_flags,
315 - const struct dpbp_cfg *cfg,
316 - u16 *token)
317 -{
318 - struct mc_command cmd = { 0 };
319 - int err;
320 -
321 - (void)(cfg); /* unused */
322 -
323 - /* prepare command */
324 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_CREATE,
325 - cmd_flags, 0);
326 -
327 - /* send command to mc*/
328 - err = mc_send_command(mc_io, &cmd);
329 - if (err)
330 - return err;
331 -
332 - /* retrieve response parameters */
333 - *token = mc_cmd_hdr_read_token(&cmd);
334 -
335 - return 0;
336 -}
337 -
338 -/**
339 - * dpbp_destroy() - Destroy the DPBP object and release all its resources.
340 - * @mc_io: Pointer to MC portal's I/O object
341 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
342 - * @token: Token of DPBP object
343 - *
344 - * Return: '0' on Success; error code otherwise.
345 - */
346 -int dpbp_destroy(struct fsl_mc_io *mc_io,
347 - u32 cmd_flags,
348 - u16 token)
349 -{
350 - struct mc_command cmd = { 0 };
351 -
352 - /* prepare command */
353 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_DESTROY,
354 - cmd_flags, token);
355 -
356 - /* send command to mc*/
357 - return mc_send_command(mc_io, &cmd);
358 -}
359 -
360 /**
361 * dpbp_enable() - Enable the DPBP.
362 * @mc_io: Pointer to MC portal's I/O object
363 @@ -250,6 +183,7 @@ int dpbp_is_enabled(struct fsl_mc_io *mc_io,
364
365 return 0;
366 }
367 +EXPORT_SYMBOL(dpbp_is_enabled);
368
369 /**
370 * dpbp_reset() - Reset the DPBP, returns the object to initial state.
371 @@ -272,310 +206,7 @@ int dpbp_reset(struct fsl_mc_io *mc_io,
372 /* send command to mc*/
373 return mc_send_command(mc_io, &cmd);
374 }
375 -
376 -/**
377 - * dpbp_set_irq() - Set IRQ information for the DPBP to trigger an interrupt.
378 - * @mc_io: Pointer to MC portal's I/O object
379 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
380 - * @token: Token of DPBP object
381 - * @irq_index: Identifies the interrupt index to configure
382 - * @irq_cfg: IRQ configuration
383 - *
384 - * Return: '0' on Success; Error code otherwise.
385 - */
386 -int dpbp_set_irq(struct fsl_mc_io *mc_io,
387 - u32 cmd_flags,
388 - u16 token,
389 - u8 irq_index,
390 - struct dpbp_irq_cfg *irq_cfg)
391 -{
392 - struct mc_command cmd = { 0 };
393 - struct dpbp_cmd_set_irq *cmd_params;
394 -
395 - /* prepare command */
396 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ,
397 - cmd_flags, token);
398 - cmd_params = (struct dpbp_cmd_set_irq *)cmd.params;
399 - cmd_params->irq_index = irq_index;
400 - cmd_params->irq_val = cpu_to_le32(irq_cfg->val);
401 - cmd_params->irq_addr = cpu_to_le64(irq_cfg->addr);
402 - cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num);
403 -
404 - /* send command to mc*/
405 - return mc_send_command(mc_io, &cmd);
406 -}
407 -
408 -/**
409 - * dpbp_get_irq() - Get IRQ information from the DPBP.
410 - * @mc_io: Pointer to MC portal's I/O object
411 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
412 - * @token: Token of DPBP object
413 - * @irq_index: The interrupt index to configure
414 - * @type: Interrupt type: 0 represents message interrupt
415 - * type (both irq_addr and irq_val are valid)
416 - * @irq_cfg: IRQ attributes
417 - *
418 - * Return: '0' on Success; Error code otherwise.
419 - */
420 -int dpbp_get_irq(struct fsl_mc_io *mc_io,
421 - u32 cmd_flags,
422 - u16 token,
423 - u8 irq_index,
424 - int *type,
425 - struct dpbp_irq_cfg *irq_cfg)
426 -{
427 - struct mc_command cmd = { 0 };
428 - struct dpbp_cmd_get_irq *cmd_params;
429 - struct dpbp_rsp_get_irq *rsp_params;
430 - int err;
431 -
432 - /* prepare command */
433 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ,
434 - cmd_flags, token);
435 - cmd_params = (struct dpbp_cmd_get_irq *)cmd.params;
436 - cmd_params->irq_index = irq_index;
437 -
438 - /* send command to mc*/
439 - err = mc_send_command(mc_io, &cmd);
440 - if (err)
441 - return err;
442 -
443 - /* retrieve response parameters */
444 - rsp_params = (struct dpbp_rsp_get_irq *)cmd.params;
445 - irq_cfg->val = le32_to_cpu(rsp_params->irq_val);
446 - irq_cfg->addr = le64_to_cpu(rsp_params->irq_addr);
447 - irq_cfg->irq_num = le32_to_cpu(rsp_params->irq_num);
448 - *type = le32_to_cpu(rsp_params->type);
449 -
450 - return 0;
451 -}
452 -
453 -/**
454 - * dpbp_set_irq_enable() - Set overall interrupt state.
455 - * @mc_io: Pointer to MC portal's I/O object
456 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
457 - * @token: Token of DPBP object
458 - * @irq_index: The interrupt index to configure
459 - * @en: Interrupt state - enable = 1, disable = 0
460 - *
461 - * Allows GPP software to control when interrupts are generated.
462 - * Each interrupt can have up to 32 causes. The enable/disable control's the
463 - * overall interrupt state. if the interrupt is disabled no causes will cause
464 - * an interrupt.
465 - *
466 - * Return: '0' on Success; Error code otherwise.
467 - */
468 -int dpbp_set_irq_enable(struct fsl_mc_io *mc_io,
469 - u32 cmd_flags,
470 - u16 token,
471 - u8 irq_index,
472 - u8 en)
473 -{
474 - struct mc_command cmd = { 0 };
475 - struct dpbp_cmd_set_irq_enable *cmd_params;
476 -
477 - /* prepare command */
478 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ_ENABLE,
479 - cmd_flags, token);
480 - cmd_params = (struct dpbp_cmd_set_irq_enable *)cmd.params;
481 - cmd_params->enable = en & DPBP_ENABLE;
482 - cmd_params->irq_index = irq_index;
483 -
484 - /* send command to mc*/
485 - return mc_send_command(mc_io, &cmd);
486 -}
487 -
488 -/**
489 - * dpbp_get_irq_enable() - Get overall interrupt state
490 - * @mc_io: Pointer to MC portal's I/O object
491 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
492 - * @token: Token of DPBP object
493 - * @irq_index: The interrupt index to configure
494 - * @en: Returned interrupt state - enable = 1, disable = 0
495 - *
496 - * Return: '0' on Success; Error code otherwise.
497 - */
498 -int dpbp_get_irq_enable(struct fsl_mc_io *mc_io,
499 - u32 cmd_flags,
500 - u16 token,
501 - u8 irq_index,
502 - u8 *en)
503 -{
504 - struct mc_command cmd = { 0 };
505 - struct dpbp_cmd_get_irq_enable *cmd_params;
506 - struct dpbp_rsp_get_irq_enable *rsp_params;
507 - int err;
508 -
509 - /* prepare command */
510 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_ENABLE,
511 - cmd_flags, token);
512 - cmd_params = (struct dpbp_cmd_get_irq_enable *)cmd.params;
513 - cmd_params->irq_index = irq_index;
514 -
515 - /* send command to mc*/
516 - err = mc_send_command(mc_io, &cmd);
517 - if (err)
518 - return err;
519 -
520 - /* retrieve response parameters */
521 - rsp_params = (struct dpbp_rsp_get_irq_enable *)cmd.params;
522 - *en = rsp_params->enabled & DPBP_ENABLE;
523 - return 0;
524 -}
525 -
526 -/**
527 - * dpbp_set_irq_mask() - Set interrupt mask.
528 - * @mc_io: Pointer to MC portal's I/O object
529 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
530 - * @token: Token of DPBP object
531 - * @irq_index: The interrupt index to configure
532 - * @mask: Event mask to trigger interrupt;
533 - * each bit:
534 - * 0 = ignore event
535 - * 1 = consider event for asserting IRQ
536 - *
537 - * Every interrupt can have up to 32 causes and the interrupt model supports
538 - * masking/unmasking each cause independently
539 - *
540 - * Return: '0' on Success; Error code otherwise.
541 - */
542 -int dpbp_set_irq_mask(struct fsl_mc_io *mc_io,
543 - u32 cmd_flags,
544 - u16 token,
545 - u8 irq_index,
546 - u32 mask)
547 -{
548 - struct mc_command cmd = { 0 };
549 - struct dpbp_cmd_set_irq_mask *cmd_params;
550 -
551 - /* prepare command */
552 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ_MASK,
553 - cmd_flags, token);
554 - cmd_params = (struct dpbp_cmd_set_irq_mask *)cmd.params;
555 - cmd_params->mask = cpu_to_le32(mask);
556 - cmd_params->irq_index = irq_index;
557 -
558 - /* send command to mc*/
559 - return mc_send_command(mc_io, &cmd);
560 -}
561 -
562 -/**
563 - * dpbp_get_irq_mask() - Get interrupt mask.
564 - * @mc_io: Pointer to MC portal's I/O object
565 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
566 - * @token: Token of DPBP object
567 - * @irq_index: The interrupt index to configure
568 - * @mask: Returned event mask to trigger interrupt
569 - *
570 - * Every interrupt can have up to 32 causes and the interrupt model supports
571 - * masking/unmasking each cause independently
572 - *
573 - * Return: '0' on Success; Error code otherwise.
574 - */
575 -int dpbp_get_irq_mask(struct fsl_mc_io *mc_io,
576 - u32 cmd_flags,
577 - u16 token,
578 - u8 irq_index,
579 - u32 *mask)
580 -{
581 - struct mc_command cmd = { 0 };
582 - struct dpbp_cmd_get_irq_mask *cmd_params;
583 - struct dpbp_rsp_get_irq_mask *rsp_params;
584 - int err;
585 -
586 - /* prepare command */
587 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_MASK,
588 - cmd_flags, token);
589 - cmd_params = (struct dpbp_cmd_get_irq_mask *)cmd.params;
590 - cmd_params->irq_index = irq_index;
591 -
592 - /* send command to mc*/
593 - err = mc_send_command(mc_io, &cmd);
594 - if (err)
595 - return err;
596 -
597 - /* retrieve response parameters */
598 - rsp_params = (struct dpbp_rsp_get_irq_mask *)cmd.params;
599 - *mask = le32_to_cpu(rsp_params->mask);
600 -
601 - return 0;
602 -}
603 -
604 -/**
605 - * dpbp_get_irq_status() - Get the current status of any pending interrupts.
606 - *
607 - * @mc_io: Pointer to MC portal's I/O object
608 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
609 - * @token: Token of DPBP object
610 - * @irq_index: The interrupt index to configure
611 - * @status: Returned interrupts status - one bit per cause:
612 - * 0 = no interrupt pending
613 - * 1 = interrupt pending
614 - *
615 - * Return: '0' on Success; Error code otherwise.
616 - */
617 -int dpbp_get_irq_status(struct fsl_mc_io *mc_io,
618 - u32 cmd_flags,
619 - u16 token,
620 - u8 irq_index,
621 - u32 *status)
622 -{
623 - struct mc_command cmd = { 0 };
624 - struct dpbp_cmd_get_irq_status *cmd_params;
625 - struct dpbp_rsp_get_irq_status *rsp_params;
626 - int err;
627 -
628 - /* prepare command */
629 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_STATUS,
630 - cmd_flags, token);
631 - cmd_params = (struct dpbp_cmd_get_irq_status *)cmd.params;
632 - cmd_params->status = cpu_to_le32(*status);
633 - cmd_params->irq_index = irq_index;
634 -
635 - /* send command to mc*/
636 - err = mc_send_command(mc_io, &cmd);
637 - if (err)
638 - return err;
639 -
640 - /* retrieve response parameters */
641 - rsp_params = (struct dpbp_rsp_get_irq_status *)cmd.params;
642 - *status = le32_to_cpu(rsp_params->status);
643 -
644 - return 0;
645 -}
646 -
647 -/**
648 - * dpbp_clear_irq_status() - Clear a pending interrupt's status
649 - *
650 - * @mc_io: Pointer to MC portal's I/O object
651 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
652 - * @token: Token of DPBP object
653 - * @irq_index: The interrupt index to configure
654 - * @status: Bits to clear (W1C) - one bit per cause:
655 - * 0 = don't change
656 - * 1 = clear status bit
657 - *
658 - * Return: '0' on Success; Error code otherwise.
659 - */
660 -int dpbp_clear_irq_status(struct fsl_mc_io *mc_io,
661 - u32 cmd_flags,
662 - u16 token,
663 - u8 irq_index,
664 - u32 status)
665 -{
666 - struct mc_command cmd = { 0 };
667 - struct dpbp_cmd_clear_irq_status *cmd_params;
668 -
669 - /* prepare command */
670 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLEAR_IRQ_STATUS,
671 - cmd_flags, token);
672 - cmd_params = (struct dpbp_cmd_clear_irq_status *)cmd.params;
673 - cmd_params->status = cpu_to_le32(status);
674 - cmd_params->irq_index = irq_index;
675 -
676 - /* send command to mc*/
677 - return mc_send_command(mc_io, &cmd);
678 -}
679 +EXPORT_SYMBOL(dpbp_reset);
680
681 /**
682 * dpbp_get_attributes - Retrieve DPBP attributes.
683 @@ -609,83 +240,40 @@ int dpbp_get_attributes(struct fsl_mc_io *mc_io,
684 rsp_params = (struct dpbp_rsp_get_attributes *)cmd.params;
685 attr->bpid = le16_to_cpu(rsp_params->bpid);
686 attr->id = le32_to_cpu(rsp_params->id);
687 - attr->version.major = le16_to_cpu(rsp_params->version_major);
688 - attr->version.minor = le16_to_cpu(rsp_params->version_minor);
689
690 return 0;
691 }
692 EXPORT_SYMBOL(dpbp_get_attributes);
693
694 /**
695 - * dpbp_set_notifications() - Set notifications towards software
696 - * @mc_io: Pointer to MC portal's I/O object
697 + * dpbp_get_api_version - Get Data Path Buffer Pool API version
698 + * @mc_io: Pointer to Mc portal's I/O object
699 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
700 - * @token: Token of DPBP object
701 - * @cfg: notifications configuration
702 + * @major_ver: Major version of Buffer Pool API
703 + * @minor_ver: Minor version of Buffer Pool API
704 *
705 * Return: '0' on Success; Error code otherwise.
706 */
707 -int dpbp_set_notifications(struct fsl_mc_io *mc_io,
708 - u32 cmd_flags,
709 - u16 token,
710 - struct dpbp_notification_cfg *cfg)
711 +int dpbp_get_api_version(struct fsl_mc_io *mc_io,
712 + u32 cmd_flags,
713 + u16 *major_ver,
714 + u16 *minor_ver)
715 {
716 struct mc_command cmd = { 0 };
717 - struct dpbp_cmd_set_notifications *cmd_params;
718 -
719 - /* prepare command */
720 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_NOTIFICATIONS,
721 - cmd_flags, token);
722 - cmd_params = (struct dpbp_cmd_set_notifications *)cmd.params;
723 - cmd_params->depletion_entry = cpu_to_le32(cfg->depletion_entry);
724 - cmd_params->depletion_exit = cpu_to_le32(cfg->depletion_exit);
725 - cmd_params->surplus_entry = cpu_to_le32(cfg->surplus_entry);
726 - cmd_params->surplus_exit = cpu_to_le32(cfg->surplus_exit);
727 - cmd_params->options = cpu_to_le16(cfg->options);
728 - cmd_params->message_ctx = cpu_to_le64(cfg->message_ctx);
729 - cmd_params->message_iova = cpu_to_le64(cfg->message_iova);
730 -
731 - /* send command to mc*/
732 - return mc_send_command(mc_io, &cmd);
733 -}
734 -
735 -/**
736 - * dpbp_get_notifications() - Get the notifications configuration
737 - * @mc_io: Pointer to MC portal's I/O object
738 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
739 - * @token: Token of DPBP object
740 - * @cfg: notifications configuration
741 - *
742 - * Return: '0' on Success; Error code otherwise.
743 - */
744 -int dpbp_get_notifications(struct fsl_mc_io *mc_io,
745 - u32 cmd_flags,
746 - u16 token,
747 - struct dpbp_notification_cfg *cfg)
748 -{
749 - struct mc_command cmd = { 0 };
750 - struct dpbp_rsp_get_notifications *rsp_params;
751 int err;
752
753 /* prepare command */
754 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_NOTIFICATIONS,
755 - cmd_flags,
756 - token);
757 + cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_API_VERSION,
758 + cmd_flags, 0);
759
760 - /* send command to mc*/
761 + /* send command to mc */
762 err = mc_send_command(mc_io, &cmd);
763 if (err)
764 return err;
765
766 /* retrieve response parameters */
767 - rsp_params = (struct dpbp_rsp_get_notifications *)cmd.params;
768 - cfg->depletion_entry = le32_to_cpu(rsp_params->depletion_entry);
769 - cfg->depletion_exit = le32_to_cpu(rsp_params->depletion_exit);
770 - cfg->surplus_entry = le32_to_cpu(rsp_params->surplus_entry);
771 - cfg->surplus_exit = le32_to_cpu(rsp_params->surplus_exit);
772 - cfg->options = le16_to_cpu(rsp_params->options);
773 - cfg->message_ctx = le64_to_cpu(rsp_params->message_ctx);
774 - cfg->message_iova = le64_to_cpu(rsp_params->message_iova);
775 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
776
777 return 0;
778 }
779 +EXPORT_SYMBOL(dpbp_get_api_version);
780 diff --git a/drivers/staging/fsl-mc/bus/dpcon-cmd.h b/drivers/staging/fsl-mc/bus/dpcon-cmd.h
781 new file mode 100644
782 index 00000000..2bb66988
783 --- /dev/null
784 +++ b/drivers/staging/fsl-mc/bus/dpcon-cmd.h
785 @@ -0,0 +1,85 @@
786 +/*
787 + * Copyright 2013-2016 Freescale Semiconductor Inc.
788 + *
789 + * Redistribution and use in source and binary forms, with or without
790 + * modification, are permitted provided that the following conditions are met:
791 + * * Redistributions of source code must retain the above copyright
792 + * notice, this list of conditions and the following disclaimer.
793 + * * Redistributions in binary form must reproduce the above copyright
794 + * notice, this list of conditions and the following disclaimer in the
795 + * documentation and/or other materials provided with the distribution.
796 + * * Neither the name of the above-listed copyright holders nor the
797 + * names of any contributors may be used to endorse or promote products
798 + * derived from this software without specific prior written permission.
799 + *
800 + * ALTERNATIVELY, this software may be distributed under the terms of the
801 + * GNU General Public License ("GPL") as published by the Free Software
802 + * Foundation, either version 2 of that License or (at your option) any
803 + * later version.
804 + *
805 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
806 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
807 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
808 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
809 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
810 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
811 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
812 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
813 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
814 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
815 + * POSSIBILITY OF SUCH DAMAGE.
816 + */
817 +#ifndef _FSL_DPCON_CMD_H
818 +#define _FSL_DPCON_CMD_H
819 +
820 +/* DPCON Version */
821 +#define DPCON_VER_MAJOR 3
822 +#define DPCON_VER_MINOR 2
823 +
824 +/* Command versioning */
825 +#define DPCON_CMD_BASE_VERSION 1
826 +#define DPCON_CMD_ID_OFFSET 4
827 +
828 +#define DPCON_CMD(id) (((id) << DPCON_CMD_ID_OFFSET) | DPCON_CMD_BASE_VERSION)
829 +
830 +/* Command IDs */
831 +#define DPCON_CMDID_CLOSE DPCON_CMD(0x800)
832 +#define DPCON_CMDID_OPEN DPCON_CMD(0x808)
833 +#define DPCON_CMDID_GET_API_VERSION DPCON_CMD(0xa08)
834 +
835 +#define DPCON_CMDID_ENABLE DPCON_CMD(0x002)
836 +#define DPCON_CMDID_DISABLE DPCON_CMD(0x003)
837 +#define DPCON_CMDID_GET_ATTR DPCON_CMD(0x004)
838 +#define DPCON_CMDID_RESET DPCON_CMD(0x005)
839 +#define DPCON_CMDID_IS_ENABLED DPCON_CMD(0x006)
840 +
841 +#define DPCON_CMDID_SET_NOTIFICATION DPCON_CMD(0x100)
842 +
843 +struct dpcon_cmd_open {
844 + __le32 dpcon_id;
845 +};
846 +
847 +#define DPCON_ENABLE 1
848 +
849 +struct dpcon_rsp_is_enabled {
850 + u8 enabled;
851 +};
852 +
853 +struct dpcon_rsp_get_attr {
854 + /* response word 0 */
855 + __le32 id;
856 + __le16 qbman_ch_id;
857 + u8 num_priorities;
858 + u8 pad;
859 +};
860 +
861 +struct dpcon_cmd_set_notification {
862 + /* cmd word 0 */
863 + __le32 dpio_id;
864 + u8 priority;
865 + u8 pad[3];
866 + /* cmd word 1 */
867 + __le64 user_ctx;
868 +};
869 +
870 +#endif /* _FSL_DPCON_CMD_H */
871 diff --git a/drivers/staging/fsl-mc/bus/dpcon.c b/drivers/staging/fsl-mc/bus/dpcon.c
872 new file mode 100644
873 index 00000000..eb713578
874 --- /dev/null
875 +++ b/drivers/staging/fsl-mc/bus/dpcon.c
876 @@ -0,0 +1,317 @@
877 +/* Copyright 2013-2016 Freescale Semiconductor Inc.
878 + *
879 + * Redistribution and use in source and binary forms, with or without
880 + * modification, are permitted provided that the following conditions are met:
881 + * * Redistributions of source code must retain the above copyright
882 + * notice, this list of conditions and the following disclaimer.
883 + * * Redistributions in binary form must reproduce the above copyright
884 + * notice, this list of conditions and the following disclaimer in the
885 + * documentation and/or other materials provided with the distribution.
886 + * * Neither the name of the above-listed copyright holders nor the
887 + * names of any contributors may be used to endorse or promote products
888 + * derived from this software without specific prior written permission.
889 + *
890 + *
891 + * ALTERNATIVELY, this software may be distributed under the terms of the
892 + * GNU General Public License ("GPL") as published by the Free Software
893 + * Foundation, either version 2 of that License or (at your option) any
894 + * later version.
895 + *
896 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
897 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
898 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
899 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
900 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
901 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
902 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
903 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
904 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
905 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
906 + * POSSIBILITY OF SUCH DAMAGE.
907 + */
908 +#include "../include/mc-sys.h"
909 +#include "../include/mc-cmd.h"
910 +#include "../include/dpcon.h"
911 +
912 +#include "dpcon-cmd.h"
913 +
914 +/**
915 + * dpcon_open() - Open a control session for the specified object
916 + * @mc_io: Pointer to MC portal's I/O object
917 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
918 + * @dpcon_id: DPCON unique ID
919 + * @token: Returned token; use in subsequent API calls
920 + *
921 + * This function can be used to open a control session for an
922 + * already created object; an object may have been declared in
923 + * the DPL or by calling the dpcon_create() function.
924 + * This function returns a unique authentication token,
925 + * associated with the specific object ID and the specific MC
926 + * portal; this token must be used in all subsequent commands for
927 + * this specific object.
928 + *
929 + * Return: '0' on Success; Error code otherwise.
930 + */
931 +int dpcon_open(struct fsl_mc_io *mc_io,
932 + u32 cmd_flags,
933 + int dpcon_id,
934 + u16 *token)
935 +{
936 + struct mc_command cmd = { 0 };
937 + struct dpcon_cmd_open *dpcon_cmd;
938 + int err;
939 +
940 + /* prepare command */
941 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_OPEN,
942 + cmd_flags,
943 + 0);
944 + dpcon_cmd = (struct dpcon_cmd_open *)cmd.params;
945 + dpcon_cmd->dpcon_id = cpu_to_le32(dpcon_id);
946 +
947 + /* send command to mc*/
948 + err = mc_send_command(mc_io, &cmd);
949 + if (err)
950 + return err;
951 +
952 + /* retrieve response parameters */
953 + *token = mc_cmd_hdr_read_token(&cmd);
954 +
955 + return 0;
956 +}
957 +EXPORT_SYMBOL(dpcon_open);
958 +
959 +/**
960 + * dpcon_close() - Close the control session of the object
961 + * @mc_io: Pointer to MC portal's I/O object
962 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
963 + * @token: Token of DPCON object
964 + *
965 + * After this function is called, no further operations are
966 + * allowed on the object without opening a new control session.
967 + *
968 + * Return: '0' on Success; Error code otherwise.
969 + */
970 +int dpcon_close(struct fsl_mc_io *mc_io,
971 + u32 cmd_flags,
972 + u16 token)
973 +{
974 + struct mc_command cmd = { 0 };
975 +
976 + /* prepare command */
977 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_CLOSE,
978 + cmd_flags,
979 + token);
980 +
981 + /* send command to mc*/
982 + return mc_send_command(mc_io, &cmd);
983 +}
984 +EXPORT_SYMBOL(dpcon_close);
985 +
986 +/**
987 + * dpcon_enable() - Enable the DPCON
988 + * @mc_io: Pointer to MC portal's I/O object
989 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
990 + * @token: Token of DPCON object
991 + *
992 + * Return: '0' on Success; Error code otherwise
993 + */
994 +int dpcon_enable(struct fsl_mc_io *mc_io,
995 + u32 cmd_flags,
996 + u16 token)
997 +{
998 + struct mc_command cmd = { 0 };
999 +
1000 + /* prepare command */
1001 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_ENABLE,
1002 + cmd_flags,
1003 + token);
1004 +
1005 + /* send command to mc*/
1006 + return mc_send_command(mc_io, &cmd);
1007 +}
1008 +EXPORT_SYMBOL(dpcon_enable);
1009 +
1010 +/**
1011 + * dpcon_disable() - Disable the DPCON
1012 + * @mc_io: Pointer to MC portal's I/O object
1013 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1014 + * @token: Token of DPCON object
1015 + *
1016 + * Return: '0' on Success; Error code otherwise
1017 + */
1018 +int dpcon_disable(struct fsl_mc_io *mc_io,
1019 + u32 cmd_flags,
1020 + u16 token)
1021 +{
1022 + struct mc_command cmd = { 0 };
1023 +
1024 + /* prepare command */
1025 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_DISABLE,
1026 + cmd_flags,
1027 + token);
1028 +
1029 + /* send command to mc*/
1030 + return mc_send_command(mc_io, &cmd);
1031 +}
1032 +EXPORT_SYMBOL(dpcon_disable);
1033 +
1034 +/**
1035 + * dpcon_is_enabled() - Check if the DPCON is enabled.
1036 + * @mc_io: Pointer to MC portal's I/O object
1037 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1038 + * @token: Token of DPCON object
1039 + * @en: Returns '1' if object is enabled; '0' otherwise
1040 + *
1041 + * Return: '0' on Success; Error code otherwise.
1042 + */
1043 +int dpcon_is_enabled(struct fsl_mc_io *mc_io,
1044 + u32 cmd_flags,
1045 + u16 token,
1046 + int *en)
1047 +{
1048 + struct mc_command cmd = { 0 };
1049 + struct dpcon_rsp_is_enabled *dpcon_rsp;
1050 + int err;
1051 +
1052 + /* prepare command */
1053 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_IS_ENABLED,
1054 + cmd_flags,
1055 + token);
1056 +
1057 + /* send command to mc*/
1058 + err = mc_send_command(mc_io, &cmd);
1059 + if (err)
1060 + return err;
1061 +
1062 + /* retrieve response parameters */
1063 + dpcon_rsp = (struct dpcon_rsp_is_enabled *)cmd.params;
1064 + *en = dpcon_rsp->enabled & DPCON_ENABLE;
1065 +
1066 + return 0;
1067 +}
1068 +EXPORT_SYMBOL(dpcon_is_enabled);
1069 +
1070 +/**
1071 + * dpcon_reset() - Reset the DPCON, returns the object to initial state.
1072 + * @mc_io: Pointer to MC portal's I/O object
1073 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1074 + * @token: Token of DPCON object
1075 + *
1076 + * Return: '0' on Success; Error code otherwise.
1077 + */
1078 +int dpcon_reset(struct fsl_mc_io *mc_io,
1079 + u32 cmd_flags,
1080 + u16 token)
1081 +{
1082 + struct mc_command cmd = { 0 };
1083 +
1084 + /* prepare command */
1085 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_RESET,
1086 + cmd_flags, token);
1087 +
1088 + /* send command to mc*/
1089 + return mc_send_command(mc_io, &cmd);
1090 +}
1091 +EXPORT_SYMBOL(dpcon_reset);
1092 +
1093 +/**
1094 + * dpcon_get_attributes() - Retrieve DPCON attributes.
1095 + * @mc_io: Pointer to MC portal's I/O object
1096 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1097 + * @token: Token of DPCON object
1098 + * @attr: Object's attributes
1099 + *
1100 + * Return: '0' on Success; Error code otherwise.
1101 + */
1102 +int dpcon_get_attributes(struct fsl_mc_io *mc_io,
1103 + u32 cmd_flags,
1104 + u16 token,
1105 + struct dpcon_attr *attr)
1106 +{
1107 + struct mc_command cmd = { 0 };
1108 + struct dpcon_rsp_get_attr *dpcon_rsp;
1109 + int err;
1110 +
1111 + /* prepare command */
1112 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_ATTR,
1113 + cmd_flags,
1114 + token);
1115 +
1116 + /* send command to mc*/
1117 + err = mc_send_command(mc_io, &cmd);
1118 + if (err)
1119 + return err;
1120 +
1121 + /* retrieve response parameters */
1122 + dpcon_rsp = (struct dpcon_rsp_get_attr *)cmd.params;
1123 + attr->id = le32_to_cpu(dpcon_rsp->id);
1124 + attr->qbman_ch_id = le16_to_cpu(dpcon_rsp->qbman_ch_id);
1125 + attr->num_priorities = dpcon_rsp->num_priorities;
1126 +
1127 + return 0;
1128 +}
1129 +EXPORT_SYMBOL(dpcon_get_attributes);
1130 +
1131 +/**
1132 + * dpcon_set_notification() - Set DPCON notification destination
1133 + * @mc_io: Pointer to MC portal's I/O object
1134 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1135 + * @token: Token of DPCON object
1136 + * @cfg: Notification parameters
1137 + *
1138 + * Return: '0' on Success; Error code otherwise
1139 + */
1140 +int dpcon_set_notification(struct fsl_mc_io *mc_io,
1141 + u32 cmd_flags,
1142 + u16 token,
1143 + struct dpcon_notification_cfg *cfg)
1144 +{
1145 + struct mc_command cmd = { 0 };
1146 + struct dpcon_cmd_set_notification *dpcon_cmd;
1147 +
1148 + /* prepare command */
1149 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_SET_NOTIFICATION,
1150 + cmd_flags,
1151 + token);
1152 + dpcon_cmd = (struct dpcon_cmd_set_notification *)cmd.params;
1153 + dpcon_cmd->dpio_id = cpu_to_le32(cfg->dpio_id);
1154 + dpcon_cmd->priority = cfg->priority;
1155 + dpcon_cmd->user_ctx = cpu_to_le64(cfg->user_ctx);
1156 +
1157 + /* send command to mc*/
1158 + return mc_send_command(mc_io, &cmd);
1159 +}
1160 +EXPORT_SYMBOL(dpcon_set_notification);
1161 +
1162 +/**
1163 + * dpcon_get_api_version - Get Data Path Concentrator API version
1164 + * @mc_io: Pointer to MC portal's DPCON object
1165 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1166 + * @major_ver: Major version of DPCON API
1167 + * @minor_ver: Minor version of DPCON API
1168 + *
1169 + * Return: '0' on Success; Error code otherwise
1170 + */
1171 +int dpcon_get_api_version(struct fsl_mc_io *mc_io,
1172 + u32 cmd_flags,
1173 + u16 *major_ver,
1174 + u16 *minor_ver)
1175 +{
1176 + struct mc_command cmd = { 0 };
1177 + int err;
1178 +
1179 + /* prepare command */
1180 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_API_VERSION,
1181 + cmd_flags, 0);
1182 +
1183 + /* send command to mc */
1184 + err = mc_send_command(mc_io, &cmd);
1185 + if (err)
1186 + return err;
1187 +
1188 + /* retrieve response parameters */
1189 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
1190 +
1191 + return 0;
1192 +}
1193 +EXPORT_SYMBOL(dpcon_get_api_version);
1194 diff --git a/drivers/staging/fsl-mc/bus/dpio/Makefile b/drivers/staging/fsl-mc/bus/dpio/Makefile
1195 new file mode 100644
1196 index 00000000..1c28794e
1197 --- /dev/null
1198 +++ b/drivers/staging/fsl-mc/bus/dpio/Makefile
1199 @@ -0,0 +1,11 @@
1200 +#
1201 +# QorIQ DPAA2 DPIO driver
1202 +#
1203 +
1204 +subdir-ccflags-y := -Werror
1205 +
1206 +obj-$(CONFIG_FSL_MC_DPIO) += fsl-mc-dpio.o
1207 +
1208 +fsl-mc-dpio-objs := dpio.o qbman-portal.o dpio-service.o dpio-driver.o
1209 +
1210 +obj-$(CONFIG_FSL_QBMAN_DEBUG) += qbman_debug.o
1211 diff --git a/drivers/staging/fsl-mc/include/dpcon-cmd.h b/drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h
1212 similarity index 64%
1213 rename from drivers/staging/fsl-mc/include/dpcon-cmd.h
1214 rename to drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h
1215 index 536b2ef1..b2dc6e76 100644
1216 --- a/drivers/staging/fsl-mc/include/dpcon-cmd.h
1217 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h
1218 @@ -1,4 +1,6 @@
1219 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
1220 +/*
1221 + * Copyright 2013-2016 Freescale Semiconductor Inc.
1222 + * Copyright 2016 NXP
1223 *
1224 * Redistribution and use in source and binary forms, with or without
1225 * modification, are permitted provided that the following conditions are met:
1226 @@ -11,7 +13,6 @@
1227 * names of any contributors may be used to endorse or promote products
1228 * derived from this software without specific prior written permission.
1229 *
1230 - *
1231 * ALTERNATIVELY, this software may be distributed under the terms of the
1232 * GNU General Public License ("GPL") as published by the Free Software
1233 * Foundation, either version 2 of that License or (at your option) any
1234 @@ -29,34 +30,46 @@
1235 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
1236 * POSSIBILITY OF SUCH DAMAGE.
1237 */
1238 -#ifndef _FSL_DPCON_CMD_H
1239 -#define _FSL_DPCON_CMD_H
1240 +#ifndef _FSL_DPIO_CMD_H
1241 +#define _FSL_DPIO_CMD_H
1242 +
1243 +/* DPIO Version */
1244 +#define DPIO_VER_MAJOR 4
1245 +#define DPIO_VER_MINOR 2
1246 +
1247 +/* Command Versioning */
1248 +
1249 +#define DPIO_CMD_ID_OFFSET 4
1250 +#define DPIO_CMD_BASE_VERSION 1
1251
1252 -/* DPCON Version */
1253 -#define DPCON_VER_MAJOR 2
1254 -#define DPCON_VER_MINOR 1
1255 +#define DPIO_CMD(id) (((id) << DPIO_CMD_ID_OFFSET) | DPIO_CMD_BASE_VERSION)
1256
1257 /* Command IDs */
1258 -#define DPCON_CMDID_CLOSE 0x800
1259 -#define DPCON_CMDID_OPEN 0x808
1260 -#define DPCON_CMDID_CREATE 0x908
1261 -#define DPCON_CMDID_DESTROY 0x900
1262 -
1263 -#define DPCON_CMDID_ENABLE 0x002
1264 -#define DPCON_CMDID_DISABLE 0x003
1265 -#define DPCON_CMDID_GET_ATTR 0x004
1266 -#define DPCON_CMDID_RESET 0x005
1267 -#define DPCON_CMDID_IS_ENABLED 0x006
1268 -
1269 -#define DPCON_CMDID_SET_IRQ 0x010
1270 -#define DPCON_CMDID_GET_IRQ 0x011
1271 -#define DPCON_CMDID_SET_IRQ_ENABLE 0x012
1272 -#define DPCON_CMDID_GET_IRQ_ENABLE 0x013
1273 -#define DPCON_CMDID_SET_IRQ_MASK 0x014
1274 -#define DPCON_CMDID_GET_IRQ_MASK 0x015
1275 -#define DPCON_CMDID_GET_IRQ_STATUS 0x016
1276 -#define DPCON_CMDID_CLEAR_IRQ_STATUS 0x017
1277 -
1278 -#define DPCON_CMDID_SET_NOTIFICATION 0x100
1279 -
1280 -#endif /* _FSL_DPCON_CMD_H */
1281 +#define DPIO_CMDID_CLOSE DPIO_CMD(0x800)
1282 +#define DPIO_CMDID_OPEN DPIO_CMD(0x803)
1283 +#define DPIO_CMDID_GET_API_VERSION DPIO_CMD(0xa03)
1284 +#define DPIO_CMDID_ENABLE DPIO_CMD(0x002)
1285 +#define DPIO_CMDID_DISABLE DPIO_CMD(0x003)
1286 +#define DPIO_CMDID_GET_ATTR DPIO_CMD(0x004)
1287 +
1288 +struct dpio_cmd_open {
1289 + __le32 dpio_id;
1290 +};
1291 +
1292 +#define DPIO_CHANNEL_MODE_MASK 0x3
1293 +
1294 +struct dpio_rsp_get_attr {
1295 + /* cmd word 0 */
1296 + __le32 id;
1297 + __le16 qbman_portal_id;
1298 + u8 num_priorities;
1299 + u8 channel_mode;
1300 + /* cmd word 1 */
1301 + __le64 qbman_portal_ce_addr;
1302 + /* cmd word 2 */
1303 + __le64 qbman_portal_ci_addr;
1304 + /* cmd word 3 */
1305 + __le32 qbman_version;
1306 +};
1307 +
1308 +#endif /* _FSL_DPIO_CMD_H */
1309 diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
1310 new file mode 100644
1311 index 00000000..8c8244a1
1312 --- /dev/null
1313 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
1314 @@ -0,0 +1,296 @@
1315 +/*
1316 + * Copyright 2014-2016 Freescale Semiconductor Inc.
1317 + * Copyright 2016 NXP
1318 + *
1319 + * Redistribution and use in source and binary forms, with or without
1320 + * modification, are permitted provided that the following conditions are met:
1321 + * * Redistributions of source code must retain the above copyright
1322 + * notice, this list of conditions and the following disclaimer.
1323 + * * Redistributions in binary form must reproduce the above copyright
1324 + * notice, this list of conditions and the following disclaimer in the
1325 + * documentation and/or other materials provided with the distribution.
1326 + * * Neither the name of Freescale Semiconductor nor the
1327 + * names of its contributors may be used to endorse or promote products
1328 + * derived from this software without specific prior written permission.
1329 + *
1330 + * ALTERNATIVELY, this software may be distributed under the terms of the
1331 + * GNU General Public License ("GPL") as published by the Free Software
1332 + * Foundation, either version 2 of that License or (at your option) any
1333 + * later version.
1334 + *
1335 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
1336 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
1337 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
1338 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
1339 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1340 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
1341 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
1342 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1343 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
1344 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1345 + */
1346 +
1347 +#include <linux/types.h>
1348 +#include <linux/init.h>
1349 +#include <linux/module.h>
1350 +#include <linux/platform_device.h>
1351 +#include <linux/interrupt.h>
1352 +#include <linux/msi.h>
1353 +#include <linux/dma-mapping.h>
1354 +#include <linux/delay.h>
1355 +
1356 +#include "../../include/mc.h"
1357 +#include "../../include/dpaa2-io.h"
1358 +
1359 +#include "qbman-portal.h"
1360 +#include "dpio.h"
1361 +#include "dpio-cmd.h"
1362 +
1363 +MODULE_LICENSE("Dual BSD/GPL");
1364 +MODULE_AUTHOR("Freescale Semiconductor, Inc");
1365 +MODULE_DESCRIPTION("DPIO Driver");
1366 +
1367 +struct dpio_priv {
1368 + struct dpaa2_io *io;
1369 +};
1370 +
1371 +static irqreturn_t dpio_irq_handler(int irq_num, void *arg)
1372 +{
1373 + struct device *dev = (struct device *)arg;
1374 + struct dpio_priv *priv = dev_get_drvdata(dev);
1375 +
1376 + return dpaa2_io_irq(priv->io);
1377 +}
1378 +
1379 +static void unregister_dpio_irq_handlers(struct fsl_mc_device *dpio_dev)
1380 +{
1381 + struct fsl_mc_device_irq *irq;
1382 +
1383 + irq = dpio_dev->irqs[0];
1384 +
1385 + /* clear the affinity hint */
1386 + irq_set_affinity_hint(irq->msi_desc->irq, NULL);
1387 +}
1388 +
1389 +static int register_dpio_irq_handlers(struct fsl_mc_device *dpio_dev, int cpu)
1390 +{
1391 + struct dpio_priv *priv;
1392 + int error;
1393 + struct fsl_mc_device_irq *irq;
1394 + cpumask_t mask;
1395 +
1396 + priv = dev_get_drvdata(&dpio_dev->dev);
1397 +
1398 + irq = dpio_dev->irqs[0];
1399 + error = devm_request_irq(&dpio_dev->dev,
1400 + irq->msi_desc->irq,
1401 + dpio_irq_handler,
1402 + 0,
1403 + dev_name(&dpio_dev->dev),
1404 + &dpio_dev->dev);
1405 + if (error < 0) {
1406 + dev_err(&dpio_dev->dev,
1407 + "devm_request_irq() failed: %d\n",
1408 + error);
1409 + return error;
1410 + }
1411 +
1412 + /* set the affinity hint */
1413 + cpumask_clear(&mask);
1414 + cpumask_set_cpu(cpu, &mask);
1415 + if (irq_set_affinity_hint(irq->msi_desc->irq, &mask))
1416 + dev_err(&dpio_dev->dev,
1417 + "irq_set_affinity failed irq %d cpu %d\n",
1418 + irq->msi_desc->irq, cpu);
1419 +
1420 + return 0;
1421 +}
1422 +
1423 +static int dpaa2_dpio_probe(struct fsl_mc_device *dpio_dev)
1424 +{
1425 + struct dpio_attr dpio_attrs;
1426 + struct dpaa2_io_desc desc;
1427 + struct dpio_priv *priv;
1428 + int err = -ENOMEM;
1429 + struct device *dev = &dpio_dev->dev;
1430 + static int next_cpu = -1;
1431 +
1432 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1433 + if (!priv)
1434 + goto err_priv_alloc;
1435 +
1436 + dev_set_drvdata(dev, priv);
1437 +
1438 + err = fsl_mc_portal_allocate(dpio_dev, 0, &dpio_dev->mc_io);
1439 + if (err) {
1440 + dev_dbg(dev, "MC portal allocation failed\n");
1441 + err = -EPROBE_DEFER;
1442 + goto err_mcportal;
1443 + }
1444 +
1445 + err = dpio_open(dpio_dev->mc_io, 0, dpio_dev->obj_desc.id,
1446 + &dpio_dev->mc_handle);
1447 + if (err) {
1448 + dev_err(dev, "dpio_open() failed\n");
1449 + goto err_open;
1450 + }
1451 +
1452 + err = dpio_get_attributes(dpio_dev->mc_io, 0, dpio_dev->mc_handle,
1453 + &dpio_attrs);
1454 + if (err) {
1455 + dev_err(dev, "dpio_get_attributes() failed %d\n", err);
1456 + goto err_get_attr;
1457 + }
1458 + desc.qman_version = dpio_attrs.qbman_version;
1459 +
1460 + err = dpio_enable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1461 + if (err) {
1462 + dev_err(dev, "dpio_enable() failed %d\n", err);
1463 + goto err_get_attr;
1464 + }
1465 +
1466 + /* initialize DPIO descriptor */
1467 + desc.receives_notifications = dpio_attrs.num_priorities ? 1 : 0;
1468 + desc.has_8prio = dpio_attrs.num_priorities == 8 ? 1 : 0;
1469 + desc.dpio_id = dpio_dev->obj_desc.id;
1470 +
1471 + /* get the cpu to use for the affinity hint */
1472 + if (next_cpu == -1)
1473 + next_cpu = cpumask_first(cpu_online_mask);
1474 + else
1475 + next_cpu = cpumask_next(next_cpu, cpu_online_mask);
1476 +
1477 + if (!cpu_possible(next_cpu)) {
1478 + dev_err(dev, "probe failed. Number of DPIOs exceeds NR_CPUS.\n");
1479 + err = -ERANGE;
1480 + goto err_allocate_irqs;
1481 + }
1482 + desc.cpu = next_cpu;
1483 +
1484 + /*
1485 + * Set the CENA regs to be the cache enabled area of the portal to
1486 + * achieve the best performance.
1487 + */
1488 + desc.regs_cena = ioremap_cache_ns(dpio_dev->regions[0].start,
1489 + resource_size(&dpio_dev->regions[0]));
1490 + desc.regs_cinh = ioremap(dpio_dev->regions[1].start,
1491 + resource_size(&dpio_dev->regions[1]));
1492 +
1493 + err = fsl_mc_allocate_irqs(dpio_dev);
1494 + if (err) {
1495 + dev_err(dev, "fsl_mc_allocate_irqs failed. err=%d\n", err);
1496 + goto err_allocate_irqs;
1497 + }
1498 +
1499 + err = register_dpio_irq_handlers(dpio_dev, desc.cpu);
1500 + if (err)
1501 + goto err_register_dpio_irq;
1502 +
1503 + priv->io = dpaa2_io_create(&desc);
1504 + if (!priv->io) {
1505 + dev_err(dev, "dpaa2_io_create failed\n");
1506 + goto err_dpaa2_io_create;
1507 + }
1508 +
1509 + dev_info(dev, "probed\n");
1510 + dev_dbg(dev, " receives_notifications = %d\n",
1511 + desc.receives_notifications);
1512 + dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1513 + fsl_mc_portal_free(dpio_dev->mc_io);
1514 +
1515 + return 0;
1516 +
1517 +err_dpaa2_io_create:
1518 + unregister_dpio_irq_handlers(dpio_dev);
1519 +err_register_dpio_irq:
1520 + fsl_mc_free_irqs(dpio_dev);
1521 +err_allocate_irqs:
1522 + dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1523 +err_get_attr:
1524 + dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1525 +err_open:
1526 + fsl_mc_portal_free(dpio_dev->mc_io);
1527 +err_mcportal:
1528 + dev_set_drvdata(dev, NULL);
1529 +err_priv_alloc:
1530 + return err;
1531 +}
1532 +
1533 +/* Tear down interrupts for a given DPIO object */
1534 +static void dpio_teardown_irqs(struct fsl_mc_device *dpio_dev)
1535 +{
1536 + unregister_dpio_irq_handlers(dpio_dev);
1537 + fsl_mc_free_irqs(dpio_dev);
1538 +}
1539 +
1540 +static int dpaa2_dpio_remove(struct fsl_mc_device *dpio_dev)
1541 +{
1542 + struct device *dev;
1543 + struct dpio_priv *priv;
1544 + int err;
1545 +
1546 + dev = &dpio_dev->dev;
1547 + priv = dev_get_drvdata(dev);
1548 +
1549 + dpaa2_io_down(priv->io);
1550 +
1551 + dpio_teardown_irqs(dpio_dev);
1552 +
1553 + err = fsl_mc_portal_allocate(dpio_dev, 0, &dpio_dev->mc_io);
1554 + if (err) {
1555 + dev_err(dev, "MC portal allocation failed\n");
1556 + goto err_mcportal;
1557 + }
1558 +
1559 + err = dpio_open(dpio_dev->mc_io, 0, dpio_dev->obj_desc.id,
1560 + &dpio_dev->mc_handle);
1561 + if (err) {
1562 + dev_err(dev, "dpio_open() failed\n");
1563 + goto err_open;
1564 + }
1565 +
1566 + dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1567 +
1568 + dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1569 +
1570 + fsl_mc_portal_free(dpio_dev->mc_io);
1571 +
1572 + dev_set_drvdata(dev, NULL);
1573 +
1574 + return 0;
1575 +
1576 +err_open:
1577 + fsl_mc_portal_free(dpio_dev->mc_io);
1578 +err_mcportal:
1579 + return err;
1580 +}
1581 +
1582 +static const struct fsl_mc_device_id dpaa2_dpio_match_id_table[] = {
1583 + {
1584 + .vendor = FSL_MC_VENDOR_FREESCALE,
1585 + .obj_type = "dpio",
1586 + },
1587 + { .vendor = 0x0 }
1588 +};
1589 +
1590 +static struct fsl_mc_driver dpaa2_dpio_driver = {
1591 + .driver = {
1592 + .name = KBUILD_MODNAME,
1593 + .owner = THIS_MODULE,
1594 + },
1595 + .probe = dpaa2_dpio_probe,
1596 + .remove = dpaa2_dpio_remove,
1597 + .match_id_table = dpaa2_dpio_match_id_table
1598 +};
1599 +
1600 +static int dpio_driver_init(void)
1601 +{
1602 + return fsl_mc_driver_register(&dpaa2_dpio_driver);
1603 +}
1604 +
1605 +static void dpio_driver_exit(void)
1606 +{
1607 + fsl_mc_driver_unregister(&dpaa2_dpio_driver);
1608 +}
1609 +module_init(dpio_driver_init);
1610 +module_exit(dpio_driver_exit);
1611 diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio-driver.txt b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.txt
1612 new file mode 100644
1613 index 00000000..0ba67716
1614 --- /dev/null
1615 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.txt
1616 @@ -0,0 +1,135 @@
1617 +Copyright 2016 NXP
1618 +
1619 +Introduction
1620 +------------
1621 +
1622 +A DPAA2 DPIO (Data Path I/O) is a hardware object that provides
1623 +interfaces to enqueue and dequeue frames to/from network interfaces
1624 +and other accelerators. A DPIO also provides hardware buffer
1625 +pool management for network interfaces.
1626 +
1627 +This document provides an overview the Linux DPIO driver, its
1628 +subcomponents, and its APIs.
1629 +
1630 +See Documentation/dpaa2/overview.txt for a general overview of DPAA2
1631 +and the general DPAA2 driver architecture in Linux.
1632 +
1633 +Driver Overview
1634 +---------------
1635 +
1636 +The DPIO driver is bound to DPIO objects discovered on the fsl-mc bus and
1637 +provides services that:
1638 + A) allow other drivers, such as the Ethernet driver, to enqueue and dequeue
1639 + frames for their respective objects
1640 + B) allow drivers to register callbacks for data availability notifications
1641 + when data becomes available on a queue or channel
1642 + C) allow drivers to manage hardware buffer pools
1643 +
1644 +The Linux DPIO driver consists of 3 primary components--
1645 + DPIO object driver-- fsl-mc driver that manages the DPIO object
1646 + DPIO service-- provides APIs to other Linux drivers for services
1647 + QBman portal interface-- sends portal commands, gets responses
1648 +
1649 + fsl-mc other
1650 + bus drivers
1651 + | |
1652 + +---+----+ +------+-----+
1653 + |DPIO obj| |DPIO service|
1654 + | driver |---| (DPIO) |
1655 + +--------+ +------+-----+
1656 + |
1657 + +------+-----+
1658 + | QBman |
1659 + | portal i/f |
1660 + +------------+
1661 + |
1662 + hardware
1663 +
1664 +The diagram below shows how the DPIO driver components fit with the other
1665 +DPAA2 Linux driver components:
1666 + +------------+
1667 + | OS Network |
1668 + | Stack |
1669 + +------------+ +------------+
1670 + | Allocator |. . . . . . . | Ethernet |
1671 + |(DPMCP,DPBP)| | (DPNI) |
1672 + +-.----------+ +---+---+----+
1673 + . . ^ |
1674 + . . <data avail, | |<enqueue,
1675 + . . tx confirm> | | dequeue>
1676 + +-------------+ . | |
1677 + | DPRC driver | . +--------+ +------------+
1678 + | (DPRC) | . . |DPIO obj| |DPIO service|
1679 + +----------+--+ | driver |-| (DPIO) |
1680 + | +--------+ +------+-----+
1681 + |<dev add/remove> +------|-----+
1682 + | | QBman |
1683 + +----+--------------+ | portal i/f |
1684 + | MC-bus driver | +------------+
1685 + | | |
1686 + | /soc/fsl-mc | |
1687 + +-------------------+ |
1688 + |
1689 + =========================================|=========|========================
1690 + +-+--DPIO---|-----------+
1691 + | | |
1692 + | QBman Portal |
1693 + +-----------------------+
1694 +
1695 + ============================================================================
1696 +
1697 +
1698 +DPIO Object Driver (dpio-driver.c)
1699 +----------------------------------
1700 +
1701 + The dpio-driver component registers with the fsl-mc bus to handle objects of
1702 + type "dpio". The implementation of probe() handles basic initialization
1703 + of the DPIO including mapping of the DPIO regions (the QBman SW portal)
1704 + and initializing interrupts and registering irq handlers. The dpio-driver
1705 + registers the probed DPIO with dpio-service.
1706 +
1707 +DPIO service (dpio-service.c, dpaa2-io.h)
1708 +------------------------------------------
1709 +
1710 + The dpio service component provides queuing, notification, and buffers
1711 + management services to DPAA2 drivers, such as the Ethernet driver. A system
1712 + will typically allocate 1 DPIO object per CPU to allow queuing operations
1713 + to happen simultaneously across all CPUs.
1714 +
1715 + Notification handling
1716 + dpaa2_io_service_register()
1717 + dpaa2_io_service_deregister()
1718 + dpaa2_io_service_rearm()
1719 +
1720 + Queuing
1721 + dpaa2_io_service_pull_fq()
1722 + dpaa2_io_service_pull_channel()
1723 + dpaa2_io_service_enqueue_fq()
1724 + dpaa2_io_service_enqueue_qd()
1725 + dpaa2_io_store_create()
1726 + dpaa2_io_store_destroy()
1727 + dpaa2_io_store_next()
1728 +
1729 + Buffer pool management
1730 + dpaa2_io_service_release()
1731 + dpaa2_io_service_acquire()
1732 +
1733 +QBman portal interface (qbman-portal.c)
1734 +---------------------------------------
1735 +
1736 + The qbman-portal component provides APIs to do the low level hardware
1737 + bit twiddling for operations such as:
1738 + -initializing Qman software portals
1739 + -building and sending portal commands
1740 + -portal interrupt configuration and processing
1741 +
1742 + The qbman-portal APIs are not public to other drivers, and are
1743 + only used by dpio-service.
1744 +
1745 +Other (dpaa2-fd.h, dpaa2-global.h)
1746 +----------------------------------
1747 +
1748 + Frame descriptor and scatter-gather definitions and the APIs used to
1749 + manipulate them are defined in dpaa2-fd.h.
1750 +
1751 + Dequeue result struct and parsing APIs are defined in dpaa2-global.h.
1752 diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio-service.c b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
1753 new file mode 100644
1754 index 00000000..46c32a67
1755 --- /dev/null
1756 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
1757 @@ -0,0 +1,689 @@
1758 +/*
1759 + * Copyright 2014-2016 Freescale Semiconductor Inc.
1760 + * Copyright 2016 NXP
1761 + *
1762 + * Redistribution and use in source and binary forms, with or without
1763 + * modification, are permitted provided that the following conditions are met:
1764 + * * Redistributions of source code must retain the above copyright
1765 + * notice, this list of conditions and the following disclaimer.
1766 + * * Redistributions in binary form must reproduce the above copyright
1767 + * notice, this list of conditions and the following disclaimer in the
1768 + * documentation and/or other materials provided with the distribution.
1769 + * * Neither the name of Freescale Semiconductor nor the
1770 + * names of its contributors may be used to endorse or promote products
1771 + * derived from this software without specific prior written permission.
1772 + *
1773 + * ALTERNATIVELY, this software may be distributed under the terms of the
1774 + * GNU General Public License ("GPL") as published by the Free Software
1775 + * Foundation, either version 2 of that License or (at your option) any
1776 + * later version.
1777 + *
1778 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
1779 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
1780 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
1781 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
1782 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1783 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
1784 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
1785 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1786 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
1787 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1788 + */
1789 +#include <linux/types.h>
1790 +#include "../../include/mc.h"
1791 +#include "../../include/dpaa2-io.h"
1792 +#include <linux/init.h>
1793 +#include <linux/module.h>
1794 +#include <linux/platform_device.h>
1795 +#include <linux/interrupt.h>
1796 +#include <linux/dma-mapping.h>
1797 +#include <linux/slab.h>
1798 +
1799 +#include "dpio.h"
1800 +#include "qbman-portal.h"
1801 +#include "qbman_debug.h"
1802 +
1803 +struct dpaa2_io {
1804 + atomic_t refs;
1805 + struct dpaa2_io_desc dpio_desc;
1806 + struct qbman_swp_desc swp_desc;
1807 + struct qbman_swp *swp;
1808 + struct list_head node;
1809 + /* protect against multiple management commands */
1810 + spinlock_t lock_mgmt_cmd;
1811 + /* protect notifications list */
1812 + spinlock_t lock_notifications;
1813 + struct list_head notifications;
1814 +};
1815 +
1816 +struct dpaa2_io_store {
1817 + unsigned int max;
1818 + dma_addr_t paddr;
1819 + struct dpaa2_dq *vaddr;
1820 + void *alloced_addr; /* unaligned value from kmalloc() */
1821 + unsigned int idx; /* position of the next-to-be-returned entry */
1822 + struct qbman_swp *swp; /* portal used to issue VDQCR */
1823 + struct device *dev; /* device used for DMA mapping */
1824 +};
1825 +
1826 +/* keep a per cpu array of DPIOs for fast access */
1827 +static struct dpaa2_io *dpio_by_cpu[NR_CPUS];
1828 +static struct list_head dpio_list = LIST_HEAD_INIT(dpio_list);
1829 +static DEFINE_SPINLOCK(dpio_list_lock);
1830 +
1831 +static inline struct dpaa2_io *service_select_by_cpu(struct dpaa2_io *d,
1832 + int cpu)
1833 +{
1834 + if (d)
1835 + return d;
1836 +
1837 + if (unlikely(cpu >= num_possible_cpus()))
1838 + return NULL;
1839 +
1840 + /*
1841 + * If cpu == -1, choose the current cpu, with no guarantees about
1842 + * potentially being migrated away.
1843 + */
1844 + if (unlikely(cpu < 0))
1845 + cpu = smp_processor_id();
1846 +
1847 + /* If a specific cpu was requested, pick it up immediately */
1848 + return dpio_by_cpu[cpu];
1849 +}
1850 +
1851 +static inline struct dpaa2_io *service_select(struct dpaa2_io *d)
1852 +{
1853 + if (d)
1854 + return d;
1855 +
1856 + spin_lock(&dpio_list_lock);
1857 + d = list_entry(dpio_list.next, struct dpaa2_io, node);
1858 + list_del(&d->node);
1859 + list_add_tail(&d->node, &dpio_list);
1860 + spin_unlock(&dpio_list_lock);
1861 +
1862 + return d;
1863 +}
1864 +
1865 +/**
1866 + * dpaa2_io_create() - create a dpaa2_io object.
1867 + * @desc: the dpaa2_io descriptor
1868 + *
1869 + * Activates a "struct dpaa2_io" corresponding to the given config of an actual
1870 + * DPIO object.
1871 + *
1872 + * Return a valid dpaa2_io object for success, or NULL for failure.
1873 + */
1874 +struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc)
1875 +{
1876 + struct dpaa2_io *obj = kmalloc(sizeof(*obj), GFP_KERNEL);
1877 +
1878 + if (!obj)
1879 + return NULL;
1880 +
1881 + /* check if CPU is out of range (-1 means any cpu) */
1882 + if (desc->cpu >= num_possible_cpus()) {
1883 + kfree(obj);
1884 + return NULL;
1885 + }
1886 +
1887 + atomic_set(&obj->refs, 1);
1888 + obj->dpio_desc = *desc;
1889 + obj->swp_desc.cena_bar = obj->dpio_desc.regs_cena;
1890 + obj->swp_desc.cinh_bar = obj->dpio_desc.regs_cinh;
1891 + obj->swp_desc.qman_version = obj->dpio_desc.qman_version;
1892 + obj->swp = qbman_swp_init(&obj->swp_desc);
1893 +
1894 + if (!obj->swp) {
1895 + kfree(obj);
1896 + return NULL;
1897 + }
1898 +
1899 + INIT_LIST_HEAD(&obj->node);
1900 + spin_lock_init(&obj->lock_mgmt_cmd);
1901 + spin_lock_init(&obj->lock_notifications);
1902 + INIT_LIST_HEAD(&obj->notifications);
1903 +
1904 + /* For now only enable DQRR interrupts */
1905 + qbman_swp_interrupt_set_trigger(obj->swp,
1906 + QBMAN_SWP_INTERRUPT_DQRI);
1907 + qbman_swp_interrupt_clear_status(obj->swp, 0xffffffff);
1908 + if (obj->dpio_desc.receives_notifications)
1909 + qbman_swp_push_set(obj->swp, 0, 1);
1910 +
1911 + spin_lock(&dpio_list_lock);
1912 + list_add_tail(&obj->node, &dpio_list);
1913 + if (desc->cpu >= 0 && !dpio_by_cpu[desc->cpu])
1914 + dpio_by_cpu[desc->cpu] = obj;
1915 + spin_unlock(&dpio_list_lock);
1916 +
1917 + return obj;
1918 +}
1919 +EXPORT_SYMBOL(dpaa2_io_create);
1920 +
1921 +/**
1922 + * dpaa2_io_down() - release the dpaa2_io object.
1923 + * @d: the dpaa2_io object to be released.
1924 + *
1925 + * The "struct dpaa2_io" type can represent an individual DPIO object (as
1926 + * described by "struct dpaa2_io_desc") or an instance of a "DPIO service",
1927 + * which can be used to group/encapsulate multiple DPIO objects. In all cases,
1928 + * each handle obtained should be released using this function.
1929 + */
1930 +void dpaa2_io_down(struct dpaa2_io *d)
1931 +{
1932 + if (!atomic_dec_and_test(&d->refs))
1933 + return;
1934 + kfree(d);
1935 +}
1936 +EXPORT_SYMBOL(dpaa2_io_down);
1937 +
1938 +#define DPAA_POLL_MAX 32
1939 +
1940 +/**
1941 + * dpaa2_io_irq() - ISR for DPIO interrupts
1942 + *
1943 + * @obj: the given DPIO object.
1944 + *
1945 + * Return IRQ_HANDLED for success or IRQ_NONE if there
1946 + * were no pending interrupts.
1947 + */
1948 +irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj)
1949 +{
1950 + const struct dpaa2_dq *dq;
1951 + int max = 0;
1952 + struct qbman_swp *swp;
1953 + u32 status;
1954 +
1955 + swp = obj->swp;
1956 + status = qbman_swp_interrupt_read_status(swp);
1957 + if (!status)
1958 + return IRQ_NONE;
1959 +
1960 + dq = qbman_swp_dqrr_next(swp);
1961 + while (dq) {
1962 + if (qbman_result_is_SCN(dq)) {
1963 + struct dpaa2_io_notification_ctx *ctx;
1964 + u64 q64;
1965 +
1966 + q64 = qbman_result_SCN_ctx(dq);
1967 + ctx = (void *)q64;
1968 + ctx->cb(ctx);
1969 + } else {
1970 + pr_crit("fsl-mc-dpio: Unrecognised/ignored DQRR entry\n");
1971 + }
1972 + qbman_swp_dqrr_consume(swp, dq);
1973 + ++max;
1974 + if (max > DPAA_POLL_MAX)
1975 + goto done;
1976 + dq = qbman_swp_dqrr_next(swp);
1977 + }
1978 +done:
1979 + qbman_swp_interrupt_clear_status(swp, status);
1980 + qbman_swp_interrupt_set_inhibit(swp, 0);
1981 + return IRQ_HANDLED;
1982 +}
1983 +EXPORT_SYMBOL(dpaa2_io_irq);
1984 +
1985 +/**
1986 + * dpaa2_io_service_register() - Prepare for servicing of FQDAN or CDAN
1987 + * notifications on the given DPIO service.
1988 + * @d: the given DPIO service.
1989 + * @ctx: the notification context.
1990 + *
1991 + * The caller should make the MC command to attach a DPAA2 object to
1992 + * a DPIO after this function completes successfully. In that way:
1993 + * (a) The DPIO service is "ready" to handle a notification arrival
1994 + * (which might happen before the "attach" command to MC has
1995 + * returned control of execution back to the caller)
1996 + * (b) The DPIO service can provide back to the caller the 'dpio_id' and
1997 + * 'qman64' parameters that it should pass along in the MC command
1998 + * in order for the object to be configured to produce the right
1999 + * notification fields to the DPIO service.
2000 + *
2001 + * Return 0 for success, or -ENODEV for failure.
2002 + */
2003 +int dpaa2_io_service_register(struct dpaa2_io *d,
2004 + struct dpaa2_io_notification_ctx *ctx)
2005 +{
2006 + unsigned long irqflags;
2007 +
2008 + d = service_select_by_cpu(d, ctx->desired_cpu);
2009 + if (!d)
2010 + return -ENODEV;
2011 +
2012 + ctx->dpio_id = d->dpio_desc.dpio_id;
2013 + ctx->qman64 = (u64)ctx;
2014 + ctx->dpio_private = d;
2015 + spin_lock_irqsave(&d->lock_notifications, irqflags);
2016 + list_add(&ctx->node, &d->notifications);
2017 + spin_unlock_irqrestore(&d->lock_notifications, irqflags);
2018 +
2019 + /* Enable the generation of CDAN notifications */
2020 + if (ctx->is_cdan)
2021 + qbman_swp_CDAN_set_context_enable(d->swp,
2022 + (u16)ctx->id,
2023 + ctx->qman64);
2024 + return 0;
2025 +}
2026 +EXPORT_SYMBOL(dpaa2_io_service_register);
2027 +
2028 +/**
2029 + * dpaa2_io_service_deregister - The opposite of 'register'.
2030 + * @service: the given DPIO service.
2031 + * @ctx: the notification context.
2032 + *
2033 + * This function should be called only after sending the MC command to
2034 + * to detach the notification-producing device from the DPIO.
2035 + */
2036 +void dpaa2_io_service_deregister(struct dpaa2_io *service,
2037 + struct dpaa2_io_notification_ctx *ctx)
2038 +{
2039 + struct dpaa2_io *d = ctx->dpio_private;
2040 + unsigned long irqflags;
2041 +
2042 + if (ctx->is_cdan)
2043 + qbman_swp_CDAN_disable(d->swp, (u16)ctx->id);
2044 +
2045 + spin_lock_irqsave(&d->lock_notifications, irqflags);
2046 + list_del(&ctx->node);
2047 + spin_unlock_irqrestore(&d->lock_notifications, irqflags);
2048 +}
2049 +EXPORT_SYMBOL(dpaa2_io_service_deregister);
2050 +
2051 +/**
2052 + * dpaa2_io_service_rearm() - Rearm the notification for the given DPIO service.
2053 + * @d: the given DPIO service.
2054 + * @ctx: the notification context.
2055 + *
2056 + * Once a FQDAN/CDAN has been produced, the corresponding FQ/channel is
2057 + * considered "disarmed". Ie. the user can issue pull dequeue operations on that
2058 + * traffic source for as long as it likes. Eventually it may wish to "rearm"
2059 + * that source to allow it to produce another FQDAN/CDAN, that's what this
2060 + * function achieves.
2061 + *
2062 + * Return 0 for success.
2063 + */
2064 +int dpaa2_io_service_rearm(struct dpaa2_io *d,
2065 + struct dpaa2_io_notification_ctx *ctx)
2066 +{
2067 + unsigned long irqflags;
2068 + int err;
2069 +
2070 + d = service_select_by_cpu(d, ctx->desired_cpu);
2071 + if (!unlikely(d))
2072 + return -ENODEV;
2073 +
2074 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
2075 + if (ctx->is_cdan)
2076 + err = qbman_swp_CDAN_enable(d->swp, (u16)ctx->id);
2077 + else
2078 + err = qbman_swp_fq_schedule(d->swp, ctx->id);
2079 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
2080 +
2081 + return err;
2082 +}
2083 +EXPORT_SYMBOL(dpaa2_io_service_rearm);
2084 +
2085 +/**
2086 + * dpaa2_io_service_pull_fq() - pull dequeue functions from a fq.
2087 + * @d: the given DPIO service.
2088 + * @fqid: the given frame queue id.
2089 + * @s: the dpaa2_io_store object for the result.
2090 + *
2091 + * Return 0 for success, or error code for failure.
2092 + */
2093 +int dpaa2_io_service_pull_fq(struct dpaa2_io *d, u32 fqid,
2094 + struct dpaa2_io_store *s)
2095 +{
2096 + struct qbman_pull_desc pd;
2097 + int err;
2098 +
2099 + qbman_pull_desc_clear(&pd);
2100 + qbman_pull_desc_set_storage(&pd, s->vaddr, s->paddr, 1);
2101 + qbman_pull_desc_set_numframes(&pd, (u8)s->max);
2102 + qbman_pull_desc_set_fq(&pd, fqid);
2103 +
2104 + d = service_select(d);
2105 + if (!d)
2106 + return -ENODEV;
2107 + s->swp = d->swp;
2108 + err = qbman_swp_pull(d->swp, &pd);
2109 + if (err)
2110 + s->swp = NULL;
2111 +
2112 + return err;
2113 +}
2114 +EXPORT_SYMBOL(dpaa2_io_service_pull_fq);
2115 +
2116 +/**
2117 + * dpaa2_io_service_pull_channel() - pull dequeue functions from a channel.
2118 + * @d: the given DPIO service.
2119 + * @channelid: the given channel id.
2120 + * @s: the dpaa2_io_store object for the result.
2121 + *
2122 + * Return 0 for success, or error code for failure.
2123 + */
2124 +int dpaa2_io_service_pull_channel(struct dpaa2_io *d, u32 channelid,
2125 + struct dpaa2_io_store *s)
2126 +{
2127 + struct qbman_pull_desc pd;
2128 + int err;
2129 +
2130 + qbman_pull_desc_clear(&pd);
2131 + qbman_pull_desc_set_storage(&pd, s->vaddr, s->paddr, 1);
2132 + qbman_pull_desc_set_numframes(&pd, (u8)s->max);
2133 + qbman_pull_desc_set_channel(&pd, channelid, qbman_pull_type_prio);
2134 +
2135 + d = service_select(d);
2136 + if (!d)
2137 + return -ENODEV;
2138 +
2139 + s->swp = d->swp;
2140 + err = qbman_swp_pull(d->swp, &pd);
2141 + if (err)
2142 + s->swp = NULL;
2143 +
2144 + return err;
2145 +}
2146 +EXPORT_SYMBOL(dpaa2_io_service_pull_channel);
2147 +
2148 +/**
2149 + * dpaa2_io_service_enqueue_fq() - Enqueue a frame to a frame queue.
2150 + * @d: the given DPIO service.
2151 + * @fqid: the given frame queue id.
2152 + * @fd: the frame descriptor which is enqueued.
2153 + *
2154 + * Return 0 for successful enqueue, -EBUSY if the enqueue ring is not ready,
2155 + * or -ENODEV if there is no dpio service.
2156 + */
2157 +int dpaa2_io_service_enqueue_fq(struct dpaa2_io *d,
2158 + u32 fqid,
2159 + const struct dpaa2_fd *fd)
2160 +{
2161 + struct qbman_eq_desc ed;
2162 +
2163 + d = service_select(d);
2164 + if (!d)
2165 + return -ENODEV;
2166 +
2167 + qbman_eq_desc_clear(&ed);
2168 + qbman_eq_desc_set_no_orp(&ed, 0);
2169 + qbman_eq_desc_set_fq(&ed, fqid);
2170 +
2171 + return qbman_swp_enqueue(d->swp, &ed, fd);
2172 +}
2173 +EXPORT_SYMBOL(dpaa2_io_service_enqueue_fq);
2174 +
2175 +/**
2176 + * dpaa2_io_service_enqueue_qd() - Enqueue a frame to a QD.
2177 + * @d: the given DPIO service.
2178 + * @qdid: the given queuing destination id.
2179 + * @prio: the given queuing priority.
2180 + * @qdbin: the given queuing destination bin.
2181 + * @fd: the frame descriptor which is enqueued.
2182 + *
2183 + * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready,
2184 + * or -ENODEV if there is no dpio service.
2185 + */
2186 +int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d,
2187 + u32 qdid, u8 prio, u16 qdbin,
2188 + const struct dpaa2_fd *fd)
2189 +{
2190 + struct qbman_eq_desc ed;
2191 +
2192 + d = service_select(d);
2193 + if (!d)
2194 + return -ENODEV;
2195 +
2196 + qbman_eq_desc_clear(&ed);
2197 + qbman_eq_desc_set_no_orp(&ed, 0);
2198 + qbman_eq_desc_set_qd(&ed, qdid, qdbin, prio);
2199 +
2200 + return qbman_swp_enqueue(d->swp, &ed, fd);
2201 +}
2202 +EXPORT_SYMBOL(dpaa2_io_service_enqueue_qd);
2203 +
2204 +/**
2205 + * dpaa2_io_service_release() - Release buffers to a buffer pool.
2206 + * @d: the given DPIO object.
2207 + * @bpid: the buffer pool id.
2208 + * @buffers: the buffers to be released.
2209 + * @num_buffers: the number of the buffers to be released.
2210 + *
2211 + * Return 0 for success, and negative error code for failure.
2212 + */
2213 +int dpaa2_io_service_release(struct dpaa2_io *d,
2214 + u32 bpid,
2215 + const u64 *buffers,
2216 + unsigned int num_buffers)
2217 +{
2218 + struct qbman_release_desc rd;
2219 +
2220 + d = service_select(d);
2221 + if (!d)
2222 + return -ENODEV;
2223 +
2224 + qbman_release_desc_clear(&rd);
2225 + qbman_release_desc_set_bpid(&rd, bpid);
2226 +
2227 + return qbman_swp_release(d->swp, &rd, buffers, num_buffers);
2228 +}
2229 +EXPORT_SYMBOL(dpaa2_io_service_release);
2230 +
2231 +/**
2232 + * dpaa2_io_service_acquire() - Acquire buffers from a buffer pool.
2233 + * @d: the given DPIO object.
2234 + * @bpid: the buffer pool id.
2235 + * @buffers: the buffer addresses for acquired buffers.
2236 + * @num_buffers: the expected number of the buffers to acquire.
2237 + *
2238 + * Return a negative error code if the command failed, otherwise it returns
2239 + * the number of buffers acquired, which may be less than the number requested.
2240 + * Eg. if the buffer pool is empty, this will return zero.
2241 + */
2242 +int dpaa2_io_service_acquire(struct dpaa2_io *d,
2243 + u32 bpid,
2244 + u64 *buffers,
2245 + unsigned int num_buffers)
2246 +{
2247 + unsigned long irqflags;
2248 + int err;
2249 +
2250 + d = service_select(d);
2251 + if (!d)
2252 + return -ENODEV;
2253 +
2254 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
2255 + err = qbman_swp_acquire(d->swp, bpid, buffers, num_buffers);
2256 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
2257 +
2258 + return err;
2259 +}
2260 +EXPORT_SYMBOL(dpaa2_io_service_acquire);
2261 +
2262 +/*
2263 + * 'Stores' are reusable memory blocks for holding dequeue results, and to
2264 + * assist with parsing those results.
2265 + */
2266 +
2267 +/**
2268 + * dpaa2_io_store_create() - Create the dma memory storage for dequeue result.
2269 + * @max_frames: the maximum number of dequeued result for frames, must be <= 16.
2270 + * @dev: the device to allow mapping/unmapping the DMAable region.
2271 + *
2272 + * The size of the storage is "max_frames*sizeof(struct dpaa2_dq)".
2273 + * The 'dpaa2_io_store' returned is a DPIO service managed object.
2274 + *
2275 + * Return pointer to dpaa2_io_store struct for successfuly created storage
2276 + * memory, or NULL on error.
2277 + */
2278 +struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames,
2279 + struct device *dev)
2280 +{
2281 + struct dpaa2_io_store *ret;
2282 + size_t size;
2283 +
2284 + if (!max_frames || (max_frames > 16))
2285 + return NULL;
2286 +
2287 + ret = kmalloc(sizeof(*ret), GFP_KERNEL);
2288 + if (!ret)
2289 + return NULL;
2290 +
2291 + ret->max = max_frames;
2292 + size = max_frames * sizeof(struct dpaa2_dq) + 64;
2293 + ret->alloced_addr = kzalloc(size, GFP_KERNEL);
2294 + if (!ret->alloced_addr) {
2295 + kfree(ret);
2296 + return NULL;
2297 + }
2298 +
2299 + ret->vaddr = PTR_ALIGN(ret->alloced_addr, 64);
2300 + ret->paddr = dma_map_single(dev, ret->vaddr,
2301 + sizeof(struct dpaa2_dq) * max_frames,
2302 + DMA_FROM_DEVICE);
2303 + if (dma_mapping_error(dev, ret->paddr)) {
2304 + kfree(ret->alloced_addr);
2305 + kfree(ret);
2306 + return NULL;
2307 + }
2308 +
2309 + ret->idx = 0;
2310 + ret->dev = dev;
2311 +
2312 + return ret;
2313 +}
2314 +EXPORT_SYMBOL(dpaa2_io_store_create);
2315 +
2316 +/**
2317 + * dpaa2_io_store_destroy() - Frees the dma memory storage for dequeue
2318 + * result.
2319 + * @s: the storage memory to be destroyed.
2320 + */
2321 +void dpaa2_io_store_destroy(struct dpaa2_io_store *s)
2322 +{
2323 + dma_unmap_single(s->dev, s->paddr, sizeof(struct dpaa2_dq) * s->max,
2324 + DMA_FROM_DEVICE);
2325 + kfree(s->alloced_addr);
2326 + kfree(s);
2327 +}
2328 +EXPORT_SYMBOL(dpaa2_io_store_destroy);
2329 +
2330 +/**
2331 + * dpaa2_io_store_next() - Determine when the next dequeue result is available.
2332 + * @s: the dpaa2_io_store object.
2333 + * @is_last: indicate whether this is the last frame in the pull command.
2334 + *
2335 + * When an object driver performs dequeues to a dpaa2_io_store, this function
2336 + * can be used to determine when the next frame result is available. Once
2337 + * this function returns non-NULL, a subsequent call to it will try to find
2338 + * the next dequeue result.
2339 + *
2340 + * Note that if a pull-dequeue has a NULL result because the target FQ/channel
2341 + * was empty, then this function will also return NULL (rather than expecting
2342 + * the caller to always check for this. As such, "is_last" can be used to
2343 + * differentiate between "end-of-empty-dequeue" and "still-waiting".
2344 + *
2345 + * Return dequeue result for a valid dequeue result, or NULL for empty dequeue.
2346 + */
2347 +struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last)
2348 +{
2349 + int match;
2350 + struct dpaa2_dq *ret = &s->vaddr[s->idx];
2351 +
2352 + match = qbman_result_has_new_result(s->swp, ret);
2353 + if (!match) {
2354 + *is_last = 0;
2355 + return NULL;
2356 + }
2357 +
2358 + s->idx++;
2359 +
2360 + if (dpaa2_dq_is_pull_complete(ret)) {
2361 + *is_last = 1;
2362 + s->idx = 0;
2363 + /*
2364 + * If we get an empty dequeue result to terminate a zero-results
2365 + * vdqcr, return NULL to the caller rather than expecting him to
2366 + * check non-NULL results every time.
2367 + */
2368 + if (!(dpaa2_dq_flags(ret) & DPAA2_DQ_STAT_VALIDFRAME))
2369 + ret = NULL;
2370 + } else {
2371 + *is_last = 0;
2372 + }
2373 +
2374 + return ret;
2375 +}
2376 +EXPORT_SYMBOL(dpaa2_io_store_next);
2377 +
2378 +#ifdef CONFIG_FSL_QBMAN_DEBUG
2379 +/**
2380 + * dpaa2_io_query_fq_count() - Get the frame and byte count for a given fq.
2381 + * @d: the given DPIO object.
2382 + * @fqid: the id of frame queue to be queried.
2383 + * @fcnt: the queried frame count.
2384 + * @bcnt: the queried byte count.
2385 + *
2386 + * Knowing the FQ count at run-time can be useful in debugging situations.
2387 + * The instantaneous frame- and byte-count are hereby returned.
2388 + *
2389 + * Return 0 for a successful query, and negative error code if query fails.
2390 + */
2391 +int dpaa2_io_query_fq_count(struct dpaa2_io *d, uint32_t fqid,
2392 + u32 *fcnt, u32 *bcnt)
2393 +{
2394 + struct qbman_attr state;
2395 + struct qbman_swp *swp;
2396 + unsigned long irqflags;
2397 + int ret;
2398 +
2399 + d = service_select(d);
2400 + if (!d)
2401 + return -ENODEV;
2402 +
2403 + swp = d->swp;
2404 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
2405 + ret = qbman_fq_query_state(swp, fqid, &state);
2406 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
2407 + if (ret)
2408 + return ret;
2409 + *fcnt = qbman_fq_state_frame_count(&state);
2410 + *bcnt = qbman_fq_state_byte_count(&state);
2411 +
2412 + return 0;
2413 +}
2414 +EXPORT_SYMBOL(dpaa2_io_query_fq_count);
2415 +
2416 +/**
2417 + * dpaa2_io_query_bp_count() - Query the number of buffers currenty in a
2418 + * buffer pool.
2419 + * @d: the given DPIO object.
2420 + * @bpid: the index of buffer pool to be queried.
2421 + * @num: the queried number of buffers in the buffer pool.
2422 + *
2423 + * Return 0 for a sucessful query, and negative error code if query fails.
2424 + */
2425 +int dpaa2_io_query_bp_count(struct dpaa2_io *d, uint32_t bpid, u32 *num)
2426 +{
2427 + struct qbman_attr state;
2428 + struct qbman_swp *swp;
2429 + unsigned long irqflags;
2430 + int ret;
2431 +
2432 + d = service_select(d);
2433 + if (!d)
2434 + return -ENODEV;
2435 +
2436 + swp = d->swp;
2437 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
2438 + ret = qbman_bp_query(swp, bpid, &state);
2439 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
2440 + if (ret)
2441 + return ret;
2442 + *num = qbman_bp_info_num_free_bufs(&state);
2443 + return 0;
2444 +}
2445 +EXPORT_SYMBOL(dpaa2_io_query_bp_count);
2446 +#endif
2447 diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio.c b/drivers/staging/fsl-mc/bus/dpio/dpio.c
2448 new file mode 100644
2449 index 00000000..d81e0232
2450 --- /dev/null
2451 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio.c
2452 @@ -0,0 +1,224 @@
2453 +/*
2454 + * Copyright 2013-2016 Freescale Semiconductor Inc.
2455 + * Copyright 2016 NXP
2456 + *
2457 + * Redistribution and use in source and binary forms, with or without
2458 + * modification, are permitted provided that the following conditions are met:
2459 + * * Redistributions of source code must retain the above copyright
2460 + * notice, this list of conditions and the following disclaimer.
2461 + * * Redistributions in binary form must reproduce the above copyright
2462 + * notice, this list of conditions and the following disclaimer in the
2463 + * documentation and/or other materials provided with the distribution.
2464 + * * Neither the name of the above-listed copyright holders nor the
2465 + * names of any contributors may be used to endorse or promote products
2466 + * derived from this software without specific prior written permission.
2467 + *
2468 + * ALTERNATIVELY, this software may be distributed under the terms of the
2469 + * GNU General Public License ("GPL") as published by the Free Software
2470 + * Foundation, either version 2 of that License or (at your option) any
2471 + * later version.
2472 + *
2473 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
2474 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2475 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2476 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
2477 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2478 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2479 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2480 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2481 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2482 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2483 + * POSSIBILITY OF SUCH DAMAGE.
2484 + */
2485 +#include "../../include/mc-sys.h"
2486 +#include "../../include/mc-cmd.h"
2487 +
2488 +#include "dpio.h"
2489 +#include "dpio-cmd.h"
2490 +
2491 +/*
2492 + * Data Path I/O Portal API
2493 + * Contains initialization APIs and runtime control APIs for DPIO
2494 + */
2495 +
2496 +/**
2497 + * dpio_open() - Open a control session for the specified object
2498 + * @mc_io: Pointer to MC portal's I/O object
2499 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2500 + * @dpio_id: DPIO unique ID
2501 + * @token: Returned token; use in subsequent API calls
2502 + *
2503 + * This function can be used to open a control session for an
2504 + * already created object; an object may have been declared in
2505 + * the DPL or by calling the dpio_create() function.
2506 + * This function returns a unique authentication token,
2507 + * associated with the specific object ID and the specific MC
2508 + * portal; this token must be used in all subsequent commands for
2509 + * this specific object.
2510 + *
2511 + * Return: '0' on Success; Error code otherwise.
2512 + */
2513 +int dpio_open(struct fsl_mc_io *mc_io,
2514 + u32 cmd_flags,
2515 + int dpio_id,
2516 + u16 *token)
2517 +{
2518 + struct mc_command cmd = { 0 };
2519 + struct dpio_cmd_open *dpio_cmd;
2520 + int err;
2521 +
2522 + /* prepare command */
2523 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_OPEN,
2524 + cmd_flags,
2525 + 0);
2526 + dpio_cmd = (struct dpio_cmd_open *)cmd.params;
2527 + dpio_cmd->dpio_id = cpu_to_le32(dpio_id);
2528 +
2529 + err = mc_send_command(mc_io, &cmd);
2530 + if (err)
2531 + return err;
2532 +
2533 + /* retrieve response parameters */
2534 + *token = mc_cmd_hdr_read_token(&cmd);
2535 +
2536 + return 0;
2537 +}
2538 +
2539 +/**
2540 + * dpio_close() - Close the control session of the object
2541 + * @mc_io: Pointer to MC portal's I/O object
2542 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2543 + * @token: Token of DPIO object
2544 + *
2545 + * Return: '0' on Success; Error code otherwise.
2546 + */
2547 +int dpio_close(struct fsl_mc_io *mc_io,
2548 + u32 cmd_flags,
2549 + u16 token)
2550 +{
2551 + struct mc_command cmd = { 0 };
2552 +
2553 + /* prepare command */
2554 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_CLOSE,
2555 + cmd_flags,
2556 + token);
2557 +
2558 + return mc_send_command(mc_io, &cmd);
2559 +}
2560 +
2561 +/**
2562 + * dpio_enable() - Enable the DPIO, allow I/O portal operations.
2563 + * @mc_io: Pointer to MC portal's I/O object
2564 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2565 + * @token: Token of DPIO object
2566 + *
2567 + * Return: '0' on Success; Error code otherwise
2568 + */
2569 +int dpio_enable(struct fsl_mc_io *mc_io,
2570 + u32 cmd_flags,
2571 + u16 token)
2572 +{
2573 + struct mc_command cmd = { 0 };
2574 +
2575 + /* prepare command */
2576 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_ENABLE,
2577 + cmd_flags,
2578 + token);
2579 +
2580 + return mc_send_command(mc_io, &cmd);
2581 +}
2582 +
2583 +/**
2584 + * dpio_disable() - Disable the DPIO, stop any I/O portal operation.
2585 + * @mc_io: Pointer to MC portal's I/O object
2586 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2587 + * @token: Token of DPIO object
2588 + *
2589 + * Return: '0' on Success; Error code otherwise
2590 + */
2591 +int dpio_disable(struct fsl_mc_io *mc_io,
2592 + u32 cmd_flags,
2593 + u16 token)
2594 +{
2595 + struct mc_command cmd = { 0 };
2596 +
2597 + /* prepare command */
2598 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_DISABLE,
2599 + cmd_flags,
2600 + token);
2601 +
2602 + return mc_send_command(mc_io, &cmd);
2603 +}
2604 +
2605 +/**
2606 + * dpio_get_attributes() - Retrieve DPIO attributes
2607 + * @mc_io: Pointer to MC portal's I/O object
2608 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2609 + * @token: Token of DPIO object
2610 + * @attr: Returned object's attributes
2611 + *
2612 + * Return: '0' on Success; Error code otherwise
2613 + */
2614 +int dpio_get_attributes(struct fsl_mc_io *mc_io,
2615 + u32 cmd_flags,
2616 + u16 token,
2617 + struct dpio_attr *attr)
2618 +{
2619 + struct mc_command cmd = { 0 };
2620 + struct dpio_rsp_get_attr *dpio_rsp;
2621 + int err;
2622 +
2623 + /* prepare command */
2624 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_ATTR,
2625 + cmd_flags,
2626 + token);
2627 +
2628 + err = mc_send_command(mc_io, &cmd);
2629 + if (err)
2630 + return err;
2631 +
2632 + /* retrieve response parameters */
2633 + dpio_rsp = (struct dpio_rsp_get_attr *)cmd.params;
2634 + attr->id = le32_to_cpu(dpio_rsp->id);
2635 + attr->qbman_portal_id = le16_to_cpu(dpio_rsp->qbman_portal_id);
2636 + attr->num_priorities = dpio_rsp->num_priorities;
2637 + attr->channel_mode = dpio_rsp->channel_mode & DPIO_CHANNEL_MODE_MASK;
2638 + attr->qbman_portal_ce_offset =
2639 + le64_to_cpu(dpio_rsp->qbman_portal_ce_addr);
2640 + attr->qbman_portal_ci_offset =
2641 + le64_to_cpu(dpio_rsp->qbman_portal_ci_addr);
2642 + attr->qbman_version = le32_to_cpu(dpio_rsp->qbman_version);
2643 +
2644 + return 0;
2645 +}
2646 +
2647 +/**
2648 + * dpio_get_api_version - Get Data Path I/O API version
2649 + * @mc_io: Pointer to MC portal's DPIO object
2650 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2651 + * @major_ver: Major version of DPIO API
2652 + * @minor_ver: Minor version of DPIO API
2653 + *
2654 + * Return: '0' on Success; Error code otherwise
2655 + */
2656 +int dpio_get_api_version(struct fsl_mc_io *mc_io,
2657 + u32 cmd_flags,
2658 + u16 *major_ver,
2659 + u16 *minor_ver)
2660 +{
2661 + struct mc_command cmd = { 0 };
2662 + int err;
2663 +
2664 + /* prepare command */
2665 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_API_VERSION,
2666 + cmd_flags, 0);
2667 +
2668 + err = mc_send_command(mc_io, &cmd);
2669 + if (err)
2670 + return err;
2671 +
2672 + /* retrieve response parameters */
2673 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
2674 +
2675 + return 0;
2676 +}
2677 diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio.h b/drivers/staging/fsl-mc/bus/dpio/dpio.h
2678 new file mode 100644
2679 index 00000000..ced1103d
2680 --- /dev/null
2681 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio.h
2682 @@ -0,0 +1,109 @@
2683 +/*
2684 + * Copyright 2013-2016 Freescale Semiconductor Inc.
2685 + * Copyright 2016 NXP
2686 + *
2687 + * Redistribution and use in source and binary forms, with or without
2688 + * modification, are permitted provided that the following conditions are met:
2689 + * * Redistributions of source code must retain the above copyright
2690 + * notice, this list of conditions and the following disclaimer.
2691 + * * Redistributions in binary form must reproduce the above copyright
2692 + * notice, this list of conditions and the following disclaimer in the
2693 + * documentation and/or other materials provided with the distribution.
2694 + * * Neither the name of the above-listed copyright holders nor the
2695 + * names of any contributors may be used to endorse or promote products
2696 + * derived from this software without specific prior written permission.
2697 + *
2698 + * ALTERNATIVELY, this software may be distributed under the terms of the
2699 + * GNU General Public License ("GPL") as published by the Free Software
2700 + * Foundation, either version 2 of that License or (at your option) any
2701 + * later version.
2702 + *
2703 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
2704 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2705 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2706 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
2707 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2708 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2709 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2710 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2711 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2712 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2713 + * POSSIBILITY OF SUCH DAMAGE.
2714 + */
2715 +#ifndef __FSL_DPIO_H
2716 +#define __FSL_DPIO_H
2717 +
2718 +struct fsl_mc_io;
2719 +
2720 +int dpio_open(struct fsl_mc_io *mc_io,
2721 + u32 cmd_flags,
2722 + int dpio_id,
2723 + u16 *token);
2724 +
2725 +int dpio_close(struct fsl_mc_io *mc_io,
2726 + u32 cmd_flags,
2727 + u16 token);
2728 +
2729 +/**
2730 + * enum dpio_channel_mode - DPIO notification channel mode
2731 + * @DPIO_NO_CHANNEL: No support for notification channel
2732 + * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a
2733 + * dedicated channel in the DPIO; user should point the queue's
2734 + * destination in the relevant interface to this DPIO
2735 + */
2736 +enum dpio_channel_mode {
2737 + DPIO_NO_CHANNEL = 0,
2738 + DPIO_LOCAL_CHANNEL = 1,
2739 +};
2740 +
2741 +/**
2742 + * struct dpio_cfg - Structure representing DPIO configuration
2743 + * @channel_mode: Notification channel mode
2744 + * @num_priorities: Number of priorities for the notification channel (1-8);
2745 + * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
2746 + */
2747 +struct dpio_cfg {
2748 + enum dpio_channel_mode channel_mode;
2749 + u8 num_priorities;
2750 +};
2751 +
2752 +int dpio_enable(struct fsl_mc_io *mc_io,
2753 + u32 cmd_flags,
2754 + u16 token);
2755 +
2756 +int dpio_disable(struct fsl_mc_io *mc_io,
2757 + u32 cmd_flags,
2758 + u16 token);
2759 +
2760 +/**
2761 + * struct dpio_attr - Structure representing DPIO attributes
2762 + * @id: DPIO object ID
2763 + * @qbman_portal_ce_offset: offset of the software portal cache-enabled area
2764 + * @qbman_portal_ci_offset: offset of the software portal cache-inhibited area
2765 + * @qbman_portal_id: Software portal ID
2766 + * @channel_mode: Notification channel mode
2767 + * @num_priorities: Number of priorities for the notification channel (1-8);
2768 + * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
2769 + * @qbman_version: QBMAN version
2770 + */
2771 +struct dpio_attr {
2772 + int id;
2773 + u64 qbman_portal_ce_offset;
2774 + u64 qbman_portal_ci_offset;
2775 + u16 qbman_portal_id;
2776 + enum dpio_channel_mode channel_mode;
2777 + u8 num_priorities;
2778 + u32 qbman_version;
2779 +};
2780 +
2781 +int dpio_get_attributes(struct fsl_mc_io *mc_io,
2782 + u32 cmd_flags,
2783 + u16 token,
2784 + struct dpio_attr *attr);
2785 +
2786 +int dpio_get_api_version(struct fsl_mc_io *mc_io,
2787 + u32 cmd_flags,
2788 + u16 *major_ver,
2789 + u16 *minor_ver);
2790 +
2791 +#endif /* __FSL_DPIO_H */
2792 diff --git a/drivers/staging/fsl-mc/bus/dpio/qbman-portal.c b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.c
2793 new file mode 100644
2794 index 00000000..e14fb65b
2795 --- /dev/null
2796 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.c
2797 @@ -0,0 +1,1049 @@
2798 +/*
2799 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
2800 + * Copyright 2016 NXP
2801 + *
2802 + * Redistribution and use in source and binary forms, with or without
2803 + * modification, are permitted provided that the following conditions are met:
2804 + * * Redistributions of source code must retain the above copyright
2805 + * notice, this list of conditions and the following disclaimer.
2806 + * * Redistributions in binary form must reproduce the above copyright
2807 + * notice, this list of conditions and the following disclaimer in the
2808 + * documentation and/or other materials provided with the distribution.
2809 + * * Neither the name of Freescale Semiconductor nor the
2810 + * names of its contributors may be used to endorse or promote products
2811 + * derived from this software without specific prior written permission.
2812 + *
2813 + * ALTERNATIVELY, this software may be distributed under the terms of the
2814 + * GNU General Public License ("GPL") as published by the Free Software
2815 + * Foundation, either version 2 of that License or (at your option) any
2816 + * later version.
2817 + *
2818 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
2819 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
2820 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
2821 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
2822 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
2823 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
2824 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
2825 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2826 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
2827 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2828 + */
2829 +
2830 +#include <asm/cacheflush.h>
2831 +#include <linux/io.h>
2832 +#include <linux/slab.h>
2833 +#include "../../include/dpaa2-global.h"
2834 +
2835 +#include "qbman-portal.h"
2836 +
2837 +struct qb_attr_code code_generic_verb = QB_CODE(0, 0, 7);
2838 +struct qb_attr_code code_generic_rslt = QB_CODE(0, 8, 8);
2839 +
2840 +#define QMAN_REV_4000 0x04000000
2841 +#define QMAN_REV_4100 0x04010000
2842 +#define QMAN_REV_4101 0x04010001
2843 +#define QMAN_REV_MASK 0xffff0000
2844 +
2845 +/* All QBMan command and result structures use this "valid bit" encoding */
2846 +#define QB_VALID_BIT ((u32)0x80)
2847 +
2848 +/* QBMan portal management command codes */
2849 +#define QBMAN_MC_ACQUIRE 0x30
2850 +#define QBMAN_WQCHAN_CONFIGURE 0x46
2851 +
2852 +/* CINH register offsets */
2853 +#define QBMAN_CINH_SWP_EQAR 0x8c0
2854 +#define QBMAN_CINH_SWP_DQPI 0xa00
2855 +#define QBMAN_CINH_SWP_DCAP 0xac0
2856 +#define QBMAN_CINH_SWP_SDQCR 0xb00
2857 +#define QBMAN_CINH_SWP_RAR 0xcc0
2858 +#define QBMAN_CINH_SWP_ISR 0xe00
2859 +#define QBMAN_CINH_SWP_IER 0xe40
2860 +#define QBMAN_CINH_SWP_ISDR 0xe80
2861 +#define QBMAN_CINH_SWP_IIR 0xec0
2862 +
2863 +/* CENA register offsets */
2864 +#define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((u32)(n) << 6))
2865 +#define QBMAN_CENA_SWP_DQRR(n) (0x200 + ((u32)(n) << 6))
2866 +#define QBMAN_CENA_SWP_RCR(n) (0x400 + ((u32)(n) << 6))
2867 +#define QBMAN_CENA_SWP_CR 0x600
2868 +#define QBMAN_CENA_SWP_RR(vb) (0x700 + ((u32)(vb) >> 1))
2869 +#define QBMAN_CENA_SWP_VDQCR 0x780
2870 +
2871 +/* Reverse mapping of QBMAN_CENA_SWP_DQRR() */
2872 +#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)(p) & 0x1ff) >> 6)
2873 +
2874 +/* Define token used to determine if response written to memory is valid */
2875 +#define QMAN_DQ_TOKEN_VALID 1
2876 +
2877 +/* SDQCR attribute codes */
2878 +#define QB_SDQCR_FC_SHIFT 29
2879 +#define QB_SDQCR_FC_MASK 0x1
2880 +#define QB_SDQCR_DCT_SHIFT 24
2881 +#define QB_SDQCR_DCT_MASK 0x3
2882 +#define QB_SDQCR_TOK_SHIFT 16
2883 +#define QB_SDQCR_TOK_MASK 0xff
2884 +#define QB_SDQCR_SRC_SHIFT 0
2885 +#define QB_SDQCR_SRC_MASK 0xffff
2886 +
2887 +/* opaque token for static dequeues */
2888 +#define QMAN_SDQCR_TOKEN 0xbb
2889 +
2890 +enum qbman_sdqcr_dct {
2891 + qbman_sdqcr_dct_null = 0,
2892 + qbman_sdqcr_dct_prio_ics,
2893 + qbman_sdqcr_dct_active_ics,
2894 + qbman_sdqcr_dct_active
2895 +};
2896 +
2897 +enum qbman_sdqcr_fc {
2898 + qbman_sdqcr_fc_one = 0,
2899 + qbman_sdqcr_fc_up_to_3 = 1
2900 +};
2901 +
2902 +#define dccvac(p) { asm volatile("dc cvac, %0;" : : "r" (p) : "memory"); }
2903 +#define dcivac(p) { asm volatile("dc ivac, %0" : : "r"(p) : "memory"); }
2904 +static inline void qbman_inval_prefetch(struct qbman_swp *p, uint32_t offset)
2905 +{
2906 + dcivac(p->addr_cena + offset);
2907 + prefetch(p->addr_cena + offset);
2908 +}
2909 +
2910 +/* Portal Access */
2911 +
2912 +static inline u32 qbman_read_register(struct qbman_swp *p, u32 offset)
2913 +{
2914 + return readl_relaxed(p->addr_cinh + offset);
2915 +}
2916 +
2917 +static inline void qbman_write_register(struct qbman_swp *p, u32 offset,
2918 + u32 value)
2919 +{
2920 + writel_relaxed(value, p->addr_cinh + offset);
2921 +}
2922 +
2923 +static inline void *qbman_get_cmd(struct qbman_swp *p, u32 offset)
2924 +{
2925 + return p->addr_cena + offset;
2926 +}
2927 +
2928 +#define QBMAN_CINH_SWP_CFG 0xd00
2929 +
2930 +#define SWP_CFG_DQRR_MF_SHIFT 20
2931 +#define SWP_CFG_EST_SHIFT 16
2932 +#define SWP_CFG_WN_SHIFT 14
2933 +#define SWP_CFG_RPM_SHIFT 12
2934 +#define SWP_CFG_DCM_SHIFT 10
2935 +#define SWP_CFG_EPM_SHIFT 8
2936 +#define SWP_CFG_SD_SHIFT 5
2937 +#define SWP_CFG_SP_SHIFT 4
2938 +#define SWP_CFG_SE_SHIFT 3
2939 +#define SWP_CFG_DP_SHIFT 2
2940 +#define SWP_CFG_DE_SHIFT 1
2941 +#define SWP_CFG_EP_SHIFT 0
2942 +
2943 +static inline u32 qbman_set_swp_cfg(u8 max_fill, u8 wn, u8 est, u8 rpm, u8 dcm,
2944 + u8 epm, int sd, int sp, int se,
2945 + int dp, int de, int ep)
2946 +{
2947 + return cpu_to_le32 (max_fill << SWP_CFG_DQRR_MF_SHIFT |
2948 + est << SWP_CFG_EST_SHIFT |
2949 + wn << SWP_CFG_WN_SHIFT |
2950 + rpm << SWP_CFG_RPM_SHIFT |
2951 + dcm << SWP_CFG_DCM_SHIFT |
2952 + epm << SWP_CFG_EPM_SHIFT |
2953 + sd << SWP_CFG_SD_SHIFT |
2954 + sp << SWP_CFG_SP_SHIFT |
2955 + se << SWP_CFG_SE_SHIFT |
2956 + dp << SWP_CFG_DP_SHIFT |
2957 + de << SWP_CFG_DE_SHIFT |
2958 + ep << SWP_CFG_EP_SHIFT);
2959 +}
2960 +
2961 +/**
2962 + * qbman_swp_init() - Create a functional object representing the given
2963 + * QBMan portal descriptor.
2964 + * @d: the given qbman swp descriptor
2965 + *
2966 + * Return qbman_swp portal for success, NULL if the object cannot
2967 + * be created.
2968 + */
2969 +struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
2970 +{
2971 + struct qbman_swp *p = kmalloc(sizeof(*p), GFP_KERNEL);
2972 + u32 reg;
2973 +
2974 + if (!p)
2975 + return NULL;
2976 + p->desc = d;
2977 + p->mc.valid_bit = QB_VALID_BIT;
2978 + p->sdq = 0;
2979 + p->sdq |= qbman_sdqcr_dct_prio_ics << QB_SDQCR_DCT_SHIFT;
2980 + p->sdq |= qbman_sdqcr_fc_up_to_3 << QB_SDQCR_FC_SHIFT;
2981 + p->sdq |= QMAN_SDQCR_TOKEN << QB_SDQCR_TOK_SHIFT;
2982 +
2983 + atomic_set(&p->vdq.available, 1);
2984 + p->vdq.valid_bit = QB_VALID_BIT;
2985 + p->dqrr.next_idx = 0;
2986 + p->dqrr.valid_bit = QB_VALID_BIT;
2987 +
2988 + if ((p->desc->qman_version & QMAN_REV_MASK) < QMAN_REV_4100) {
2989 + p->dqrr.dqrr_size = 4;
2990 + p->dqrr.reset_bug = 1;
2991 + } else {
2992 + p->dqrr.dqrr_size = 8;
2993 + p->dqrr.reset_bug = 0;
2994 + }
2995 +
2996 + p->addr_cena = d->cena_bar;
2997 + p->addr_cinh = d->cinh_bar;
2998 +
2999 + reg = qbman_set_swp_cfg(p->dqrr.dqrr_size,
3000 + 0, /* Writes cacheable */
3001 + 0, /* EQCR_CI stashing threshold */
3002 + 3, /* RPM: Valid bit mode, RCR in array mode */
3003 + 2, /* DCM: Discrete consumption ack mode */
3004 + 3, /* EPM: Valid bit mode, EQCR in array mode */
3005 + 0, /* mem stashing drop enable == FALSE */
3006 + 1, /* mem stashing priority == TRUE */
3007 + 0, /* mem stashing enable == FALSE */
3008 + 1, /* dequeue stashing priority == TRUE */
3009 + 0, /* dequeue stashing enable == FALSE */
3010 + 0); /* EQCR_CI stashing priority == FALSE */
3011 +
3012 + qbman_write_register(p, QBMAN_CINH_SWP_CFG, reg);
3013 + reg = qbman_read_register(p, QBMAN_CINH_SWP_CFG);
3014 + if (!reg) {
3015 + pr_err("qbman: the portal is not enabled!\n");
3016 + return NULL;
3017 + }
3018 +
3019 + /*
3020 + * SDQCR needs to be initialized to 0 when no channels are
3021 + * being dequeued from or else the QMan HW will indicate an
3022 + * error. The values that were calculated above will be
3023 + * applied when dequeues from a specific channel are enabled.
3024 + */
3025 + qbman_write_register(p, QBMAN_CINH_SWP_SDQCR, 0);
3026 + return p;
3027 +}
3028 +
3029 +/**
3030 + * qbman_swp_finish() - Create and destroy a functional object representing
3031 + * the given QBMan portal descriptor.
3032 + * @p: the qbman_swp object to be destroyed
3033 + */
3034 +void qbman_swp_finish(struct qbman_swp *p)
3035 +{
3036 + kfree(p);
3037 +}
3038 +
3039 +/**
3040 + * qbman_swp_interrupt_read_status()
3041 + * @p: the given software portal
3042 + *
3043 + * Return the value in the SWP_ISR register.
3044 + */
3045 +u32 qbman_swp_interrupt_read_status(struct qbman_swp *p)
3046 +{
3047 + return qbman_read_register(p, QBMAN_CINH_SWP_ISR);
3048 +}
3049 +
3050 +/**
3051 + * qbman_swp_interrupt_clear_status()
3052 + * @p: the given software portal
3053 + * @mask: The mask to clear in SWP_ISR register
3054 + */
3055 +void qbman_swp_interrupt_clear_status(struct qbman_swp *p, u32 mask)
3056 +{
3057 + qbman_write_register(p, QBMAN_CINH_SWP_ISR, mask);
3058 +}
3059 +
3060 +/**
3061 + * qbman_swp_interrupt_get_trigger() - read interrupt enable register
3062 + * @p: the given software portal
3063 + *
3064 + * Return the value in the SWP_IER register.
3065 + */
3066 +u32 qbman_swp_interrupt_get_trigger(struct qbman_swp *p)
3067 +{
3068 + return qbman_read_register(p, QBMAN_CINH_SWP_IER);
3069 +}
3070 +
3071 +/**
3072 + * qbman_swp_interrupt_set_trigger() - enable interrupts for a swp
3073 + * @p: the given software portal
3074 + * @mask: The mask of bits to enable in SWP_IER
3075 + */
3076 +void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, u32 mask)
3077 +{
3078 + qbman_write_register(p, QBMAN_CINH_SWP_IER, mask);
3079 +}
3080 +
3081 +/**
3082 + * qbman_swp_interrupt_get_inhibit() - read interrupt mask register
3083 + * @p: the given software portal object
3084 + *
3085 + * Return the value in the SWP_IIR register.
3086 + */
3087 +int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p)
3088 +{
3089 + return qbman_read_register(p, QBMAN_CINH_SWP_IIR);
3090 +}
3091 +
3092 +/**
3093 + * qbman_swp_interrupt_set_inhibit() - write interrupt mask register
3094 + * @p: the given software portal object
3095 + * @mask: The mask to set in SWP_IIR register
3096 + */
3097 +void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit)
3098 +{
3099 + qbman_write_register(p, QBMAN_CINH_SWP_IIR, inhibit ? 0xffffffff : 0);
3100 +}
3101 +
3102 +/*
3103 + * Different management commands all use this common base layer of code to issue
3104 + * commands and poll for results.
3105 + */
3106 +
3107 +/*
3108 + * Returns a pointer to where the caller should fill in their management command
3109 + * (caller should ignore the verb byte)
3110 + */
3111 +void *qbman_swp_mc_start(struct qbman_swp *p)
3112 +{
3113 + return qbman_get_cmd(p, QBMAN_CENA_SWP_CR);
3114 +}
3115 +
3116 +/*
3117 + * Commits merges in the caller-supplied command verb (which should not include
3118 + * the valid-bit) and submits the command to hardware
3119 + */
3120 +void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, u8 cmd_verb)
3121 +{
3122 + u8 *v = cmd;
3123 +
3124 + dma_wmb();
3125 + *v = cmd_verb | p->mc.valid_bit;
3126 + dccvac(cmd);
3127 +}
3128 +
3129 +/*
3130 + * Checks for a completed response (returns non-NULL if only if the response
3131 + * is complete).
3132 + */
3133 +void *qbman_swp_mc_result(struct qbman_swp *p)
3134 +{
3135 + u32 *ret, verb;
3136 +
3137 + qbman_inval_prefetch(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
3138 + ret = qbman_get_cmd(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
3139 +
3140 + /* Remove the valid-bit - command completed if the rest is non-zero */
3141 + verb = ret[0] & ~QB_VALID_BIT;
3142 + if (!verb)
3143 + return NULL;
3144 + p->mc.valid_bit ^= QB_VALID_BIT;
3145 + return ret;
3146 +}
3147 +
3148 +#define QB_ENQUEUE_CMD_OPTIONS_SHIFT 0
3149 +enum qb_enqueue_commands {
3150 + enqueue_empty = 0,
3151 + enqueue_response_always = 1,
3152 + enqueue_rejects_to_fq = 2
3153 +};
3154 +
3155 +#define QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT 2
3156 +#define QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT 3
3157 +#define QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT 4
3158 +
3159 +/**
3160 + * qbman_eq_desc_clear() - Clear the contents of a descriptor to
3161 + * default/starting state.
3162 + */
3163 +void qbman_eq_desc_clear(struct qbman_eq_desc *d)
3164 +{
3165 + memset(d, 0, sizeof(*d));
3166 +}
3167 +
3168 +/**
3169 + * qbman_eq_desc_set_no_orp() - Set enqueue descriptor without orp
3170 + * @d: the enqueue descriptor.
3171 + * @response_success: 1 = enqueue with response always; 0 = enqueue with
3172 + * rejections returned on a FQ.
3173 + */
3174 +void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success)
3175 +{
3176 + d->verb &= ~(1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT);
3177 + if (respond_success)
3178 + d->verb |= enqueue_response_always;
3179 + else
3180 + d->verb |= enqueue_rejects_to_fq;
3181 +}
3182 +
3183 +/*
3184 + * Exactly one of the following descriptor "targets" should be set. (Calling any
3185 + * one of these will replace the effect of any prior call to one of these.)
3186 + * -enqueue to a frame queue
3187 + * -enqueue to a queuing destination
3188 + */
3189 +
3190 +/**
3191 + * qbman_eq_desc_set_fq() - set the FQ for the enqueue command
3192 + * @d: the enqueue descriptor
3193 + * @fqid: the id of the frame queue to be enqueued
3194 + */
3195 +void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, u32 fqid)
3196 +{
3197 + d->verb &= ~(1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT);
3198 + d->tgtid = cpu_to_le32(fqid);
3199 +}
3200 +
3201 +/**
3202 + * qbman_eq_desc_set_qd() - Set Queuing Destination for the enqueue command
3203 + * @d: the enqueue descriptor
3204 + * @qdid: the id of the queuing destination to be enqueued
3205 + * @qd_bin: the queuing destination bin
3206 + * @qd_prio: the queuing destination priority
3207 + */
3208 +void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
3209 + u32 qd_bin, u32 qd_prio)
3210 +{
3211 + d->verb |= 1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT;
3212 + d->tgtid = cpu_to_le32(qdid);
3213 + d->qdbin = cpu_to_le16(qd_bin);
3214 + d->qpri = qd_prio;
3215 +}
3216 +
3217 +#define EQAR_IDX(eqar) ((eqar) & 0x7)
3218 +#define EQAR_VB(eqar) ((eqar) & 0x80)
3219 +#define EQAR_SUCCESS(eqar) ((eqar) & 0x100)
3220 +
3221 +/**
3222 + * qbman_swp_enqueue() - Issue an enqueue command
3223 + * @s: the software portal used for enqueue
3224 + * @d: the enqueue descriptor
3225 + * @fd: the frame descriptor to be enqueued
3226 + *
3227 + * Please note that 'fd' should only be NULL if the "action" of the
3228 + * descriptor is "orp_hole" or "orp_nesn".
3229 + *
3230 + * Return 0 for successful enqueue, -EBUSY if the EQCR is not ready.
3231 + */
3232 +int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,
3233 + const struct dpaa2_fd *fd)
3234 +{
3235 + struct qbman_eq_desc *p;
3236 + u32 eqar = qbman_read_register(s, QBMAN_CINH_SWP_EQAR);
3237 +
3238 + if (!EQAR_SUCCESS(eqar))
3239 + return -EBUSY;
3240 +
3241 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
3242 + memcpy(&p->dca, &d->dca, 31);
3243 + memcpy(&p->fd, fd, sizeof(*fd));
3244 +
3245 + /* Set the verb byte, have to substitute in the valid-bit */
3246 + dma_wmb();
3247 + p->verb = d->verb | EQAR_VB(eqar);
3248 + dccvac(p);
3249 +
3250 + return 0;
3251 +}
3252 +
3253 +/* Static (push) dequeue */
3254 +
3255 +/**
3256 + * qbman_swp_push_get() - Get the push dequeue setup
3257 + * @p: the software portal object
3258 + * @channel_idx: the channel index to query
3259 + * @enabled: returned boolean to show whether the push dequeue is enabled
3260 + * for the given channel
3261 + */
3262 +void qbman_swp_push_get(struct qbman_swp *s, u8 channel_idx, int *enabled)
3263 +{
3264 + u16 src = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
3265 +
3266 + WARN_ON(channel_idx > 15);
3267 + *enabled = src | (1 << channel_idx);
3268 +}
3269 +
3270 +/**
3271 + * qbman_swp_push_set() - Enable or disable push dequeue
3272 + * @p: the software portal object
3273 + * @channel_idx: the channel index (0 to 15)
3274 + * @enable: enable or disable push dequeue
3275 + */
3276 +void qbman_swp_push_set(struct qbman_swp *s, u8 channel_idx, int enable)
3277 +{
3278 + u16 dqsrc;
3279 +
3280 + WARN_ON(channel_idx > 15);
3281 + if (enable)
3282 + s->sdq |= 1 << channel_idx;
3283 + else
3284 + s->sdq &= ~(1 << channel_idx);
3285 +
3286 + /* Read make the complete src map. If no channels are enabled
3287 + * the SDQCR must be 0 or else QMan will assert errors
3288 + */
3289 + dqsrc = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
3290 + if (dqsrc != 0)
3291 + qbman_write_register(s, QBMAN_CINH_SWP_SDQCR, s->sdq);
3292 + else
3293 + qbman_write_register(s, QBMAN_CINH_SWP_SDQCR, 0);
3294 +}
3295 +
3296 +#define QB_VDQCR_VERB_DCT_SHIFT 0
3297 +#define QB_VDQCR_VERB_DT_SHIFT 2
3298 +#define QB_VDQCR_VERB_RLS_SHIFT 4
3299 +#define QB_VDQCR_VERB_WAE_SHIFT 5
3300 +
3301 +enum qb_pull_dt_e {
3302 + qb_pull_dt_channel,
3303 + qb_pull_dt_workqueue,
3304 + qb_pull_dt_framequeue
3305 +};
3306 +
3307 +/**
3308 + * qbman_pull_desc_clear() - Clear the contents of a descriptor to
3309 + * default/starting state
3310 + * @d: the pull dequeue descriptor to be cleared
3311 + */
3312 +void qbman_pull_desc_clear(struct qbman_pull_desc *d)
3313 +{
3314 + memset(d, 0, sizeof(*d));
3315 +}
3316 +
3317 +/**
3318 + * qbman_pull_desc_set_storage()- Set the pull dequeue storage
3319 + * @d: the pull dequeue descriptor to be set
3320 + * @storage: the pointer of the memory to store the dequeue result
3321 + * @storage_phys: the physical address of the storage memory
3322 + * @stash: to indicate whether write allocate is enabled
3323 + *
3324 + * If not called, or if called with 'storage' as NULL, the result pull dequeues
3325 + * will produce results to DQRR. If 'storage' is non-NULL, then results are
3326 + * produced to the given memory location (using the DMA address which
3327 + * the caller provides in 'storage_phys'), and 'stash' controls whether or not
3328 + * those writes to main-memory express a cache-warming attribute.
3329 + */
3330 +void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
3331 + struct dpaa2_dq *storage,
3332 + dma_addr_t storage_phys,
3333 + int stash)
3334 +{
3335 + /* save the virtual address */
3336 + d->rsp_addr_virt = (u64)storage;
3337 +
3338 + if (!storage) {
3339 + d->verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT);
3340 + return;
3341 + }
3342 + d->verb |= 1 << QB_VDQCR_VERB_RLS_SHIFT;
3343 + if (stash)
3344 + d->verb |= 1 << QB_VDQCR_VERB_WAE_SHIFT;
3345 + else
3346 + d->verb &= ~(1 << QB_VDQCR_VERB_WAE_SHIFT);
3347 +
3348 + d->rsp_addr = cpu_to_le64(storage_phys);
3349 +}
3350 +
3351 +/**
3352 + * qbman_pull_desc_set_numframes() - Set the number of frames to be dequeued
3353 + * @d: the pull dequeue descriptor to be set
3354 + * @numframes: number of frames to be set, must be between 1 and 16, inclusive
3355 + */
3356 +void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, u8 numframes)
3357 +{
3358 + d->numf = numframes - 1;
3359 +}
3360 +
3361 +void qbman_pull_desc_set_token(struct qbman_pull_desc *d, u8 token)
3362 +{
3363 + d->tok = token;
3364 +}
3365 +
3366 +/*
3367 + * Exactly one of the following descriptor "actions" should be set. (Calling any
3368 + * one of these will replace the effect of any prior call to one of these.)
3369 + * - pull dequeue from the given frame queue (FQ)
3370 + * - pull dequeue from any FQ in the given work queue (WQ)
3371 + * - pull dequeue from any FQ in any WQ in the given channel
3372 + */
3373 +
3374 +/**
3375 + * qbman_pull_desc_set_fq() - Set fqid from which the dequeue command dequeues
3376 + * @fqid: the frame queue index of the given FQ
3377 + */
3378 +void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, u32 fqid)
3379 +{
3380 + d->verb |= 1 << QB_VDQCR_VERB_DCT_SHIFT;
3381 + d->verb |= qb_pull_dt_framequeue << QB_VDQCR_VERB_DT_SHIFT;
3382 + d->dq_src = cpu_to_le32(fqid);
3383 +}
3384 +
3385 +/**
3386 + * qbman_pull_desc_set_wq() - Set wqid from which the dequeue command dequeues
3387 + * @wqid: composed of channel id and wqid within the channel
3388 + * @dct: the dequeue command type
3389 + */
3390 +void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, u32 wqid,
3391 + enum qbman_pull_type_e dct)
3392 +{
3393 + d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
3394 + d->verb |= qb_pull_dt_workqueue << QB_VDQCR_VERB_DT_SHIFT;
3395 + d->dq_src = cpu_to_le32(wqid);
3396 +}
3397 +
3398 +/**
3399 + * qbman_pull_desc_set_channel() - Set channelid from which the dequeue command
3400 + * dequeues
3401 + * @chid: the channel id to be dequeued
3402 + * @dct: the dequeue command type
3403 + */
3404 +void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, u32 chid,
3405 + enum qbman_pull_type_e dct)
3406 +{
3407 + d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
3408 + d->verb |= qb_pull_dt_channel << QB_VDQCR_VERB_DT_SHIFT;
3409 + d->dq_src = cpu_to_le32(chid);
3410 +}
3411 +
3412 +/**
3413 + * qbman_swp_pull() - Issue the pull dequeue command
3414 + * @s: the software portal object
3415 + * @d: the software portal descriptor which has been configured with
3416 + * the set of qbman_pull_desc_set_*() calls
3417 + *
3418 + * Return 0 for success, and -EBUSY if the software portal is not ready
3419 + * to do pull dequeue.
3420 + */
3421 +int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d)
3422 +{
3423 + struct qbman_pull_desc *p;
3424 +
3425 + if (!atomic_dec_and_test(&s->vdq.available)) {
3426 + atomic_inc(&s->vdq.available);
3427 + return -EBUSY;
3428 + }
3429 + s->vdq.storage = (void *)d->rsp_addr_virt;
3430 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_VDQCR);
3431 + p->numf = d->numf;
3432 + p->tok = QMAN_DQ_TOKEN_VALID;
3433 + p->dq_src = d->dq_src;
3434 + p->rsp_addr = d->rsp_addr;
3435 + p->rsp_addr_virt = d->rsp_addr_virt;
3436 + dma_wmb();
3437 +
3438 + /* Set the verb byte, have to substitute in the valid-bit */
3439 + p->verb = d->verb | s->vdq.valid_bit;
3440 + s->vdq.valid_bit ^= QB_VALID_BIT;
3441 + dccvac(p);
3442 +
3443 + return 0;
3444 +}
3445 +
3446 +#define QMAN_DQRR_PI_MASK 0xf
3447 +
3448 +/**
3449 + * qbman_swp_dqrr_next() - Get an valid DQRR entry
3450 + * @s: the software portal object
3451 + *
3452 + * Return NULL if there are no unconsumed DQRR entries. Return a DQRR entry
3453 + * only once, so repeated calls can return a sequence of DQRR entries, without
3454 + * requiring they be consumed immediately or in any particular order.
3455 + */
3456 +const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s)
3457 +{
3458 + u32 verb;
3459 + u32 response_verb;
3460 + u32 flags;
3461 + struct dpaa2_dq *p;
3462 +
3463 + /* Before using valid-bit to detect if something is there, we have to
3464 + * handle the case of the DQRR reset bug...
3465 + */
3466 + if (unlikely(s->dqrr.reset_bug)) {
3467 + /*
3468 + * We pick up new entries by cache-inhibited producer index,
3469 + * which means that a non-coherent mapping would require us to
3470 + * invalidate and read *only* once that PI has indicated that
3471 + * there's an entry here. The first trip around the DQRR ring
3472 + * will be much less efficient than all subsequent trips around
3473 + * it...
3474 + */
3475 + u8 pi = qbman_read_register(s, QBMAN_CINH_SWP_DQPI) &
3476 + QMAN_DQRR_PI_MASK;
3477 +
3478 + /* there are new entries if pi != next_idx */
3479 + if (pi == s->dqrr.next_idx)
3480 + return NULL;
3481 +
3482 + /*
3483 + * if next_idx is/was the last ring index, and 'pi' is
3484 + * different, we can disable the workaround as all the ring
3485 + * entries have now been DMA'd to so valid-bit checking is
3486 + * repaired. Note: this logic needs to be based on next_idx
3487 + * (which increments one at a time), rather than on pi (which
3488 + * can burst and wrap-around between our snapshots of it).
3489 + */
3490 + if (s->dqrr.next_idx == (s->dqrr.dqrr_size - 1)) {
3491 + pr_debug("next_idx=%d, pi=%d, clear reset bug\n",
3492 + s->dqrr.next_idx, pi);
3493 + s->dqrr.reset_bug = 0;
3494 + }
3495 + qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3496 + }
3497 +
3498 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3499 + verb = p->dq.verb;
3500 +
3501 + /*
3502 + * If the valid-bit isn't of the expected polarity, nothing there. Note,
3503 + * in the DQRR reset bug workaround, we shouldn't need to skip these
3504 + * check, because we've already determined that a new entry is available
3505 + * and we've invalidated the cacheline before reading it, so the
3506 + * valid-bit behaviour is repaired and should tell us what we already
3507 + * knew from reading PI.
3508 + */
3509 + if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) {
3510 + qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3511 + return NULL;
3512 + }
3513 + /*
3514 + * There's something there. Move "next_idx" attention to the next ring
3515 + * entry (and prefetch it) before returning what we found.
3516 + */
3517 + s->dqrr.next_idx++;
3518 + s->dqrr.next_idx &= s->dqrr.dqrr_size - 1; /* Wrap around */
3519 + if (!s->dqrr.next_idx)
3520 + s->dqrr.valid_bit ^= QB_VALID_BIT;
3521 +
3522 + /*
3523 + * If this is the final response to a volatile dequeue command
3524 + * indicate that the vdq is available
3525 + */
3526 + flags = p->dq.stat;
3527 + response_verb = verb & QBMAN_RESULT_MASK;
3528 + if ((response_verb == QBMAN_RESULT_DQ) &&
3529 + (flags & DPAA2_DQ_STAT_VOLATILE) &&
3530 + (flags & DPAA2_DQ_STAT_EXPIRED))
3531 + atomic_inc(&s->vdq.available);
3532 +
3533 + qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3534 +
3535 + return p;
3536 +}
3537 +
3538 +/**
3539 + * qbman_swp_dqrr_consume() - Consume DQRR entries previously returned from
3540 + * qbman_swp_dqrr_next().
3541 + * @s: the software portal object
3542 + * @dq: the DQRR entry to be consumed
3543 + */
3544 +void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct dpaa2_dq *dq)
3545 +{
3546 + qbman_write_register(s, QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq));
3547 +}
3548 +
3549 +/**
3550 + * qbman_result_has_new_result() - Check and get the dequeue response from the
3551 + * dq storage memory set in pull dequeue command
3552 + * @s: the software portal object
3553 + * @dq: the dequeue result read from the memory
3554 + *
3555 + * Return 1 for getting a valid dequeue result, or 0 for not getting a valid
3556 + * dequeue result.
3557 + *
3558 + * Only used for user-provided storage of dequeue results, not DQRR. For
3559 + * efficiency purposes, the driver will perform any required endianness
3560 + * conversion to ensure that the user's dequeue result storage is in host-endian
3561 + * format. As such, once the user has called qbman_result_has_new_result() and
3562 + * been returned a valid dequeue result, they should not call it again on
3563 + * the same memory location (except of course if another dequeue command has
3564 + * been executed to produce a new result to that location).
3565 + */
3566 +int qbman_result_has_new_result(struct qbman_swp *s, const struct dpaa2_dq *dq)
3567 +{
3568 + if (dq->dq.tok != QMAN_DQ_TOKEN_VALID)
3569 + return 0;
3570 +
3571 + /*
3572 + * Set token to be 0 so we will detect change back to 1
3573 + * next time the looping is traversed. Const is cast away here
3574 + * as we want users to treat the dequeue responses as read only.
3575 + */
3576 + ((struct dpaa2_dq *)dq)->dq.tok = 0;
3577 +
3578 + /*
3579 + * Determine whether VDQCR is available based on whether the
3580 + * current result is sitting in the first storage location of
3581 + * the busy command.
3582 + */
3583 + if (s->vdq.storage == dq) {
3584 + s->vdq.storage = NULL;
3585 + atomic_inc(&s->vdq.available);
3586 + }
3587 +
3588 + return 1;
3589 +}
3590 +
3591 +/**
3592 + * qbman_release_desc_clear() - Clear the contents of a descriptor to
3593 + * default/starting state.
3594 + */
3595 +void qbman_release_desc_clear(struct qbman_release_desc *d)
3596 +{
3597 + memset(d, 0, sizeof(*d));
3598 + d->verb = 1 << 5; /* Release Command Valid */
3599 +}
3600 +
3601 +/**
3602 + * qbman_release_desc_set_bpid() - Set the ID of the buffer pool to release to
3603 + */
3604 +void qbman_release_desc_set_bpid(struct qbman_release_desc *d, u16 bpid)
3605 +{
3606 + d->bpid = cpu_to_le16(bpid);
3607 +}
3608 +
3609 +/**
3610 + * qbman_release_desc_set_rcdi() - Determines whether or not the portal's RCDI
3611 + * interrupt source should be asserted after the release command is completed.
3612 + */
3613 +void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable)
3614 +{
3615 + if (enable)
3616 + d->verb |= 1 << 6;
3617 + else
3618 + d->verb &= ~(1 << 6);
3619 +}
3620 +
3621 +#define RAR_IDX(rar) ((rar) & 0x7)
3622 +#define RAR_VB(rar) ((rar) & 0x80)
3623 +#define RAR_SUCCESS(rar) ((rar) & 0x100)
3624 +
3625 +/**
3626 + * qbman_swp_release() - Issue a buffer release command
3627 + * @s: the software portal object
3628 + * @d: the release descriptor
3629 + * @buffers: a pointer pointing to the buffer address to be released
3630 + * @num_buffers: number of buffers to be released, must be less than 8
3631 + *
3632 + * Return 0 for success, -EBUSY if the release command ring is not ready.
3633 + */
3634 +int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
3635 + const u64 *buffers, unsigned int num_buffers)
3636 +{
3637 + int i;
3638 + struct qbman_release_desc *p;
3639 + u32 rar;
3640 +
3641 + if (!num_buffers || (num_buffers > 7))
3642 + return -EINVAL;
3643 +
3644 + rar = qbman_read_register(s, QBMAN_CINH_SWP_RAR);
3645 + if (!RAR_SUCCESS(rar))
3646 + return -EBUSY;
3647 +
3648 + /* Start the release command */
3649 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_RCR(RAR_IDX(rar)));
3650 + /* Copy the caller's buffer pointers to the command */
3651 + for (i = 0; i < num_buffers; i++)
3652 + p->buf[i] = cpu_to_le64(buffers[i]);
3653 + p->bpid = d->bpid;
3654 +
3655 + /*
3656 + * Set the verb byte, have to substitute in the valid-bit and the number
3657 + * of buffers.
3658 + */
3659 + dma_wmb();
3660 + p->verb = d->verb | RAR_VB(rar) | num_buffers;
3661 + dccvac(p);
3662 +
3663 + return 0;
3664 +}
3665 +
3666 +struct qbman_acquire_desc {
3667 + u8 verb;
3668 + u8 reserved;
3669 + u16 bpid;
3670 + u8 num;
3671 + u8 reserved2[59];
3672 +};
3673 +
3674 +struct qbman_acquire_rslt {
3675 + u8 verb;
3676 + u8 rslt;
3677 + u16 reserved;
3678 + u8 num;
3679 + u8 reserved2[3];
3680 + u64 buf[7];
3681 +};
3682 +
3683 +/**
3684 + * qbman_swp_acquire() - Issue a buffer acquire command
3685 + * @s: the software portal object
3686 + * @bpid: the buffer pool index
3687 + * @buffers: a pointer pointing to the acquired buffer addresses
3688 + * @num_buffers: number of buffers to be acquired, must be less than 8
3689 + *
3690 + * Return 0 for success, or negative error code if the acquire command
3691 + * fails.
3692 + */
3693 +int qbman_swp_acquire(struct qbman_swp *s, u16 bpid, u64 *buffers,
3694 + unsigned int num_buffers)
3695 +{
3696 + struct qbman_acquire_desc *p;
3697 + struct qbman_acquire_rslt *r;
3698 + int i;
3699 +
3700 + if (!num_buffers || (num_buffers > 7))
3701 + return -EINVAL;
3702 +
3703 + /* Start the management command */
3704 + p = qbman_swp_mc_start(s);
3705 +
3706 + if (!p)
3707 + return -EBUSY;
3708 +
3709 + /* Encode the caller-provided attributes */
3710 + p->bpid = cpu_to_le16(bpid);
3711 + p->num = num_buffers;
3712 +
3713 + /* Complete the management command */
3714 + r = qbman_swp_mc_complete(s, p, QBMAN_MC_ACQUIRE);
3715 + if (unlikely(!r)) {
3716 + pr_err("qbman: acquire from BPID %d failed, no response\n",
3717 + bpid);
3718 + return -EIO;
3719 + }
3720 +
3721 + /* Decode the outcome */
3722 + WARN_ON((r->verb & 0x7f) != QBMAN_MC_ACQUIRE);
3723 +
3724 + /* Determine success or failure */
3725 + if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
3726 + pr_err("qbman: acquire from BPID 0x%x failed, code=0x%02x\n",
3727 + bpid, r->rslt);
3728 + return -EIO;
3729 + }
3730 +
3731 + WARN_ON(r->num > num_buffers);
3732 +
3733 + /* Copy the acquired buffers to the caller's array */
3734 + for (i = 0; i < r->num; i++)
3735 + buffers[i] = le64_to_cpu(r->buf[i]);
3736 +
3737 + return (int)r->num;
3738 +}
3739 +
3740 +struct qbman_alt_fq_state_desc {
3741 + u8 verb;
3742 + u8 reserved[3];
3743 + u32 fqid;
3744 + u8 reserved2[56];
3745 +};
3746 +
3747 +struct qbman_alt_fq_state_rslt {
3748 + u8 verb;
3749 + u8 rslt;
3750 + u8 reserved[62];
3751 +};
3752 +
3753 +#define ALT_FQ_FQID_MASK 0x00FFFFFF
3754 +
3755 +int qbman_swp_alt_fq_state(struct qbman_swp *s, u32 fqid,
3756 + u8 alt_fq_verb)
3757 +{
3758 + struct qbman_alt_fq_state_desc *p;
3759 + struct qbman_alt_fq_state_rslt *r;
3760 +
3761 + /* Start the management command */
3762 + p = qbman_swp_mc_start(s);
3763 + if (!p)
3764 + return -EBUSY;
3765 +
3766 + p->fqid = cpu_to_le32(fqid) & ALT_FQ_FQID_MASK;
3767 +
3768 + /* Complete the management command */
3769 + r = qbman_swp_mc_complete(s, p, alt_fq_verb);
3770 + if (unlikely(!r)) {
3771 + pr_err("qbman: mgmt cmd failed, no response (verb=0x%x)\n",
3772 + alt_fq_verb);
3773 + return -EIO;
3774 + }
3775 +
3776 + /* Decode the outcome */
3777 + WARN_ON((r->verb & QBMAN_RESULT_MASK) != alt_fq_verb);
3778 +
3779 + /* Determine success or failure */
3780 + if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
3781 + pr_err("qbman: ALT FQID %d failed: verb = 0x%08x code = 0x%02x\n",
3782 + fqid, r->verb, r->rslt);
3783 + return -EIO;
3784 + }
3785 +
3786 + return 0;
3787 +}
3788 +
3789 +struct qbman_cdan_ctrl_desc {
3790 + u8 verb;
3791 + u8 reserved;
3792 + u16 ch;
3793 + u8 we;
3794 + u8 ctrl;
3795 + u16 reserved2;
3796 + u64 cdan_ctx;
3797 + u8 reserved3[48];
3798 +
3799 +};
3800 +
3801 +struct qbman_cdan_ctrl_rslt {
3802 + u8 verb;
3803 + u8 rslt;
3804 + u16 ch;
3805 + u8 reserved[60];
3806 +};
3807 +
3808 +int qbman_swp_CDAN_set(struct qbman_swp *s, u16 channelid,
3809 + u8 we_mask, u8 cdan_en,
3810 + u64 ctx)
3811 +{
3812 + struct qbman_cdan_ctrl_desc *p = NULL;
3813 + struct qbman_cdan_ctrl_rslt *r = NULL;
3814 +
3815 + /* Start the management command */
3816 + p = qbman_swp_mc_start(s);
3817 + if (!p)
3818 + return -EBUSY;
3819 +
3820 + /* Encode the caller-provided attributes */
3821 + p->ch = cpu_to_le16(channelid);
3822 + p->we = we_mask;
3823 + if (cdan_en)
3824 + p->ctrl = 1;
3825 + else
3826 + p->ctrl = 0;
3827 + p->cdan_ctx = cpu_to_le64(ctx);
3828 +
3829 + /* Complete the management command */
3830 + r = qbman_swp_mc_complete(s, p, QBMAN_WQCHAN_CONFIGURE);
3831 + if (unlikely(!r)) {
3832 + pr_err("qbman: wqchan config failed, no response\n");
3833 + return -EIO;
3834 + }
3835 +
3836 + WARN_ON((r->verb & 0x7f) != QBMAN_WQCHAN_CONFIGURE);
3837 +
3838 + /* Determine success or failure */
3839 + if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
3840 + pr_err("qbman: CDAN cQID %d failed: code = 0x%02x\n",
3841 + channelid, r->rslt);
3842 + return -EIO;
3843 + }
3844 +
3845 + return 0;
3846 +}
3847 diff --git a/drivers/staging/fsl-mc/bus/dpio/qbman-portal.h b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.h
3848 new file mode 100644
3849 index 00000000..4254034c
3850 --- /dev/null
3851 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.h
3852 @@ -0,0 +1,662 @@
3853 +/*
3854 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3855 + * Copyright 2016 NXP
3856 + *
3857 + * Redistribution and use in source and binary forms, with or without
3858 + * modification, are permitted provided that the following conditions are met:
3859 + * * Redistributions of source code must retain the above copyright
3860 + * notice, this list of conditions and the following disclaimer.
3861 + * * Redistributions in binary form must reproduce the above copyright
3862 + * notice, this list of conditions and the following disclaimer in the
3863 + * documentation and/or other materials provided with the distribution.
3864 + * * Neither the name of Freescale Semiconductor nor the
3865 + * names of its contributors may be used to endorse or promote products
3866 + * derived from this software without specific prior written permission.
3867 + *
3868 + * ALTERNATIVELY, this software may be distributed under the terms of the
3869 + * GNU General Public License ("GPL") as published by the Free Software
3870 + * Foundation, either version 2 of that License or (at your option) any
3871 + * later version.
3872 + *
3873 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
3874 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
3875 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
3876 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
3877 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
3878 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
3879 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
3880 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3881 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
3882 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3883 + */
3884 +#ifndef __FSL_QBMAN_PORTAL_H
3885 +#define __FSL_QBMAN_PORTAL_H
3886 +
3887 +#include "qbman_private.h"
3888 +#include "../../include/dpaa2-fd.h"
3889 +
3890 +struct dpaa2_dq;
3891 +struct qbman_swp;
3892 +
3893 +/* qbman software portal descriptor structure */
3894 +struct qbman_swp_desc {
3895 + void *cena_bar; /* Cache-enabled portal base address */
3896 + void *cinh_bar; /* Cache-inhibited portal base address */
3897 + u32 qman_version;
3898 +};
3899 +
3900 +#define QBMAN_SWP_INTERRUPT_EQRI 0x01
3901 +#define QBMAN_SWP_INTERRUPT_EQDI 0x02
3902 +#define QBMAN_SWP_INTERRUPT_DQRI 0x04
3903 +#define QBMAN_SWP_INTERRUPT_RCRI 0x08
3904 +#define QBMAN_SWP_INTERRUPT_RCDI 0x10
3905 +#define QBMAN_SWP_INTERRUPT_VDCI 0x20
3906 +
3907 +/* the structure for pull dequeue descriptor */
3908 +struct qbman_pull_desc {
3909 + u8 verb;
3910 + u8 numf;
3911 + u8 tok;
3912 + u8 reserved;
3913 + u32 dq_src;
3914 + u64 rsp_addr;
3915 + u64 rsp_addr_virt;
3916 + u8 padding[40];
3917 +};
3918 +
3919 +enum qbman_pull_type_e {
3920 + /* dequeue with priority precedence, respect intra-class scheduling */
3921 + qbman_pull_type_prio = 1,
3922 + /* dequeue with active FQ precedence, respect ICS */
3923 + qbman_pull_type_active,
3924 + /* dequeue with active FQ precedence, no ICS */
3925 + qbman_pull_type_active_noics
3926 +};
3927 +
3928 +/* Definitions for parsing dequeue entries */
3929 +#define QBMAN_RESULT_MASK 0x7f
3930 +#define QBMAN_RESULT_DQ 0x60
3931 +#define QBMAN_RESULT_FQRN 0x21
3932 +#define QBMAN_RESULT_FQRNI 0x22
3933 +#define QBMAN_RESULT_FQPN 0x24
3934 +#define QBMAN_RESULT_FQDAN 0x25
3935 +#define QBMAN_RESULT_CDAN 0x26
3936 +#define QBMAN_RESULT_CSCN_MEM 0x27
3937 +#define QBMAN_RESULT_CGCU 0x28
3938 +#define QBMAN_RESULT_BPSCN 0x29
3939 +#define QBMAN_RESULT_CSCN_WQ 0x2a
3940 +
3941 +/* QBMan FQ management command codes */
3942 +#define QBMAN_FQ_SCHEDULE 0x48
3943 +#define QBMAN_FQ_FORCE 0x49
3944 +#define QBMAN_FQ_XON 0x4d
3945 +#define QBMAN_FQ_XOFF 0x4e
3946 +
3947 +/* structure of enqueue descriptor */
3948 +struct qbman_eq_desc {
3949 + u8 verb;
3950 + u8 dca;
3951 + u16 seqnum;
3952 + u16 orpid;
3953 + u16 reserved1;
3954 + u32 tgtid;
3955 + u32 tag;
3956 + u16 qdbin;
3957 + u8 qpri;
3958 + u8 reserved[3];
3959 + u8 wae;
3960 + u8 rspid;
3961 + u64 rsp_addr;
3962 + u8 fd[32];
3963 +};
3964 +
3965 +/* buffer release descriptor */
3966 +struct qbman_release_desc {
3967 + u8 verb;
3968 + u8 reserved;
3969 + u16 bpid;
3970 + u32 reserved2;
3971 + u64 buf[7];
3972 +};
3973 +
3974 +/* Management command result codes */
3975 +#define QBMAN_MC_RSLT_OK 0xf0
3976 +
3977 +#define CODE_CDAN_WE_EN 0x1
3978 +#define CODE_CDAN_WE_CTX 0x4
3979 +
3980 +/* portal data structure */
3981 +struct qbman_swp {
3982 + const struct qbman_swp_desc *desc;
3983 + void __iomem *addr_cena;
3984 + void __iomem *addr_cinh;
3985 +
3986 + /* Management commands */
3987 + struct {
3988 + u32 valid_bit; /* 0x00 or 0x80 */
3989 + } mc;
3990 +
3991 + /* Push dequeues */
3992 + u32 sdq;
3993 +
3994 + /* Volatile dequeues */
3995 + struct {
3996 + atomic_t available; /* indicates if a command can be sent */
3997 + u32 valid_bit; /* 0x00 or 0x80 */
3998 + struct dpaa2_dq *storage; /* NULL if DQRR */
3999 + } vdq;
4000 +
4001 + /* DQRR */
4002 + struct {
4003 + u32 next_idx;
4004 + u32 valid_bit;
4005 + u8 dqrr_size;
4006 + int reset_bug; /* indicates dqrr reset workaround is needed */
4007 + } dqrr;
4008 +};
4009 +
4010 +struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d);
4011 +void qbman_swp_finish(struct qbman_swp *p);
4012 +u32 qbman_swp_interrupt_read_status(struct qbman_swp *p);
4013 +void qbman_swp_interrupt_clear_status(struct qbman_swp *p, u32 mask);
4014 +u32 qbman_swp_interrupt_get_trigger(struct qbman_swp *p);
4015 +void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, u32 mask);
4016 +int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p);
4017 +void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit);
4018 +
4019 +void qbman_swp_push_get(struct qbman_swp *p, u8 channel_idx, int *enabled);
4020 +void qbman_swp_push_set(struct qbman_swp *p, u8 channel_idx, int enable);
4021 +
4022 +void qbman_pull_desc_clear(struct qbman_pull_desc *d);
4023 +void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
4024 + struct dpaa2_dq *storage,
4025 + dma_addr_t storage_phys,
4026 + int stash);
4027 +void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, u8 numframes);
4028 +void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, u32 fqid);
4029 +void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, u32 wqid,
4030 + enum qbman_pull_type_e dct);
4031 +void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, u32 chid,
4032 + enum qbman_pull_type_e dct);
4033 +
4034 +int qbman_swp_pull(struct qbman_swp *p, struct qbman_pull_desc *d);
4035 +
4036 +const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s);
4037 +void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct dpaa2_dq *dq);
4038 +
4039 +int qbman_result_has_new_result(struct qbman_swp *p, const struct dpaa2_dq *dq);
4040 +
4041 +void qbman_eq_desc_clear(struct qbman_eq_desc *d);
4042 +void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success);
4043 +void qbman_eq_desc_set_token(struct qbman_eq_desc *d, u8 token);
4044 +void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, u32 fqid);
4045 +void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
4046 + u32 qd_bin, u32 qd_prio);
4047 +
4048 +int qbman_swp_enqueue(struct qbman_swp *p, const struct qbman_eq_desc *d,
4049 + const struct dpaa2_fd *fd);
4050 +
4051 +void qbman_release_desc_clear(struct qbman_release_desc *d);
4052 +void qbman_release_desc_set_bpid(struct qbman_release_desc *d, u16 bpid);
4053 +void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable);
4054 +
4055 +int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
4056 + const u64 *buffers, unsigned int num_buffers);
4057 +int qbman_swp_acquire(struct qbman_swp *s, u16 bpid, u64 *buffers,
4058 + unsigned int num_buffers);
4059 +int qbman_swp_alt_fq_state(struct qbman_swp *s, u32 fqid,
4060 + u8 alt_fq_verb);
4061 +int qbman_swp_CDAN_set(struct qbman_swp *s, u16 channelid,
4062 + u8 we_mask, u8 cdan_en,
4063 + u64 ctx);
4064 +
4065 +void *qbman_swp_mc_start(struct qbman_swp *p);
4066 +void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, u8 cmd_verb);
4067 +void *qbman_swp_mc_result(struct qbman_swp *p);
4068 +
4069 +/**
4070 + * qbman_result_is_DQ() - check if the dequeue result is a dequeue response
4071 + * @dq: the dequeue result to be checked
4072 + *
4073 + * DQRR entries may contain non-dequeue results, ie. notifications
4074 + */
4075 +static inline int qbman_result_is_DQ(const struct dpaa2_dq *dq)
4076 +{
4077 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_DQ);
4078 +}
4079 +
4080 +/**
4081 + * qbman_result_is_SCN() - Check the dequeue result is notification or not
4082 + * @dq: the dequeue result to be checked
4083 + *
4084 + */
4085 +static inline int qbman_result_is_SCN(const struct dpaa2_dq *dq)
4086 +{
4087 + return !qbman_result_is_DQ(dq);
4088 +}
4089 +
4090 +/* FQ Data Availability */
4091 +static inline int qbman_result_is_FQDAN(const struct dpaa2_dq *dq)
4092 +{
4093 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQDAN);
4094 +}
4095 +
4096 +/* Channel Data Availability */
4097 +static inline int qbman_result_is_CDAN(const struct dpaa2_dq *dq)
4098 +{
4099 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CDAN);
4100 +}
4101 +
4102 +/* Congestion State Change */
4103 +static inline int qbman_result_is_CSCN(const struct dpaa2_dq *dq)
4104 +{
4105 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CSCN_WQ);
4106 +}
4107 +
4108 +/* Buffer Pool State Change */
4109 +static inline int qbman_result_is_BPSCN(const struct dpaa2_dq *dq)
4110 +{
4111 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_BPSCN);
4112 +}
4113 +
4114 +/* Congestion Group Count Update */
4115 +static inline int qbman_result_is_CGCU(const struct dpaa2_dq *dq)
4116 +{
4117 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CGCU);
4118 +}
4119 +
4120 +/* Retirement */
4121 +static inline int qbman_result_is_FQRN(const struct dpaa2_dq *dq)
4122 +{
4123 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQRN);
4124 +}
4125 +
4126 +/* Retirement Immediate */
4127 +static inline int qbman_result_is_FQRNI(const struct dpaa2_dq *dq)
4128 +{
4129 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQRNI);
4130 +}
4131 +
4132 + /* Park */
4133 +static inline int qbman_result_is_FQPN(const struct dpaa2_dq *dq)
4134 +{
4135 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQPN);
4136 +}
4137 +
4138 +/**
4139 + * qbman_result_SCN_state() - Get the state field in State-change notification
4140 + */
4141 +static inline u8 qbman_result_SCN_state(const struct dpaa2_dq *scn)
4142 +{
4143 + return scn->scn.state;
4144 +}
4145 +
4146 +#define SCN_RID_MASK 0x00FFFFFF
4147 +
4148 +/**
4149 + * qbman_result_SCN_rid() - Get the resource id in State-change notification
4150 + */
4151 +static inline u32 qbman_result_SCN_rid(const struct dpaa2_dq *scn)
4152 +{
4153 + return le32_to_cpu(scn->scn.rid_tok) & SCN_RID_MASK;
4154 +}
4155 +
4156 +/**
4157 + * qbman_result_SCN_ctx() - Get the context data in State-change notification
4158 + */
4159 +static inline u64 qbman_result_SCN_ctx(const struct dpaa2_dq *scn)
4160 +{
4161 + return le64_to_cpu(scn->scn.ctx);
4162 +}
4163 +
4164 +/**
4165 + * qbman_swp_fq_schedule() - Move the fq to the scheduled state
4166 + * @s: the software portal object
4167 + * @fqid: the index of frame queue to be scheduled
4168 + *
4169 + * There are a couple of different ways that a FQ can end up parked state,
4170 + * This schedules it.
4171 + *
4172 + * Return 0 for success, or negative error code for failure.
4173 + */
4174 +static inline int qbman_swp_fq_schedule(struct qbman_swp *s, u32 fqid)
4175 +{
4176 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_SCHEDULE);
4177 +}
4178 +
4179 +/**
4180 + * qbman_swp_fq_force() - Force the FQ to fully scheduled state
4181 + * @s: the software portal object
4182 + * @fqid: the index of frame queue to be forced
4183 + *
4184 + * Force eligible will force a tentatively-scheduled FQ to be fully-scheduled
4185 + * and thus be available for selection by any channel-dequeuing behaviour (push
4186 + * or pull). If the FQ is subsequently "dequeued" from the channel and is still
4187 + * empty at the time this happens, the resulting dq_entry will have no FD.
4188 + * (qbman_result_DQ_fd() will return NULL.)
4189 + *
4190 + * Return 0 for success, or negative error code for failure.
4191 + */
4192 +static inline int qbman_swp_fq_force(struct qbman_swp *s, u32 fqid)
4193 +{
4194 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_FORCE);
4195 +}
4196 +
4197 +/**
4198 + * qbman_swp_fq_xon() - sets FQ flow-control to XON
4199 + * @s: the software portal object
4200 + * @fqid: the index of frame queue
4201 + *
4202 + * This setting doesn't affect enqueues to the FQ, just dequeues.
4203 + *
4204 + * Return 0 for success, or negative error code for failure.
4205 + */
4206 +static inline int qbman_swp_fq_xon(struct qbman_swp *s, u32 fqid)
4207 +{
4208 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XON);
4209 +}
4210 +
4211 +/**
4212 + * qbman_swp_fq_xoff() - sets FQ flow-control to XOFF
4213 + * @s: the software portal object
4214 + * @fqid: the index of frame queue
4215 + *
4216 + * This setting doesn't affect enqueues to the FQ, just dequeues.
4217 + * XOFF FQs will remain in the tenatively-scheduled state, even when
4218 + * non-empty, meaning they won't be selected for scheduled dequeuing.
4219 + * If a FQ is changed to XOFF after it had already become truly-scheduled
4220 + * to a channel, and a pull dequeue of that channel occurs that selects
4221 + * that FQ for dequeuing, then the resulting dq_entry will have no FD.
4222 + * (qbman_result_DQ_fd() will return NULL.)
4223 + *
4224 + * Return 0 for success, or negative error code for failure.
4225 + */
4226 +static inline int qbman_swp_fq_xoff(struct qbman_swp *s, u32 fqid)
4227 +{
4228 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XOFF);
4229 +}
4230 +
4231 +/* If the user has been allocated a channel object that is going to generate
4232 + * CDANs to another channel, then the qbman_swp_CDAN* functions will be
4233 + * necessary.
4234 + *
4235 + * CDAN-enabled channels only generate a single CDAN notification, after which
4236 + * they need to be reenabled before they'll generate another. The idea is
4237 + * that pull dequeuing will occur in reaction to the CDAN, followed by a
4238 + * reenable step. Each function generates a distinct command to hardware, so a
4239 + * combination function is provided if the user wishes to modify the "context"
4240 + * (which shows up in each CDAN message) each time they reenable, as a single
4241 + * command to hardware.
4242 + */
4243 +
4244 +/**
4245 + * qbman_swp_CDAN_set_context() - Set CDAN context
4246 + * @s: the software portal object
4247 + * @channelid: the channel index
4248 + * @ctx: the context to be set in CDAN
4249 + *
4250 + * Return 0 for success, or negative error code for failure.
4251 + */
4252 +static inline int qbman_swp_CDAN_set_context(struct qbman_swp *s, u16 channelid,
4253 + u64 ctx)
4254 +{
4255 + return qbman_swp_CDAN_set(s, channelid,
4256 + CODE_CDAN_WE_CTX,
4257 + 0, ctx);
4258 +}
4259 +
4260 +/**
4261 + * qbman_swp_CDAN_enable() - Enable CDAN for the channel
4262 + * @s: the software portal object
4263 + * @channelid: the index of the channel to generate CDAN
4264 + *
4265 + * Return 0 for success, or negative error code for failure.
4266 + */
4267 +static inline int qbman_swp_CDAN_enable(struct qbman_swp *s, u16 channelid)
4268 +{
4269 + return qbman_swp_CDAN_set(s, channelid,
4270 + CODE_CDAN_WE_EN,
4271 + 1, 0);
4272 +}
4273 +
4274 +/**
4275 + * qbman_swp_CDAN_disable() - disable CDAN for the channel
4276 + * @s: the software portal object
4277 + * @channelid: the index of the channel to generate CDAN
4278 + *
4279 + * Return 0 for success, or negative error code for failure.
4280 + */
4281 +static inline int qbman_swp_CDAN_disable(struct qbman_swp *s, u16 channelid)
4282 +{
4283 + return qbman_swp_CDAN_set(s, channelid,
4284 + CODE_CDAN_WE_EN,
4285 + 0, 0);
4286 +}
4287 +
4288 +/**
4289 + * qbman_swp_CDAN_set_context_enable() - Set CDAN contest and enable CDAN
4290 + * @s: the software portal object
4291 + * @channelid: the index of the channel to generate CDAN
4292 + * @ctx:i the context set in CDAN
4293 + *
4294 + * Return 0 for success, or negative error code for failure.
4295 + */
4296 +static inline int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s,
4297 + u16 channelid,
4298 + u64 ctx)
4299 +{
4300 + return qbman_swp_CDAN_set(s, channelid,
4301 + CODE_CDAN_WE_EN | CODE_CDAN_WE_CTX,
4302 + 1, ctx);
4303 +}
4304 +
4305 +/* Wraps up submit + poll-for-result */
4306 +static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd,
4307 + u8 cmd_verb)
4308 +{
4309 + int loopvar = 1000;
4310 +
4311 + qbman_swp_mc_submit(swp, cmd, cmd_verb);
4312 +
4313 + do {
4314 + cmd = qbman_swp_mc_result(swp);
4315 + } while (!cmd && loopvar--);
4316 +
4317 + WARN_ON(!loopvar);
4318 +
4319 + return cmd;
4320 +}
4321 +
4322 +/* ------------ */
4323 +/* qb_attr_code */
4324 +/* ------------ */
4325 +
4326 +/* This struct locates a sub-field within a QBMan portal (CENA) cacheline which
4327 + * is either serving as a configuration command or a query result. The
4328 + * representation is inherently little-endian, as the indexing of the words is
4329 + * itself little-endian in nature and layerscape is little endian for anything
4330 + * that crosses a word boundary too (64-bit fields are the obvious examples).
4331 + */
4332 +struct qb_attr_code {
4333 + unsigned int word; /* which u32[] array member encodes the field */
4334 + unsigned int lsoffset; /* encoding offset from ls-bit */
4335 + unsigned int width; /* encoding width. (bool must be 1.) */
4336 +};
4337 +
4338 +/* Some pre-defined codes */
4339 +extern struct qb_attr_code code_generic_verb;
4340 +extern struct qb_attr_code code_generic_rslt;
4341 +
4342 +/* Macros to define codes */
4343 +#define QB_CODE(a, b, c) { a, b, c}
4344 +#define QB_CODE_NULL \
4345 + QB_CODE((unsigned int)-1, (unsigned int)-1, (unsigned int)-1)
4346 +
4347 +/* Rotate a code "ms", meaning that it moves from less-significant bytes to
4348 + * more-significant, from less-significant words to more-significant, etc. The
4349 + * "ls" version does the inverse, from more-significant towards
4350 + * less-significant.
4351 + */
4352 +static inline void qb_attr_code_rotate_ms(struct qb_attr_code *code,
4353 + unsigned int bits)
4354 +{
4355 + code->lsoffset += bits;
4356 + while (code->lsoffset > 31) {
4357 + code->word++;
4358 + code->lsoffset -= 32;
4359 + }
4360 +}
4361 +
4362 +static inline void qb_attr_code_rotate_ls(struct qb_attr_code *code,
4363 + unsigned int bits)
4364 +{
4365 + /* Don't be fooled, this trick should work because the types are
4366 + * unsigned. So the case that interests the while loop (the rotate has
4367 + * gone too far and the word count needs to compensate for it), is
4368 + * manifested when lsoffset is negative. But that equates to a really
4369 + * large unsigned value, starting with lots of "F"s. As such, we can
4370 + * continue adding 32 back to it until it wraps back round above zero,
4371 + * to a value of 31 or less...
4372 + */
4373 + code->lsoffset -= bits;
4374 + while (code->lsoffset > 31) {
4375 + code->word--;
4376 + code->lsoffset += 32;
4377 + }
4378 +}
4379 +
4380 +/* Implement a loop of code rotations until 'expr' evaluates to FALSE (0). */
4381 +#define qb_attr_code_for_ms(code, bits, expr) \
4382 + for (; expr; qb_attr_code_rotate_ms(code, bits))
4383 +#define qb_attr_code_for_ls(code, bits, expr) \
4384 + for (; expr; qb_attr_code_rotate_ls(code, bits))
4385 +
4386 +static inline void word_copy(void *d, const void *s, unsigned int cnt)
4387 +{
4388 + u32 *dd = d;
4389 + const u32 *ss = s;
4390 +
4391 + while (cnt--)
4392 + *(dd++) = *(ss++);
4393 +}
4394 +
4395 +/*
4396 + * Currently, the CENA support code expects each 32-bit word to be written in
4397 + * host order, and these are converted to hardware (little-endian) order on
4398 + * command submission. However, 64-bit quantities are must be written (and read)
4399 + * as two 32-bit words with the least-significant word first, irrespective of
4400 + * host endianness.
4401 + */
4402 +static inline void u64_to_le32_copy(void *d, const u64 *s,
4403 + unsigned int cnt)
4404 +{
4405 + u32 *dd = d;
4406 + const u32 *ss = (const u32 *)s;
4407 +
4408 + while (cnt--) {
4409 + /*
4410 + * TBD: the toolchain was choking on the use of 64-bit types up
4411 + * until recently so this works entirely with 32-bit variables.
4412 + * When 64-bit types become usable again, investigate better
4413 + * ways of doing this.
4414 + */
4415 +#if defined(__BIG_ENDIAN)
4416 + *(dd++) = ss[1];
4417 + *(dd++) = ss[0];
4418 + ss += 2;
4419 +#else
4420 + *(dd++) = *(ss++);
4421 + *(dd++) = *(ss++);
4422 +#endif
4423 + }
4424 +}
4425 +
4426 +static inline void u64_from_le32_copy(u64 *d, const void *s,
4427 + unsigned int cnt)
4428 +{
4429 + const u32 *ss = s;
4430 + u32 *dd = (u32 *)d;
4431 +
4432 + while (cnt--) {
4433 +#if defined(__BIG_ENDIAN)
4434 + dd[1] = *(ss++);
4435 + dd[0] = *(ss++);
4436 + dd += 2;
4437 +#else
4438 + *(dd++) = *(ss++);
4439 + *(dd++) = *(ss++);
4440 +#endif
4441 + }
4442 +}
4443 +
4444 +/* decode a field from a cacheline */
4445 +static inline u32 qb_attr_code_decode(const struct qb_attr_code *code,
4446 + const u32 *cacheline)
4447 +{
4448 + return d32_u32(code->lsoffset, code->width, cacheline[code->word]);
4449 +}
4450 +
4451 +static inline u64 qb_attr_code_decode_64(const struct qb_attr_code *code,
4452 + const u64 *cacheline)
4453 +{
4454 + u64 res;
4455 +
4456 + u64_from_le32_copy(&res, &cacheline[code->word / 2], 1);
4457 + return res;
4458 +}
4459 +
4460 +/* encode a field to a cacheline */
4461 +static inline void qb_attr_code_encode(const struct qb_attr_code *code,
4462 + u32 *cacheline, u32 val)
4463 +{
4464 + cacheline[code->word] =
4465 + r32_u32(code->lsoffset, code->width, cacheline[code->word])
4466 + | e32_u32(code->lsoffset, code->width, val);
4467 +}
4468 +
4469 +static inline void qb_attr_code_encode_64(const struct qb_attr_code *code,
4470 + u64 *cacheline, u64 val)
4471 +{
4472 + u64_to_le32_copy(&cacheline[code->word / 2], &val, 1);
4473 +}
4474 +
4475 +/* Small-width signed values (two's-complement) will decode into medium-width
4476 + * positives. (Eg. for an 8-bit signed field, which stores values from -128 to
4477 + * +127, a setting of -7 would appear to decode to the 32-bit unsigned value
4478 + * 249. Likewise -120 would decode as 136.) This function allows the caller to
4479 + * "re-sign" such fields to 32-bit signed. (Eg. -7, which was 249 with an 8-bit
4480 + * encoding, will become 0xfffffff9 if you cast the return value to u32).
4481 + */
4482 +static inline int32_t qb_attr_code_makesigned(const struct qb_attr_code *code,
4483 + u32 val)
4484 +{
4485 + WARN_ON(val >= (1 << code->width));
4486 + /* If the high bit was set, it was encoding a negative */
4487 + if (val >= (1 << (code->width - 1)))
4488 + return (int32_t)0 - (int32_t)(((u32)1 << code->width) -
4489 + val);
4490 + /* Otherwise, it was encoding a positive */
4491 + return (int32_t)val;
4492 +}
4493 +
4494 +/* ---------------------- */
4495 +/* Descriptors/cachelines */
4496 +/* ---------------------- */
4497 +
4498 +/* To avoid needless dynamic allocation, the driver API often gives the caller
4499 + * a "descriptor" type that the caller can instantiate however they like.
4500 + * Ultimately though, it is just a cacheline of binary storage (or something
4501 + * smaller when it is known that the descriptor doesn't need all 64 bytes) for
4502 + * holding pre-formatted pieces of hardware commands. The performance-critical
4503 + * code can then copy these descriptors directly into hardware command
4504 + * registers more efficiently than trying to construct/format commands
4505 + * on-the-fly. The API user sees the descriptor as an array of 32-bit words in
4506 + * order for the compiler to know its size, but the internal details are not
4507 + * exposed. The following macro is used within the driver for converting *any*
4508 + * descriptor pointer to a usable array pointer. The use of a macro (instead of
4509 + * an inline) is necessary to work with different descriptor types and to work
4510 + * correctly with const and non-const inputs (and similarly-qualified outputs).
4511 + */
4512 +#define qb_cl(d) (&(d)->dont_manipulate_directly[0])
4513 +
4514 +#endif /* __FSL_QBMAN_PORTAL_H */
4515 diff --git a/drivers/staging/fsl-mc/bus/dpio/qbman_debug.c b/drivers/staging/fsl-mc/bus/dpio/qbman_debug.c
4516 new file mode 100644
4517 index 00000000..1c77fa6a
4518 --- /dev/null
4519 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman_debug.c
4520 @@ -0,0 +1,853 @@
4521 +/* Copyright (C) 2015 Freescale Semiconductor, Inc.
4522 + *
4523 + * Redistribution and use in source and binary forms, with or without
4524 + * modification, are permitted provided that the following conditions are met:
4525 + * * Redistributions of source code must retain the above copyright
4526 + * notice, this list of conditions and the following disclaimer.
4527 + * * Redistributions in binary form must reproduce the above copyright
4528 + * notice, this list of conditions and the following disclaimer in the
4529 + * documentation and/or other materials provided with the distribution.
4530 + * * Neither the name of Freescale Semiconductor nor the
4531 + * names of its contributors may be used to endorse or promote products
4532 + * derived from this software without specific prior written permission.
4533 + *
4534 + *
4535 + * ALTERNATIVELY, this software may be distributed under the terms of the
4536 + * GNU General Public License ("GPL") as published by the Free Software
4537 + * Foundation, either version 2 of that License or (at your option) any
4538 + * later version.
4539 + *
4540 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
4541 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
4542 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
4543 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
4544 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
4545 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
4546 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
4547 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4548 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
4549 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4550 + */
4551 +
4552 +#include <linux/errno.h>
4553 +
4554 +#include "../../include/dpaa2-global.h"
4555 +#include "qbman-portal.h"
4556 +#include "qbman_debug.h"
4557 +
4558 +/* QBMan portal management command code */
4559 +#define QBMAN_BP_QUERY 0x32
4560 +#define QBMAN_FQ_QUERY 0x44
4561 +#define QBMAN_FQ_QUERY_NP 0x45
4562 +#define QBMAN_CGR_QUERY 0x51
4563 +#define QBMAN_WRED_QUERY 0x54
4564 +#define QBMAN_CGR_STAT_QUERY 0x55
4565 +#define QBMAN_CGR_STAT_QUERY_CLR 0x56
4566 +
4567 +enum qbman_attr_usage_e {
4568 + qbman_attr_usage_fq,
4569 + qbman_attr_usage_bpool,
4570 + qbman_attr_usage_cgr,
4571 +};
4572 +
4573 +struct int_qbman_attr {
4574 + u32 words[32];
4575 + enum qbman_attr_usage_e usage;
4576 +};
4577 +
4578 +#define attr_type_set(a, e) \
4579 +{ \
4580 + struct qbman_attr *__attr = a; \
4581 + enum qbman_attr_usage_e __usage = e; \
4582 + ((struct int_qbman_attr *)__attr)->usage = __usage; \
4583 +}
4584 +
4585 +#define ATTR32(d) (&(d)->dont_manipulate_directly[0])
4586 +#define ATTR32_1(d) (&(d)->dont_manipulate_directly[16])
4587 +
4588 +static struct qb_attr_code code_bp_bpid = QB_CODE(0, 16, 16);
4589 +static struct qb_attr_code code_bp_bdi = QB_CODE(1, 16, 1);
4590 +static struct qb_attr_code code_bp_va = QB_CODE(1, 17, 1);
4591 +static struct qb_attr_code code_bp_wae = QB_CODE(1, 18, 1);
4592 +static struct qb_attr_code code_bp_swdet = QB_CODE(4, 0, 16);
4593 +static struct qb_attr_code code_bp_swdxt = QB_CODE(4, 16, 16);
4594 +static struct qb_attr_code code_bp_hwdet = QB_CODE(5, 0, 16);
4595 +static struct qb_attr_code code_bp_hwdxt = QB_CODE(5, 16, 16);
4596 +static struct qb_attr_code code_bp_swset = QB_CODE(6, 0, 16);
4597 +static struct qb_attr_code code_bp_swsxt = QB_CODE(6, 16, 16);
4598 +static struct qb_attr_code code_bp_vbpid = QB_CODE(7, 0, 14);
4599 +static struct qb_attr_code code_bp_icid = QB_CODE(7, 16, 15);
4600 +static struct qb_attr_code code_bp_pl = QB_CODE(7, 31, 1);
4601 +static struct qb_attr_code code_bp_bpscn_addr_lo = QB_CODE(8, 0, 32);
4602 +static struct qb_attr_code code_bp_bpscn_addr_hi = QB_CODE(9, 0, 32);
4603 +static struct qb_attr_code code_bp_bpscn_ctx_lo = QB_CODE(10, 0, 32);
4604 +static struct qb_attr_code code_bp_bpscn_ctx_hi = QB_CODE(11, 0, 32);
4605 +static struct qb_attr_code code_bp_hw_targ = QB_CODE(12, 0, 16);
4606 +static struct qb_attr_code code_bp_state = QB_CODE(1, 24, 3);
4607 +static struct qb_attr_code code_bp_fill = QB_CODE(2, 0, 32);
4608 +static struct qb_attr_code code_bp_hdptr = QB_CODE(3, 0, 32);
4609 +static struct qb_attr_code code_bp_sdcnt = QB_CODE(13, 0, 8);
4610 +static struct qb_attr_code code_bp_hdcnt = QB_CODE(13, 1, 8);
4611 +static struct qb_attr_code code_bp_sscnt = QB_CODE(13, 2, 8);
4612 +
4613 +void qbman_bp_attr_clear(struct qbman_attr *a)
4614 +{
4615 + memset(a, 0, sizeof(*a));
4616 + attr_type_set(a, qbman_attr_usage_bpool);
4617 +}
4618 +
4619 +int qbman_bp_query(struct qbman_swp *s, u32 bpid,
4620 + struct qbman_attr *a)
4621 +{
4622 + u32 *p;
4623 + u32 verb, rslt;
4624 + u32 *attr = ATTR32(a);
4625 +
4626 + qbman_bp_attr_clear(a);
4627 +
4628 + /* Start the management command */
4629 + p = qbman_swp_mc_start(s);
4630 + if (!p)
4631 + return -EBUSY;
4632 +
4633 + /* Encode the caller-provided attributes */
4634 + qb_attr_code_encode(&code_bp_bpid, p, bpid);
4635 +
4636 + /* Complete the management command */
4637 + p = qbman_swp_mc_complete(s, p, QBMAN_BP_QUERY);
4638 +
4639 + /* Decode the outcome */
4640 + verb = qb_attr_code_decode(&code_generic_verb, p);
4641 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
4642 + WARN_ON(verb != QBMAN_BP_QUERY);
4643 +
4644 + /* Determine success or failure */
4645 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
4646 + pr_err("Query of BPID 0x%x failed, code=0x%02x\n", bpid, rslt);
4647 + return -EIO;
4648 + }
4649 +
4650 + /* For the query, word[0] of the result contains only the
4651 + * verb/rslt fields, so skip word[0].
4652 + */
4653 + word_copy(&attr[1], &p[1], 15);
4654 + return 0;
4655 +}
4656 +
4657 +void qbman_bp_attr_get_bdi(struct qbman_attr *a, int *bdi, int *va, int *wae)
4658 +{
4659 + u32 *p = ATTR32(a);
4660 +
4661 + *bdi = !!qb_attr_code_decode(&code_bp_bdi, p);
4662 + *va = !!qb_attr_code_decode(&code_bp_va, p);
4663 + *wae = !!qb_attr_code_decode(&code_bp_wae, p);
4664 +}
4665 +
4666 +static u32 qbman_bp_thresh_to_value(u32 val)
4667 +{
4668 + return (val & 0xff) << ((val & 0xf00) >> 8);
4669 +}
4670 +
4671 +void qbman_bp_attr_get_swdet(struct qbman_attr *a, u32 *swdet)
4672 +{
4673 + u32 *p = ATTR32(a);
4674 +
4675 + *swdet = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swdet,
4676 + p));
4677 +}
4678 +
4679 +void qbman_bp_attr_get_swdxt(struct qbman_attr *a, u32 *swdxt)
4680 +{
4681 + u32 *p = ATTR32(a);
4682 +
4683 + *swdxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swdxt,
4684 + p));
4685 +}
4686 +
4687 +void qbman_bp_attr_get_hwdet(struct qbman_attr *a, u32 *hwdet)
4688 +{
4689 + u32 *p = ATTR32(a);
4690 +
4691 + *hwdet = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_hwdet,
4692 + p));
4693 +}
4694 +
4695 +void qbman_bp_attr_get_hwdxt(struct qbman_attr *a, u32 *hwdxt)
4696 +{
4697 + u32 *p = ATTR32(a);
4698 +
4699 + *hwdxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_hwdxt,
4700 + p));
4701 +}
4702 +
4703 +void qbman_bp_attr_get_swset(struct qbman_attr *a, u32 *swset)
4704 +{
4705 + u32 *p = ATTR32(a);
4706 +
4707 + *swset = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swset,
4708 + p));
4709 +}
4710 +
4711 +void qbman_bp_attr_get_swsxt(struct qbman_attr *a, u32 *swsxt)
4712 +{
4713 + u32 *p = ATTR32(a);
4714 +
4715 + *swsxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swsxt,
4716 + p));
4717 +}
4718 +
4719 +void qbman_bp_attr_get_vbpid(struct qbman_attr *a, u32 *vbpid)
4720 +{
4721 + u32 *p = ATTR32(a);
4722 +
4723 + *vbpid = qb_attr_code_decode(&code_bp_vbpid, p);
4724 +}
4725 +
4726 +void qbman_bp_attr_get_icid(struct qbman_attr *a, u32 *icid, int *pl)
4727 +{
4728 + u32 *p = ATTR32(a);
4729 +
4730 + *icid = qb_attr_code_decode(&code_bp_icid, p);
4731 + *pl = !!qb_attr_code_decode(&code_bp_pl, p);
4732 +}
4733 +
4734 +void qbman_bp_attr_get_bpscn_addr(struct qbman_attr *a, u64 *bpscn_addr)
4735 +{
4736 + u32 *p = ATTR32(a);
4737 +
4738 + *bpscn_addr = ((u64)qb_attr_code_decode(&code_bp_bpscn_addr_hi,
4739 + p) << 32) |
4740 + (u64)qb_attr_code_decode(&code_bp_bpscn_addr_lo,
4741 + p);
4742 +}
4743 +
4744 +void qbman_bp_attr_get_bpscn_ctx(struct qbman_attr *a, u64 *bpscn_ctx)
4745 +{
4746 + u32 *p = ATTR32(a);
4747 +
4748 + *bpscn_ctx = ((u64)qb_attr_code_decode(&code_bp_bpscn_ctx_hi, p)
4749 + << 32) |
4750 + (u64)qb_attr_code_decode(&code_bp_bpscn_ctx_lo,
4751 + p);
4752 +}
4753 +
4754 +void qbman_bp_attr_get_hw_targ(struct qbman_attr *a, u32 *hw_targ)
4755 +{
4756 + u32 *p = ATTR32(a);
4757 +
4758 + *hw_targ = qb_attr_code_decode(&code_bp_hw_targ, p);
4759 +}
4760 +
4761 +int qbman_bp_info_has_free_bufs(struct qbman_attr *a)
4762 +{
4763 + u32 *p = ATTR32(a);
4764 +
4765 + return !(int)(qb_attr_code_decode(&code_bp_state, p) & 0x1);
4766 +}
4767 +
4768 +int qbman_bp_info_is_depleted(struct qbman_attr *a)
4769 +{
4770 + u32 *p = ATTR32(a);
4771 +
4772 + return (int)(qb_attr_code_decode(&code_bp_state, p) & 0x2);
4773 +}
4774 +
4775 +int qbman_bp_info_is_surplus(struct qbman_attr *a)
4776 +{
4777 + u32 *p = ATTR32(a);
4778 +
4779 + return (int)(qb_attr_code_decode(&code_bp_state, p) & 0x4);
4780 +}
4781 +
4782 +u32 qbman_bp_info_num_free_bufs(struct qbman_attr *a)
4783 +{
4784 + u32 *p = ATTR32(a);
4785 +
4786 + return qb_attr_code_decode(&code_bp_fill, p);
4787 +}
4788 +
4789 +u32 qbman_bp_info_hdptr(struct qbman_attr *a)
4790 +{
4791 + u32 *p = ATTR32(a);
4792 +
4793 + return qb_attr_code_decode(&code_bp_hdptr, p);
4794 +}
4795 +
4796 +u32 qbman_bp_info_sdcnt(struct qbman_attr *a)
4797 +{
4798 + u32 *p = ATTR32(a);
4799 +
4800 + return qb_attr_code_decode(&code_bp_sdcnt, p);
4801 +}
4802 +
4803 +u32 qbman_bp_info_hdcnt(struct qbman_attr *a)
4804 +{
4805 + u32 *p = ATTR32(a);
4806 +
4807 + return qb_attr_code_decode(&code_bp_hdcnt, p);
4808 +}
4809 +
4810 +u32 qbman_bp_info_sscnt(struct qbman_attr *a)
4811 +{
4812 + u32 *p = ATTR32(a);
4813 +
4814 + return qb_attr_code_decode(&code_bp_sscnt, p);
4815 +}
4816 +
4817 +static struct qb_attr_code code_fq_fqid = QB_CODE(1, 0, 24);
4818 +static struct qb_attr_code code_fq_cgrid = QB_CODE(2, 16, 16);
4819 +static struct qb_attr_code code_fq_destwq = QB_CODE(3, 0, 15);
4820 +static struct qb_attr_code code_fq_fqctrl = QB_CODE(3, 24, 8);
4821 +static struct qb_attr_code code_fq_icscred = QB_CODE(4, 0, 15);
4822 +static struct qb_attr_code code_fq_tdthresh = QB_CODE(4, 16, 13);
4823 +static struct qb_attr_code code_fq_oa_len = QB_CODE(5, 0, 12);
4824 +static struct qb_attr_code code_fq_oa_ics = QB_CODE(5, 14, 1);
4825 +static struct qb_attr_code code_fq_oa_cgr = QB_CODE(5, 15, 1);
4826 +static struct qb_attr_code code_fq_mctl_bdi = QB_CODE(5, 24, 1);
4827 +static struct qb_attr_code code_fq_mctl_ff = QB_CODE(5, 25, 1);
4828 +static struct qb_attr_code code_fq_mctl_va = QB_CODE(5, 26, 1);
4829 +static struct qb_attr_code code_fq_mctl_ps = QB_CODE(5, 27, 1);
4830 +static struct qb_attr_code code_fq_ctx_lower32 = QB_CODE(6, 0, 32);
4831 +static struct qb_attr_code code_fq_ctx_upper32 = QB_CODE(7, 0, 32);
4832 +static struct qb_attr_code code_fq_icid = QB_CODE(8, 0, 15);
4833 +static struct qb_attr_code code_fq_pl = QB_CODE(8, 15, 1);
4834 +static struct qb_attr_code code_fq_vfqid = QB_CODE(9, 0, 24);
4835 +static struct qb_attr_code code_fq_erfqid = QB_CODE(10, 0, 24);
4836 +
4837 +void qbman_fq_attr_clear(struct qbman_attr *a)
4838 +{
4839 + memset(a, 0, sizeof(*a));
4840 + attr_type_set(a, qbman_attr_usage_fq);
4841 +}
4842 +
4843 +/* FQ query function for programmable fields */
4844 +int qbman_fq_query(struct qbman_swp *s, u32 fqid, struct qbman_attr *desc)
4845 +{
4846 + u32 *p;
4847 + u32 verb, rslt;
4848 + u32 *d = ATTR32(desc);
4849 +
4850 + qbman_fq_attr_clear(desc);
4851 +
4852 + p = qbman_swp_mc_start(s);
4853 + if (!p)
4854 + return -EBUSY;
4855 + qb_attr_code_encode(&code_fq_fqid, p, fqid);
4856 + p = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY);
4857 +
4858 + /* Decode the outcome */
4859 + verb = qb_attr_code_decode(&code_generic_verb, p);
4860 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
4861 + WARN_ON(verb != QBMAN_FQ_QUERY);
4862 +
4863 + /* Determine success or failure */
4864 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
4865 + pr_err("Query of FQID 0x%x failed, code=0x%02x\n",
4866 + fqid, rslt);
4867 + return -EIO;
4868 + }
4869 + /*
4870 + * For the configure, word[0] of the command contains only the WE-mask.
4871 + * For the query, word[0] of the result contains only the verb/rslt
4872 + * fields. Skip word[0] in the latter case.
4873 + */
4874 + word_copy(&d[1], &p[1], 15);
4875 + return 0;
4876 +}
4877 +
4878 +void qbman_fq_attr_get_fqctrl(struct qbman_attr *d, u32 *fqctrl)
4879 +{
4880 + u32 *p = ATTR32(d);
4881 +
4882 + *fqctrl = qb_attr_code_decode(&code_fq_fqctrl, p);
4883 +}
4884 +
4885 +void qbman_fq_attr_get_cgrid(struct qbman_attr *d, u32 *cgrid)
4886 +{
4887 + u32 *p = ATTR32(d);
4888 +
4889 + *cgrid = qb_attr_code_decode(&code_fq_cgrid, p);
4890 +}
4891 +
4892 +void qbman_fq_attr_get_destwq(struct qbman_attr *d, u32 *destwq)
4893 +{
4894 + u32 *p = ATTR32(d);
4895 +
4896 + *destwq = qb_attr_code_decode(&code_fq_destwq, p);
4897 +}
4898 +
4899 +void qbman_fq_attr_get_icscred(struct qbman_attr *d, u32 *icscred)
4900 +{
4901 + u32 *p = ATTR32(d);
4902 +
4903 + *icscred = qb_attr_code_decode(&code_fq_icscred, p);
4904 +}
4905 +
4906 +static struct qb_attr_code code_tdthresh_exp = QB_CODE(0, 0, 5);
4907 +static struct qb_attr_code code_tdthresh_mant = QB_CODE(0, 5, 8);
4908 +static u32 qbman_thresh_to_value(u32 val)
4909 +{
4910 + u32 m, e;
4911 +
4912 + m = qb_attr_code_decode(&code_tdthresh_mant, &val);
4913 + e = qb_attr_code_decode(&code_tdthresh_exp, &val);
4914 + return m << e;
4915 +}
4916 +
4917 +void qbman_fq_attr_get_tdthresh(struct qbman_attr *d, u32 *tdthresh)
4918 +{
4919 + u32 *p = ATTR32(d);
4920 +
4921 + *tdthresh = qbman_thresh_to_value(qb_attr_code_decode(&code_fq_tdthresh,
4922 + p));
4923 +}
4924 +
4925 +void qbman_fq_attr_get_oa(struct qbman_attr *d,
4926 + int *oa_ics, int *oa_cgr, int32_t *oa_len)
4927 +{
4928 + u32 *p = ATTR32(d);
4929 +
4930 + *oa_ics = !!qb_attr_code_decode(&code_fq_oa_ics, p);
4931 + *oa_cgr = !!qb_attr_code_decode(&code_fq_oa_cgr, p);
4932 + *oa_len = qb_attr_code_makesigned(&code_fq_oa_len,
4933 + qb_attr_code_decode(&code_fq_oa_len, p));
4934 +}
4935 +
4936 +void qbman_fq_attr_get_mctl(struct qbman_attr *d,
4937 + int *bdi, int *ff, int *va, int *ps)
4938 +{
4939 + u32 *p = ATTR32(d);
4940 +
4941 + *bdi = !!qb_attr_code_decode(&code_fq_mctl_bdi, p);
4942 + *ff = !!qb_attr_code_decode(&code_fq_mctl_ff, p);
4943 + *va = !!qb_attr_code_decode(&code_fq_mctl_va, p);
4944 + *ps = !!qb_attr_code_decode(&code_fq_mctl_ps, p);
4945 +}
4946 +
4947 +void qbman_fq_attr_get_ctx(struct qbman_attr *d, u32 *hi, u32 *lo)
4948 +{
4949 + u32 *p = ATTR32(d);
4950 +
4951 + *hi = qb_attr_code_decode(&code_fq_ctx_upper32, p);
4952 + *lo = qb_attr_code_decode(&code_fq_ctx_lower32, p);
4953 +}
4954 +
4955 +void qbman_fq_attr_get_icid(struct qbman_attr *d, u32 *icid, int *pl)
4956 +{
4957 + u32 *p = ATTR32(d);
4958 +
4959 + *icid = qb_attr_code_decode(&code_fq_icid, p);
4960 + *pl = !!qb_attr_code_decode(&code_fq_pl, p);
4961 +}
4962 +
4963 +void qbman_fq_attr_get_vfqid(struct qbman_attr *d, u32 *vfqid)
4964 +{
4965 + u32 *p = ATTR32(d);
4966 +
4967 + *vfqid = qb_attr_code_decode(&code_fq_vfqid, p);
4968 +}
4969 +
4970 +void qbman_fq_attr_get_erfqid(struct qbman_attr *d, u32 *erfqid)
4971 +{
4972 + u32 *p = ATTR32(d);
4973 +
4974 + *erfqid = qb_attr_code_decode(&code_fq_erfqid, p);
4975 +}
4976 +
4977 +/* Query FQ Non-Programmalbe Fields */
4978 +static struct qb_attr_code code_fq_np_state = QB_CODE(0, 16, 3);
4979 +static struct qb_attr_code code_fq_np_fe = QB_CODE(0, 19, 1);
4980 +static struct qb_attr_code code_fq_np_x = QB_CODE(0, 20, 1);
4981 +static struct qb_attr_code code_fq_np_r = QB_CODE(0, 21, 1);
4982 +static struct qb_attr_code code_fq_np_oe = QB_CODE(0, 22, 1);
4983 +static struct qb_attr_code code_fq_np_frm_cnt = QB_CODE(6, 0, 24);
4984 +static struct qb_attr_code code_fq_np_byte_cnt = QB_CODE(7, 0, 32);
4985 +
4986 +int qbman_fq_query_state(struct qbman_swp *s, u32 fqid,
4987 + struct qbman_attr *state)
4988 +{
4989 + u32 *p;
4990 + u32 verb, rslt;
4991 + u32 *d = ATTR32(state);
4992 +
4993 + qbman_fq_attr_clear(state);
4994 +
4995 + p = qbman_swp_mc_start(s);
4996 + if (!p)
4997 + return -EBUSY;
4998 + qb_attr_code_encode(&code_fq_fqid, p, fqid);
4999 + p = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY_NP);
5000 +
5001 + /* Decode the outcome */
5002 + verb = qb_attr_code_decode(&code_generic_verb, p);
5003 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
5004 + WARN_ON(verb != QBMAN_FQ_QUERY_NP);
5005 +
5006 + /* Determine success or failure */
5007 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
5008 + pr_err("Query NP fields of FQID 0x%x failed, code=0x%02x\n",
5009 + fqid, rslt);
5010 + return -EIO;
5011 + }
5012 + word_copy(&d[0], &p[0], 16);
5013 + return 0;
5014 +}
5015 +
5016 +u32 qbman_fq_state_schedstate(const struct qbman_attr *state)
5017 +{
5018 + const u32 *p = ATTR32(state);
5019 +
5020 + return qb_attr_code_decode(&code_fq_np_state, p);
5021 +}
5022 +
5023 +int qbman_fq_state_force_eligible(const struct qbman_attr *state)
5024 +{
5025 + const u32 *p = ATTR32(state);
5026 +
5027 + return !!qb_attr_code_decode(&code_fq_np_fe, p);
5028 +}
5029 +
5030 +int qbman_fq_state_xoff(const struct qbman_attr *state)
5031 +{
5032 + const u32 *p = ATTR32(state);
5033 +
5034 + return !!qb_attr_code_decode(&code_fq_np_x, p);
5035 +}
5036 +
5037 +int qbman_fq_state_retirement_pending(const struct qbman_attr *state)
5038 +{
5039 + const u32 *p = ATTR32(state);
5040 +
5041 + return !!qb_attr_code_decode(&code_fq_np_r, p);
5042 +}
5043 +
5044 +int qbman_fq_state_overflow_error(const struct qbman_attr *state)
5045 +{
5046 + const u32 *p = ATTR32(state);
5047 +
5048 + return !!qb_attr_code_decode(&code_fq_np_oe, p);
5049 +}
5050 +
5051 +u32 qbman_fq_state_frame_count(const struct qbman_attr *state)
5052 +{
5053 + const u32 *p = ATTR32(state);
5054 +
5055 + return qb_attr_code_decode(&code_fq_np_frm_cnt, p);
5056 +}
5057 +
5058 +u32 qbman_fq_state_byte_count(const struct qbman_attr *state)
5059 +{
5060 + const u32 *p = ATTR32(state);
5061 +
5062 + return qb_attr_code_decode(&code_fq_np_byte_cnt, p);
5063 +}
5064 +
5065 +/* Query CGR */
5066 +static struct qb_attr_code code_cgr_cgid = QB_CODE(0, 16, 16);
5067 +static struct qb_attr_code code_cgr_cscn_wq_en_enter = QB_CODE(2, 0, 1);
5068 +static struct qb_attr_code code_cgr_cscn_wq_en_exit = QB_CODE(2, 1, 1);
5069 +static struct qb_attr_code code_cgr_cscn_wq_icd = QB_CODE(2, 2, 1);
5070 +static struct qb_attr_code code_cgr_mode = QB_CODE(3, 16, 2);
5071 +static struct qb_attr_code code_cgr_rej_cnt_mode = QB_CODE(3, 18, 1);
5072 +static struct qb_attr_code code_cgr_cscn_bdi = QB_CODE(3, 19, 1);
5073 +static struct qb_attr_code code_cgr_cscn_wr_en_enter = QB_CODE(3, 24, 1);
5074 +static struct qb_attr_code code_cgr_cscn_wr_en_exit = QB_CODE(3, 25, 1);
5075 +static struct qb_attr_code code_cgr_cg_wr_ae = QB_CODE(3, 26, 1);
5076 +static struct qb_attr_code code_cgr_cscn_dcp_en = QB_CODE(3, 27, 1);
5077 +static struct qb_attr_code code_cgr_cg_wr_va = QB_CODE(3, 28, 1);
5078 +static struct qb_attr_code code_cgr_i_cnt_wr_en = QB_CODE(4, 0, 1);
5079 +static struct qb_attr_code code_cgr_i_cnt_wr_bnd = QB_CODE(4, 1, 5);
5080 +static struct qb_attr_code code_cgr_td_en = QB_CODE(4, 8, 1);
5081 +static struct qb_attr_code code_cgr_cs_thres = QB_CODE(4, 16, 13);
5082 +static struct qb_attr_code code_cgr_cs_thres_x = QB_CODE(5, 0, 13);
5083 +static struct qb_attr_code code_cgr_td_thres = QB_CODE(5, 16, 13);
5084 +static struct qb_attr_code code_cgr_cscn_tdcp = QB_CODE(6, 0, 16);
5085 +static struct qb_attr_code code_cgr_cscn_wqid = QB_CODE(6, 16, 16);
5086 +static struct qb_attr_code code_cgr_cscn_vcgid = QB_CODE(7, 0, 16);
5087 +static struct qb_attr_code code_cgr_cg_icid = QB_CODE(7, 16, 15);
5088 +static struct qb_attr_code code_cgr_cg_pl = QB_CODE(7, 31, 1);
5089 +static struct qb_attr_code code_cgr_cg_wr_addr_lo = QB_CODE(8, 0, 32);
5090 +static struct qb_attr_code code_cgr_cg_wr_addr_hi = QB_CODE(9, 0, 32);
5091 +static struct qb_attr_code code_cgr_cscn_ctx_lo = QB_CODE(10, 0, 32);
5092 +static struct qb_attr_code code_cgr_cscn_ctx_hi = QB_CODE(11, 0, 32);
5093 +
5094 +void qbman_cgr_attr_clear(struct qbman_attr *a)
5095 +{
5096 + memset(a, 0, sizeof(*a));
5097 + attr_type_set(a, qbman_attr_usage_cgr);
5098 +}
5099 +
5100 +int qbman_cgr_query(struct qbman_swp *s, u32 cgid, struct qbman_attr *attr)
5101 +{
5102 + u32 *p;
5103 + u32 verb, rslt;
5104 + u32 *d[2];
5105 + int i;
5106 + u32 query_verb;
5107 +
5108 + d[0] = ATTR32(attr);
5109 + d[1] = ATTR32_1(attr);
5110 +
5111 + qbman_cgr_attr_clear(attr);
5112 +
5113 + for (i = 0; i < 2; i++) {
5114 + p = qbman_swp_mc_start(s);
5115 + if (!p)
5116 + return -EBUSY;
5117 + query_verb = i ? QBMAN_WRED_QUERY : QBMAN_CGR_QUERY;
5118 +
5119 + qb_attr_code_encode(&code_cgr_cgid, p, cgid);
5120 + p = qbman_swp_mc_complete(s, p, p[0] | query_verb);
5121 +
5122 + /* Decode the outcome */
5123 + verb = qb_attr_code_decode(&code_generic_verb, p);
5124 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
5125 + WARN_ON(verb != query_verb);
5126 +
5127 + /* Determine success or failure */
5128 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
5129 + pr_err("Query CGID 0x%x failed,", cgid);
5130 + pr_err(" verb=0x%02x, code=0x%02x\n", verb, rslt);
5131 + return -EIO;
5132 + }
5133 + /* For the configure, word[0] of the command contains only the
5134 + * verb/cgid. For the query, word[0] of the result contains
5135 + * only the verb/rslt fields. Skip word[0] in the latter case.
5136 + */
5137 + word_copy(&d[i][1], &p[1], 15);
5138 + }
5139 + return 0;
5140 +}
5141 +
5142 +void qbman_cgr_attr_get_ctl1(struct qbman_attr *d, int *cscn_wq_en_enter,
5143 + int *cscn_wq_en_exit, int *cscn_wq_icd)
5144 + {
5145 + u32 *p = ATTR32(d);
5146 + *cscn_wq_en_enter = !!qb_attr_code_decode(&code_cgr_cscn_wq_en_enter,
5147 + p);
5148 + *cscn_wq_en_exit = !!qb_attr_code_decode(&code_cgr_cscn_wq_en_exit, p);
5149 + *cscn_wq_icd = !!qb_attr_code_decode(&code_cgr_cscn_wq_icd, p);
5150 +}
5151 +
5152 +void qbman_cgr_attr_get_mode(struct qbman_attr *d, u32 *mode,
5153 + int *rej_cnt_mode, int *cscn_bdi)
5154 +{
5155 + u32 *p = ATTR32(d);
5156 + *mode = qb_attr_code_decode(&code_cgr_mode, p);
5157 + *rej_cnt_mode = !!qb_attr_code_decode(&code_cgr_rej_cnt_mode, p);
5158 + *cscn_bdi = !!qb_attr_code_decode(&code_cgr_cscn_bdi, p);
5159 +}
5160 +
5161 +void qbman_cgr_attr_get_ctl2(struct qbman_attr *d, int *cscn_wr_en_enter,
5162 + int *cscn_wr_en_exit, int *cg_wr_ae,
5163 + int *cscn_dcp_en, int *cg_wr_va)
5164 +{
5165 + u32 *p = ATTR32(d);
5166 + *cscn_wr_en_enter = !!qb_attr_code_decode(&code_cgr_cscn_wr_en_enter,
5167 + p);
5168 + *cscn_wr_en_exit = !!qb_attr_code_decode(&code_cgr_cscn_wr_en_exit, p);
5169 + *cg_wr_ae = !!qb_attr_code_decode(&code_cgr_cg_wr_ae, p);
5170 + *cscn_dcp_en = !!qb_attr_code_decode(&code_cgr_cscn_dcp_en, p);
5171 + *cg_wr_va = !!qb_attr_code_decode(&code_cgr_cg_wr_va, p);
5172 +}
5173 +
5174 +void qbman_cgr_attr_get_iwc(struct qbman_attr *d, int *i_cnt_wr_en,
5175 + u32 *i_cnt_wr_bnd)
5176 +{
5177 + u32 *p = ATTR32(d);
5178 + *i_cnt_wr_en = !!qb_attr_code_decode(&code_cgr_i_cnt_wr_en, p);
5179 + *i_cnt_wr_bnd = qb_attr_code_decode(&code_cgr_i_cnt_wr_bnd, p);
5180 +}
5181 +
5182 +void qbman_cgr_attr_get_tdc(struct qbman_attr *d, int *td_en)
5183 +{
5184 + u32 *p = ATTR32(d);
5185 + *td_en = !!qb_attr_code_decode(&code_cgr_td_en, p);
5186 +}
5187 +
5188 +void qbman_cgr_attr_get_cs_thres(struct qbman_attr *d, u32 *cs_thres)
5189 +{
5190 + u32 *p = ATTR32(d);
5191 + *cs_thres = qbman_thresh_to_value(qb_attr_code_decode(
5192 + &code_cgr_cs_thres, p));
5193 +}
5194 +
5195 +void qbman_cgr_attr_get_cs_thres_x(struct qbman_attr *d,
5196 + u32 *cs_thres_x)
5197 +{
5198 + u32 *p = ATTR32(d);
5199 + *cs_thres_x = qbman_thresh_to_value(qb_attr_code_decode(
5200 + &code_cgr_cs_thres_x, p));
5201 +}
5202 +
5203 +void qbman_cgr_attr_get_td_thres(struct qbman_attr *d, u32 *td_thres)
5204 +{
5205 + u32 *p = ATTR32(d);
5206 + *td_thres = qbman_thresh_to_value(qb_attr_code_decode(
5207 + &code_cgr_td_thres, p));
5208 +}
5209 +
5210 +void qbman_cgr_attr_get_cscn_tdcp(struct qbman_attr *d, u32 *cscn_tdcp)
5211 +{
5212 + u32 *p = ATTR32(d);
5213 + *cscn_tdcp = qb_attr_code_decode(&code_cgr_cscn_tdcp, p);
5214 +}
5215 +
5216 +void qbman_cgr_attr_get_cscn_wqid(struct qbman_attr *d, u32 *cscn_wqid)
5217 +{
5218 + u32 *p = ATTR32(d);
5219 + *cscn_wqid = qb_attr_code_decode(&code_cgr_cscn_wqid, p);
5220 +}
5221 +
5222 +void qbman_cgr_attr_get_cscn_vcgid(struct qbman_attr *d,
5223 + u32 *cscn_vcgid)
5224 +{
5225 + u32 *p = ATTR32(d);
5226 + *cscn_vcgid = qb_attr_code_decode(&code_cgr_cscn_vcgid, p);
5227 +}
5228 +
5229 +void qbman_cgr_attr_get_cg_icid(struct qbman_attr *d, u32 *icid,
5230 + int *pl)
5231 +{
5232 + u32 *p = ATTR32(d);
5233 + *icid = qb_attr_code_decode(&code_cgr_cg_icid, p);
5234 + *pl = !!qb_attr_code_decode(&code_cgr_cg_pl, p);
5235 +}
5236 +
5237 +void qbman_cgr_attr_get_cg_wr_addr(struct qbman_attr *d,
5238 + u64 *cg_wr_addr)
5239 +{
5240 + u32 *p = ATTR32(d);
5241 + *cg_wr_addr = ((u64)qb_attr_code_decode(&code_cgr_cg_wr_addr_hi,
5242 + p) << 32) |
5243 + (u64)qb_attr_code_decode(&code_cgr_cg_wr_addr_lo,
5244 + p);
5245 +}
5246 +
5247 +void qbman_cgr_attr_get_cscn_ctx(struct qbman_attr *d, u64 *cscn_ctx)
5248 +{
5249 + u32 *p = ATTR32(d);
5250 + *cscn_ctx = ((u64)qb_attr_code_decode(&code_cgr_cscn_ctx_hi, p)
5251 + << 32) |
5252 + (u64)qb_attr_code_decode(&code_cgr_cscn_ctx_lo, p);
5253 +}
5254 +
5255 +#define WRED_EDP_WORD(n) (18 + (n) / 4)
5256 +#define WRED_EDP_OFFSET(n) (8 * ((n) % 4))
5257 +#define WRED_PARM_DP_WORD(n) ((n) + 20)
5258 +#define WRED_WE_EDP(n) (16 + (n) * 2)
5259 +#define WRED_WE_PARM_DP(n) (17 + (n) * 2)
5260 +void qbman_cgr_attr_wred_get_edp(struct qbman_attr *d, u32 idx,
5261 + int *edp)
5262 +{
5263 + u32 *p = ATTR32(d);
5264 + struct qb_attr_code code_wred_edp = QB_CODE(WRED_EDP_WORD(idx),
5265 + WRED_EDP_OFFSET(idx), 8);
5266 + *edp = (int)qb_attr_code_decode(&code_wred_edp, p);
5267 +}
5268 +
5269 +void qbman_cgr_attr_wred_dp_decompose(u32 dp, u64 *minth,
5270 + u64 *maxth, u8 *maxp)
5271 +{
5272 + u8 ma, mn, step_i, step_s, pn;
5273 +
5274 + ma = (u8)(dp >> 24);
5275 + mn = (u8)(dp >> 19) & 0x1f;
5276 + step_i = (u8)(dp >> 11);
5277 + step_s = (u8)(dp >> 6) & 0x1f;
5278 + pn = (u8)dp & 0x3f;
5279 +
5280 + *maxp = ((pn << 2) * 100) / 256;
5281 +
5282 + if (mn == 0)
5283 + *maxth = ma;
5284 + else
5285 + *maxth = ((ma + 256) * (1 << (mn - 1)));
5286 +
5287 + if (step_s == 0)
5288 + *minth = *maxth - step_i;
5289 + else
5290 + *minth = *maxth - (256 + step_i) * (1 << (step_s - 1));
5291 +}
5292 +
5293 +void qbman_cgr_attr_wred_get_parm_dp(struct qbman_attr *d, u32 idx,
5294 + u32 *dp)
5295 +{
5296 + u32 *p = ATTR32(d);
5297 + struct qb_attr_code code_wred_parm_dp = QB_CODE(WRED_PARM_DP_WORD(idx),
5298 + 0, 8);
5299 + *dp = qb_attr_code_decode(&code_wred_parm_dp, p);
5300 +}
5301 +
5302 +/* Query CGR/CCGR/CQ statistics */
5303 +static struct qb_attr_code code_cgr_stat_ct = QB_CODE(4, 0, 32);
5304 +static struct qb_attr_code code_cgr_stat_frame_cnt_lo = QB_CODE(4, 0, 32);
5305 +static struct qb_attr_code code_cgr_stat_frame_cnt_hi = QB_CODE(5, 0, 8);
5306 +static struct qb_attr_code code_cgr_stat_byte_cnt_lo = QB_CODE(6, 0, 32);
5307 +static struct qb_attr_code code_cgr_stat_byte_cnt_hi = QB_CODE(7, 0, 16);
5308 +static int qbman_cgr_statistics_query(struct qbman_swp *s, u32 cgid,
5309 + int clear, u32 command_type,
5310 + u64 *frame_cnt, u64 *byte_cnt)
5311 +{
5312 + u32 *p;
5313 + u32 verb, rslt;
5314 + u32 query_verb;
5315 + u32 hi, lo;
5316 +
5317 + p = qbman_swp_mc_start(s);
5318 + if (!p)
5319 + return -EBUSY;
5320 +
5321 + qb_attr_code_encode(&code_cgr_cgid, p, cgid);
5322 + if (command_type < 2)
5323 + qb_attr_code_encode(&code_cgr_stat_ct, p, command_type);
5324 + query_verb = clear ?
5325 + QBMAN_CGR_STAT_QUERY_CLR : QBMAN_CGR_STAT_QUERY;
5326 + p = qbman_swp_mc_complete(s, p, p[0] | query_verb);
5327 +
5328 + /* Decode the outcome */
5329 + verb = qb_attr_code_decode(&code_generic_verb, p);
5330 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
5331 + WARN_ON(verb != query_verb);
5332 +
5333 + /* Determine success or failure */
5334 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
5335 + pr_err("Query statistics of CGID 0x%x failed,", cgid);
5336 + pr_err(" verb=0x%02x code=0x%02x\n", verb, rslt);
5337 + return -EIO;
5338 + }
5339 +
5340 + if (*frame_cnt) {
5341 + hi = qb_attr_code_decode(&code_cgr_stat_frame_cnt_hi, p);
5342 + lo = qb_attr_code_decode(&code_cgr_stat_frame_cnt_lo, p);
5343 + *frame_cnt = ((u64)hi << 32) | (u64)lo;
5344 + }
5345 + if (*byte_cnt) {
5346 + hi = qb_attr_code_decode(&code_cgr_stat_byte_cnt_hi, p);
5347 + lo = qb_attr_code_decode(&code_cgr_stat_byte_cnt_lo, p);
5348 + *byte_cnt = ((u64)hi << 32) | (u64)lo;
5349 + }
5350 +
5351 + return 0;
5352 +}
5353 +
5354 +int qbman_cgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5355 + u64 *frame_cnt, u64 *byte_cnt)
5356 +{
5357 + return qbman_cgr_statistics_query(s, cgid, clear, 0xff,
5358 + frame_cnt, byte_cnt);
5359 +}
5360 +
5361 +int qbman_ccgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5362 + u64 *frame_cnt, u64 *byte_cnt)
5363 +{
5364 + return qbman_cgr_statistics_query(s, cgid, clear, 1,
5365 + frame_cnt, byte_cnt);
5366 +}
5367 +
5368 +int qbman_cq_dequeue_statistics(struct qbman_swp *s, u32 cgid, int clear,
5369 + u64 *frame_cnt, u64 *byte_cnt)
5370 +{
5371 + return qbman_cgr_statistics_query(s, cgid, clear, 0,
5372 + frame_cnt, byte_cnt);
5373 +}
5374 diff --git a/drivers/staging/fsl-mc/bus/dpio/qbman_debug.h b/drivers/staging/fsl-mc/bus/dpio/qbman_debug.h
5375 new file mode 100644
5376 index 00000000..0a247a49
5377 --- /dev/null
5378 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman_debug.h
5379 @@ -0,0 +1,136 @@
5380 +/* Copyright (C) 2015 Freescale Semiconductor, Inc.
5381 + *
5382 + * Redistribution and use in source and binary forms, with or without
5383 + * modification, are permitted provided that the following conditions are met:
5384 + * * Redistributions of source code must retain the above copyright
5385 + * notice, this list of conditions and the following disclaimer.
5386 + * * Redistributions in binary form must reproduce the above copyright
5387 + * notice, this list of conditions and the following disclaimer in the
5388 + * documentation and/or other materials provided with the distribution.
5389 + * * Neither the name of Freescale Semiconductor nor the
5390 + * names of its contributors may be used to endorse or promote products
5391 + * derived from this software without specific prior written permission.
5392 + *
5393 + *
5394 + * ALTERNATIVELY, this software may be distributed under the terms of the
5395 + * GNU General Public License ("GPL") as published by the Free Software
5396 + * Foundation, either version 2 of that License or (at your option) any
5397 + * later version.
5398 + *
5399 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
5400 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
5401 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
5402 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
5403 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
5404 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
5405 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
5406 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5407 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
5408 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5409 + */
5410 +
5411 +struct qbman_attr {
5412 + u32 dont_manipulate_directly[40];
5413 +};
5414 +
5415 +/* Buffer pool query commands */
5416 +int qbman_bp_query(struct qbman_swp *s, u32 bpid,
5417 + struct qbman_attr *a);
5418 +void qbman_bp_attr_get_bdi(struct qbman_attr *a, int *bdi, int *va, int *wae);
5419 +void qbman_bp_attr_get_swdet(struct qbman_attr *a, u32 *swdet);
5420 +void qbman_bp_attr_get_swdxt(struct qbman_attr *a, u32 *swdxt);
5421 +void qbman_bp_attr_get_hwdet(struct qbman_attr *a, u32 *hwdet);
5422 +void qbman_bp_attr_get_hwdxt(struct qbman_attr *a, u32 *hwdxt);
5423 +void qbman_bp_attr_get_swset(struct qbman_attr *a, u32 *swset);
5424 +void qbman_bp_attr_get_swsxt(struct qbman_attr *a, u32 *swsxt);
5425 +void qbman_bp_attr_get_vbpid(struct qbman_attr *a, u32 *vbpid);
5426 +void qbman_bp_attr_get_icid(struct qbman_attr *a, u32 *icid, int *pl);
5427 +void qbman_bp_attr_get_bpscn_addr(struct qbman_attr *a, u64 *bpscn_addr);
5428 +void qbman_bp_attr_get_bpscn_ctx(struct qbman_attr *a, u64 *bpscn_ctx);
5429 +void qbman_bp_attr_get_hw_targ(struct qbman_attr *a, u32 *hw_targ);
5430 +int qbman_bp_info_has_free_bufs(struct qbman_attr *a);
5431 +int qbman_bp_info_is_depleted(struct qbman_attr *a);
5432 +int qbman_bp_info_is_surplus(struct qbman_attr *a);
5433 +u32 qbman_bp_info_num_free_bufs(struct qbman_attr *a);
5434 +u32 qbman_bp_info_hdptr(struct qbman_attr *a);
5435 +u32 qbman_bp_info_sdcnt(struct qbman_attr *a);
5436 +u32 qbman_bp_info_hdcnt(struct qbman_attr *a);
5437 +u32 qbman_bp_info_sscnt(struct qbman_attr *a);
5438 +
5439 +/* FQ query function for programmable fields */
5440 +int qbman_fq_query(struct qbman_swp *s, u32 fqid,
5441 + struct qbman_attr *desc);
5442 +void qbman_fq_attr_get_fqctrl(struct qbman_attr *d, u32 *fqctrl);
5443 +void qbman_fq_attr_get_cgrid(struct qbman_attr *d, u32 *cgrid);
5444 +void qbman_fq_attr_get_destwq(struct qbman_attr *d, u32 *destwq);
5445 +void qbman_fq_attr_get_icscred(struct qbman_attr *d, u32 *icscred);
5446 +void qbman_fq_attr_get_tdthresh(struct qbman_attr *d, u32 *tdthresh);
5447 +void qbman_fq_attr_get_oa(struct qbman_attr *d,
5448 + int *oa_ics, int *oa_cgr, int32_t *oa_len);
5449 +void qbman_fq_attr_get_mctl(struct qbman_attr *d,
5450 + int *bdi, int *ff, int *va, int *ps);
5451 +void qbman_fq_attr_get_ctx(struct qbman_attr *d, u32 *hi, u32 *lo);
5452 +void qbman_fq_attr_get_icid(struct qbman_attr *d, u32 *icid, int *pl);
5453 +void qbman_fq_attr_get_vfqid(struct qbman_attr *d, u32 *vfqid);
5454 +void qbman_fq_attr_get_erfqid(struct qbman_attr *d, u32 *erfqid);
5455 +
5456 +/* FQ query command for non-programmable fields*/
5457 +enum qbman_fq_schedstate_e {
5458 + qbman_fq_schedstate_oos = 0,
5459 + qbman_fq_schedstate_retired,
5460 + qbman_fq_schedstate_tentatively_scheduled,
5461 + qbman_fq_schedstate_truly_scheduled,
5462 + qbman_fq_schedstate_parked,
5463 + qbman_fq_schedstate_held_active,
5464 +};
5465 +
5466 +int qbman_fq_query_state(struct qbman_swp *s, u32 fqid,
5467 + struct qbman_attr *state);
5468 +u32 qbman_fq_state_schedstate(const struct qbman_attr *state);
5469 +int qbman_fq_state_force_eligible(const struct qbman_attr *state);
5470 +int qbman_fq_state_xoff(const struct qbman_attr *state);
5471 +int qbman_fq_state_retirement_pending(const struct qbman_attr *state);
5472 +int qbman_fq_state_overflow_error(const struct qbman_attr *state);
5473 +u32 qbman_fq_state_frame_count(const struct qbman_attr *state);
5474 +u32 qbman_fq_state_byte_count(const struct qbman_attr *state);
5475 +
5476 +/* CGR query */
5477 +int qbman_cgr_query(struct qbman_swp *s, u32 cgid,
5478 + struct qbman_attr *attr);
5479 +void qbman_cgr_attr_get_ctl1(struct qbman_attr *d, int *cscn_wq_en_enter,
5480 + int *cscn_wq_en_exit, int *cscn_wq_icd);
5481 +void qbman_cgr_attr_get_mode(struct qbman_attr *d, u32 *mode,
5482 + int *rej_cnt_mode, int *cscn_bdi);
5483 +void qbman_cgr_attr_get_ctl2(struct qbman_attr *d, int *cscn_wr_en_enter,
5484 + int *cscn_wr_en_exit, int *cg_wr_ae,
5485 + int *cscn_dcp_en, int *cg_wr_va);
5486 +void qbman_cgr_attr_get_iwc(struct qbman_attr *d, int *i_cnt_wr_en,
5487 + u32 *i_cnt_wr_bnd);
5488 +void qbman_cgr_attr_get_tdc(struct qbman_attr *d, int *td_en);
5489 +void qbman_cgr_attr_get_cs_thres(struct qbman_attr *d, u32 *cs_thres);
5490 +void qbman_cgr_attr_get_cs_thres_x(struct qbman_attr *d,
5491 + u32 *cs_thres_x);
5492 +void qbman_cgr_attr_get_td_thres(struct qbman_attr *d, u32 *td_thres);
5493 +void qbman_cgr_attr_get_cscn_tdcp(struct qbman_attr *d, u32 *cscn_tdcp);
5494 +void qbman_cgr_attr_get_cscn_wqid(struct qbman_attr *d, u32 *cscn_wqid);
5495 +void qbman_cgr_attr_get_cscn_vcgid(struct qbman_attr *d,
5496 + u32 *cscn_vcgid);
5497 +void qbman_cgr_attr_get_cg_icid(struct qbman_attr *d, u32 *icid,
5498 + int *pl);
5499 +void qbman_cgr_attr_get_cg_wr_addr(struct qbman_attr *d,
5500 + u64 *cg_wr_addr);
5501 +void qbman_cgr_attr_get_cscn_ctx(struct qbman_attr *d, u64 *cscn_ctx);
5502 +void qbman_cgr_attr_wred_get_edp(struct qbman_attr *d, u32 idx,
5503 + int *edp);
5504 +void qbman_cgr_attr_wred_dp_decompose(u32 dp, u64 *minth,
5505 + u64 *maxth, u8 *maxp);
5506 +void qbman_cgr_attr_wred_get_parm_dp(struct qbman_attr *d, u32 idx,
5507 + u32 *dp);
5508 +
5509 +/* CGR/CCGR/CQ statistics query */
5510 +int qbman_cgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5511 + u64 *frame_cnt, u64 *byte_cnt);
5512 +int qbman_ccgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5513 + u64 *frame_cnt, u64 *byte_cnt);
5514 +int qbman_cq_dequeue_statistics(struct qbman_swp *s, u32 cgid, int clear,
5515 + u64 *frame_cnt, u64 *byte_cnt);
5516 diff --git a/drivers/staging/fsl-mc/bus/dpio/qbman_private.h b/drivers/staging/fsl-mc/bus/dpio/qbman_private.h
5517 new file mode 100644
5518 index 00000000..98a64be2
5519 --- /dev/null
5520 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman_private.h
5521 @@ -0,0 +1,171 @@
5522 +/* Copyright (C) 2014 Freescale Semiconductor, Inc.
5523 + *
5524 + * Redistribution and use in source and binary forms, with or without
5525 + * modification, are permitted provided that the following conditions are met:
5526 + * * Redistributions of source code must retain the above copyright
5527 + * notice, this list of conditions and the following disclaimer.
5528 + * * Redistributions in binary form must reproduce the above copyright
5529 + * notice, this list of conditions and the following disclaimer in the
5530 + * documentation and/or other materials provided with the distribution.
5531 + * * Neither the name of Freescale Semiconductor nor the
5532 + * names of its contributors may be used to endorse or promote products
5533 + * derived from this software without specific prior written permission.
5534 + *
5535 + *
5536 + * ALTERNATIVELY, this software may be distributed under the terms of the
5537 + * GNU General Public License ("GPL") as published by the Free Software
5538 + * Foundation, either version 2 of that License or (at your option) any
5539 + * later version.
5540 + *
5541 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
5542 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
5543 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
5544 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
5545 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
5546 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
5547 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
5548 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5549 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
5550 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5551 + */
5552 +
5553 +/* Perform extra checking */
5554 +#define QBMAN_CHECKING
5555 +
5556 +/* To maximise the amount of logic that is common between the Linux driver and
5557 + * other targets (such as the embedded MC firmware), we pivot here between the
5558 + * inclusion of two platform-specific headers.
5559 + *
5560 + * The first, qbman_sys_decl.h, includes any and all required system headers as
5561 + * well as providing any definitions for the purposes of compatibility. The
5562 + * second, qbman_sys.h, is where platform-specific routines go.
5563 + *
5564 + * The point of the split is that the platform-independent code (including this
5565 + * header) may depend on platform-specific declarations, yet other
5566 + * platform-specific routines may depend on platform-independent definitions.
5567 + */
5568 +
5569 +#define QMAN_REV_4000 0x04000000
5570 +#define QMAN_REV_4100 0x04010000
5571 +#define QMAN_REV_4101 0x04010001
5572 +
5573 +/* When things go wrong, it is a convenient trick to insert a few FOO()
5574 + * statements in the code to trace progress. TODO: remove this once we are
5575 + * hacking the code less actively.
5576 + */
5577 +#define FOO() fsl_os_print("FOO: %s:%d\n", __FILE__, __LINE__)
5578 +
5579 +/* Any time there is a register interface which we poll on, this provides a
5580 + * "break after x iterations" scheme for it. It's handy for debugging, eg.
5581 + * where you don't want millions of lines of log output from a polling loop
5582 + * that won't, because such things tend to drown out the earlier log output
5583 + * that might explain what caused the problem. (NB: put ";" after each macro!)
5584 + * TODO: we should probably remove this once we're done sanitising the
5585 + * simulator...
5586 + */
5587 +#define DBG_POLL_START(loopvar) (loopvar = 1000)
5588 +#define DBG_POLL_CHECK(loopvar) \
5589 + do {if (!((loopvar)--)) WARN_ON(1); } while (0)
5590 +
5591 +/* For CCSR or portal-CINH registers that contain fields at arbitrary offsets
5592 + * and widths, these macro-generated encode/decode/isolate/remove inlines can
5593 + * be used.
5594 + *
5595 + * Eg. to "d"ecode a 14-bit field out of a register (into a "u16" type),
5596 + * where the field is located 3 bits "up" from the least-significant bit of the
5597 + * register (ie. the field location within the 32-bit register corresponds to a
5598 + * mask of 0x0001fff8), you would do;
5599 + * u16 field = d32_u16(3, 14, reg_value);
5600 + *
5601 + * Or to "e"ncode a 1-bit boolean value (input type is "int", zero is FALSE,
5602 + * non-zero is TRUE, so must convert all non-zero inputs to 1, hence the "!!"
5603 + * operator) into a register at bit location 0x00080000 (19 bits "in" from the
5604 + * LS bit), do;
5605 + * reg_value |= e32_int(19, 1, !!field);
5606 + *
5607 + * If you wish to read-modify-write a register, such that you leave the 14-bit
5608 + * field as-is but have all other fields set to zero, then "i"solate the 14-bit
5609 + * value using;
5610 + * reg_value = i32_u16(3, 14, reg_value);
5611 + *
5612 + * Alternatively, you could "r"emove the 1-bit boolean field (setting it to
5613 + * zero) but leaving all other fields as-is;
5614 + * reg_val = r32_int(19, 1, reg_value);
5615 + *
5616 + */
5617 +#define MAKE_MASK32(width) (width == 32 ? 0xffffffff : \
5618 + (u32)((1 << width) - 1))
5619 +#define DECLARE_CODEC32(t) \
5620 +static inline u32 e32_##t(u32 lsoffset, u32 width, t val) \
5621 +{ \
5622 + WARN_ON(width > (sizeof(t) * 8)); \
5623 + return ((u32)val & MAKE_MASK32(width)) << lsoffset; \
5624 +} \
5625 +static inline t d32_##t(u32 lsoffset, u32 width, u32 val) \
5626 +{ \
5627 + WARN_ON(width > (sizeof(t) * 8)); \
5628 + return (t)((val >> lsoffset) & MAKE_MASK32(width)); \
5629 +} \
5630 +static inline u32 i32_##t(u32 lsoffset, u32 width, \
5631 + u32 val) \
5632 +{ \
5633 + WARN_ON(width > (sizeof(t) * 8)); \
5634 + return e32_##t(lsoffset, width, d32_##t(lsoffset, width, val)); \
5635 +} \
5636 +static inline u32 r32_##t(u32 lsoffset, u32 width, \
5637 + u32 val) \
5638 +{ \
5639 + WARN_ON(width > (sizeof(t) * 8)); \
5640 + return ~(MAKE_MASK32(width) << lsoffset) & val; \
5641 +}
5642 +DECLARE_CODEC32(u32)
5643 +DECLARE_CODEC32(u16)
5644 +DECLARE_CODEC32(u8)
5645 +DECLARE_CODEC32(int)
5646 +
5647 + /*********************/
5648 + /* Debugging assists */
5649 + /*********************/
5650 +
5651 +static inline void __hexdump(unsigned long start, unsigned long end,
5652 + unsigned long p, size_t sz,
5653 + const unsigned char *c)
5654 +{
5655 + while (start < end) {
5656 + unsigned int pos = 0;
5657 + char buf[64];
5658 + int nl = 0;
5659 +
5660 + pos += sprintf(buf + pos, "%08lx: ", start);
5661 + do {
5662 + if ((start < p) || (start >= (p + sz)))
5663 + pos += sprintf(buf + pos, "..");
5664 + else
5665 + pos += sprintf(buf + pos, "%02x", *(c++));
5666 + if (!(++start & 15)) {
5667 + buf[pos++] = '\n';
5668 + nl = 1;
5669 + } else {
5670 + nl = 0;
5671 + if (!(start & 1))
5672 + buf[pos++] = ' ';
5673 + if (!(start & 3))
5674 + buf[pos++] = ' ';
5675 + }
5676 + } while (start & 15);
5677 + if (!nl)
5678 + buf[pos++] = '\n';
5679 + buf[pos] = '\0';
5680 + pr_info("%s", buf);
5681 + }
5682 +}
5683 +
5684 +static inline void hexdump(const void *ptr, size_t sz)
5685 +{
5686 + unsigned long p = (unsigned long)ptr;
5687 + unsigned long start = p & ~15ul;
5688 + unsigned long end = (p + sz + 15) & ~15ul;
5689 + const unsigned char *c = ptr;
5690 +
5691 + __hexdump(start, end, p, sz, c);
5692 +}
5693 diff --git a/drivers/staging/fsl-mc/bus/dpmcp-cmd.h b/drivers/staging/fsl-mc/bus/dpmcp-cmd.h
5694 index d098a6d8..384a13d0 100644
5695 --- a/drivers/staging/fsl-mc/bus/dpmcp-cmd.h
5696 +++ b/drivers/staging/fsl-mc/bus/dpmcp-cmd.h
5697 @@ -1,4 +1,5 @@
5698 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
5699 +/*
5700 + * Copyright 2013-2016 Freescale Semiconductor Inc.
5701 *
5702 * Redistribution and use in source and binary forms, with or without
5703 * modification, are permitted provided that the following conditions are met:
5704 @@ -11,7 +12,6 @@
5705 * names of any contributors may be used to endorse or promote products
5706 * derived from this software without specific prior written permission.
5707 *
5708 - *
5709 * ALTERNATIVELY, this software may be distributed under the terms of the
5710 * GNU General Public License ("GPL") as published by the Free Software
5711 * Foundation, either version 2 of that License or (at your option) any
5712 @@ -33,108 +33,24 @@
5713 #define _FSL_DPMCP_CMD_H
5714
5715 /* Minimal supported DPMCP Version */
5716 -#define DPMCP_MIN_VER_MAJOR 3
5717 -#define DPMCP_MIN_VER_MINOR 0
5718 +#define DPMCP_MIN_VER_MAJOR 3
5719 +#define DPMCP_MIN_VER_MINOR 0
5720
5721 -/* Command IDs */
5722 -#define DPMCP_CMDID_CLOSE 0x800
5723 -#define DPMCP_CMDID_OPEN 0x80b
5724 -#define DPMCP_CMDID_CREATE 0x90b
5725 -#define DPMCP_CMDID_DESTROY 0x900
5726 +/* Command versioning */
5727 +#define DPMCP_CMD_BASE_VERSION 1
5728 +#define DPMCP_CMD_ID_OFFSET 4
5729
5730 -#define DPMCP_CMDID_GET_ATTR 0x004
5731 -#define DPMCP_CMDID_RESET 0x005
5732 +#define DPMCP_CMD(id) ((id << DPMCP_CMD_ID_OFFSET) | DPMCP_CMD_BASE_VERSION)
5733 +
5734 +/* Command IDs */
5735 +#define DPMCP_CMDID_CLOSE DPMCP_CMD(0x800)
5736 +#define DPMCP_CMDID_OPEN DPMCP_CMD(0x80b)
5737 +#define DPMCP_CMDID_GET_API_VERSION DPMCP_CMD(0xa0b)
5738
5739 -#define DPMCP_CMDID_SET_IRQ 0x010
5740 -#define DPMCP_CMDID_GET_IRQ 0x011
5741 -#define DPMCP_CMDID_SET_IRQ_ENABLE 0x012
5742 -#define DPMCP_CMDID_GET_IRQ_ENABLE 0x013
5743 -#define DPMCP_CMDID_SET_IRQ_MASK 0x014
5744 -#define DPMCP_CMDID_GET_IRQ_MASK 0x015
5745 -#define DPMCP_CMDID_GET_IRQ_STATUS 0x016
5746 +#define DPMCP_CMDID_RESET DPMCP_CMD(0x005)
5747
5748 struct dpmcp_cmd_open {
5749 __le32 dpmcp_id;
5750 };
5751
5752 -struct dpmcp_cmd_create {
5753 - __le32 portal_id;
5754 -};
5755 -
5756 -struct dpmcp_cmd_set_irq {
5757 - /* cmd word 0 */
5758 - u8 irq_index;
5759 - u8 pad[3];
5760 - __le32 irq_val;
5761 - /* cmd word 1 */
5762 - __le64 irq_addr;
5763 - /* cmd word 2 */
5764 - __le32 irq_num;
5765 -};
5766 -
5767 -struct dpmcp_cmd_get_irq {
5768 - __le32 pad;
5769 - u8 irq_index;
5770 -};
5771 -
5772 -struct dpmcp_rsp_get_irq {
5773 - /* cmd word 0 */
5774 - __le32 irq_val;
5775 - __le32 pad;
5776 - /* cmd word 1 */
5777 - __le64 irq_paddr;
5778 - /* cmd word 2 */
5779 - __le32 irq_num;
5780 - __le32 type;
5781 -};
5782 -
5783 -#define DPMCP_ENABLE 0x1
5784 -
5785 -struct dpmcp_cmd_set_irq_enable {
5786 - u8 enable;
5787 - u8 pad[3];
5788 - u8 irq_index;
5789 -};
5790 -
5791 -struct dpmcp_cmd_get_irq_enable {
5792 - __le32 pad;
5793 - u8 irq_index;
5794 -};
5795 -
5796 -struct dpmcp_rsp_get_irq_enable {
5797 - u8 enabled;
5798 -};
5799 -
5800 -struct dpmcp_cmd_set_irq_mask {
5801 - __le32 mask;
5802 - u8 irq_index;
5803 -};
5804 -
5805 -struct dpmcp_cmd_get_irq_mask {
5806 - __le32 pad;
5807 - u8 irq_index;
5808 -};
5809 -
5810 -struct dpmcp_rsp_get_irq_mask {
5811 - __le32 mask;
5812 -};
5813 -
5814 -struct dpmcp_cmd_get_irq_status {
5815 - __le32 status;
5816 - u8 irq_index;
5817 -};
5818 -
5819 -struct dpmcp_rsp_get_irq_status {
5820 - __le32 status;
5821 -};
5822 -
5823 -struct dpmcp_rsp_get_attributes {
5824 - /* response word 0 */
5825 - __le32 pad;
5826 - __le32 id;
5827 - /* response word 1 */
5828 - __le16 version_major;
5829 - __le16 version_minor;
5830 -};
5831 -
5832 #endif /* _FSL_DPMCP_CMD_H */
5833 diff --git a/drivers/staging/fsl-mc/bus/dpmcp.c b/drivers/staging/fsl-mc/bus/dpmcp.c
5834 index 55766f78..ad4c8b43 100644
5835 --- a/drivers/staging/fsl-mc/bus/dpmcp.c
5836 +++ b/drivers/staging/fsl-mc/bus/dpmcp.c
5837 @@ -1,4 +1,5 @@
5838 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
5839 +/*
5840 + * Copyright 2013-2016 Freescale Semiconductor Inc.
5841 *
5842 * Redistribution and use in source and binary forms, with or without
5843 * modification, are permitted provided that the following conditions are met:
5844 @@ -11,7 +12,6 @@
5845 * names of any contributors may be used to endorse or promote products
5846 * derived from this software without specific prior written permission.
5847 *
5848 - *
5849 * ALTERNATIVELY, this software may be distributed under the terms of the
5850 * GNU General Public License ("GPL") as published by the Free Software
5851 * Foundation, either version 2 of that License or (at your option) any
5852 @@ -103,76 +103,6 @@ int dpmcp_close(struct fsl_mc_io *mc_io,
5853 return mc_send_command(mc_io, &cmd);
5854 }
5855
5856 -/**
5857 - * dpmcp_create() - Create the DPMCP object.
5858 - * @mc_io: Pointer to MC portal's I/O object
5859 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5860 - * @cfg: Configuration structure
5861 - * @token: Returned token; use in subsequent API calls
5862 - *
5863 - * Create the DPMCP object, allocate required resources and
5864 - * perform required initialization.
5865 - *
5866 - * The object can be created either by declaring it in the
5867 - * DPL file, or by calling this function.
5868 - * This function returns a unique authentication token,
5869 - * associated with the specific object ID and the specific MC
5870 - * portal; this token must be used in all subsequent calls to
5871 - * this specific object. For objects that are created using the
5872 - * DPL file, call dpmcp_open function to get an authentication
5873 - * token first.
5874 - *
5875 - * Return: '0' on Success; Error code otherwise.
5876 - */
5877 -int dpmcp_create(struct fsl_mc_io *mc_io,
5878 - u32 cmd_flags,
5879 - const struct dpmcp_cfg *cfg,
5880 - u16 *token)
5881 -{
5882 - struct mc_command cmd = { 0 };
5883 - struct dpmcp_cmd_create *cmd_params;
5884 -
5885 - int err;
5886 -
5887 - /* prepare command */
5888 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_CREATE,
5889 - cmd_flags, 0);
5890 - cmd_params = (struct dpmcp_cmd_create *)cmd.params;
5891 - cmd_params->portal_id = cpu_to_le32(cfg->portal_id);
5892 -
5893 - /* send command to mc*/
5894 - err = mc_send_command(mc_io, &cmd);
5895 - if (err)
5896 - return err;
5897 -
5898 - /* retrieve response parameters */
5899 - *token = mc_cmd_hdr_read_token(&cmd);
5900 -
5901 - return 0;
5902 -}
5903 -
5904 -/**
5905 - * dpmcp_destroy() - Destroy the DPMCP object and release all its resources.
5906 - * @mc_io: Pointer to MC portal's I/O object
5907 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5908 - * @token: Token of DPMCP object
5909 - *
5910 - * Return: '0' on Success; error code otherwise.
5911 - */
5912 -int dpmcp_destroy(struct fsl_mc_io *mc_io,
5913 - u32 cmd_flags,
5914 - u16 token)
5915 -{
5916 - struct mc_command cmd = { 0 };
5917 -
5918 - /* prepare command */
5919 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_DESTROY,
5920 - cmd_flags, token);
5921 -
5922 - /* send command to mc*/
5923 - return mc_send_command(mc_io, &cmd);
5924 -}
5925 -
5926 /**
5927 * dpmcp_reset() - Reset the DPMCP, returns the object to initial state.
5928 * @mc_io: Pointer to MC portal's I/O object
5929 @@ -196,309 +126,33 @@ int dpmcp_reset(struct fsl_mc_io *mc_io,
5930 }
5931
5932 /**
5933 - * dpmcp_set_irq() - Set IRQ information for the DPMCP to trigger an interrupt.
5934 - * @mc_io: Pointer to MC portal's I/O object
5935 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5936 - * @token: Token of DPMCP object
5937 - * @irq_index: Identifies the interrupt index to configure
5938 - * @irq_cfg: IRQ configuration
5939 - *
5940 - * Return: '0' on Success; Error code otherwise.
5941 - */
5942 -int dpmcp_set_irq(struct fsl_mc_io *mc_io,
5943 - u32 cmd_flags,
5944 - u16 token,
5945 - u8 irq_index,
5946 - struct dpmcp_irq_cfg *irq_cfg)
5947 -{
5948 - struct mc_command cmd = { 0 };
5949 - struct dpmcp_cmd_set_irq *cmd_params;
5950 -
5951 - /* prepare command */
5952 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ,
5953 - cmd_flags, token);
5954 - cmd_params = (struct dpmcp_cmd_set_irq *)cmd.params;
5955 - cmd_params->irq_index = irq_index;
5956 - cmd_params->irq_val = cpu_to_le32(irq_cfg->val);
5957 - cmd_params->irq_addr = cpu_to_le64(irq_cfg->paddr);
5958 - cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num);
5959 -
5960 - /* send command to mc*/
5961 - return mc_send_command(mc_io, &cmd);
5962 -}
5963 -
5964 -/**
5965 - * dpmcp_get_irq() - Get IRQ information from the DPMCP.
5966 - * @mc_io: Pointer to MC portal's I/O object
5967 + * dpmcp_get_api_version - Get Data Path Management Command Portal API version
5968 + * @mc_io: Pointer to Mc portal's I/O object
5969 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5970 - * @token: Token of DPMCP object
5971 - * @irq_index: The interrupt index to configure
5972 - * @type: Interrupt type: 0 represents message interrupt
5973 - * type (both irq_addr and irq_val are valid)
5974 - * @irq_cfg: IRQ attributes
5975 + * @major_ver: Major version of Data Path Management Command Portal API
5976 + * @minor_ver: Minor version of Data Path Management Command Portal API
5977 *
5978 * Return: '0' on Success; Error code otherwise.
5979 */
5980 -int dpmcp_get_irq(struct fsl_mc_io *mc_io,
5981 - u32 cmd_flags,
5982 - u16 token,
5983 - u8 irq_index,
5984 - int *type,
5985 - struct dpmcp_irq_cfg *irq_cfg)
5986 +int dpmcp_get_api_version(struct fsl_mc_io *mc_io,
5987 + u32 cmd_flags,
5988 + u16 *major_ver,
5989 + u16 *minor_ver)
5990 {
5991 struct mc_command cmd = { 0 };
5992 - struct dpmcp_cmd_get_irq *cmd_params;
5993 - struct dpmcp_rsp_get_irq *rsp_params;
5994 int err;
5995
5996 /* prepare command */
5997 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ,
5998 - cmd_flags, token);
5999 - cmd_params = (struct dpmcp_cmd_get_irq *)cmd.params;
6000 - cmd_params->irq_index = irq_index;
6001 -
6002 - /* send command to mc*/
6003 - err = mc_send_command(mc_io, &cmd);
6004 - if (err)
6005 - return err;
6006 -
6007 - /* retrieve response parameters */
6008 - rsp_params = (struct dpmcp_rsp_get_irq *)cmd.params;
6009 - irq_cfg->val = le32_to_cpu(rsp_params->irq_val);
6010 - irq_cfg->paddr = le64_to_cpu(rsp_params->irq_paddr);
6011 - irq_cfg->irq_num = le32_to_cpu(rsp_params->irq_num);
6012 - *type = le32_to_cpu(rsp_params->type);
6013 - return 0;
6014 -}
6015 -
6016 -/**
6017 - * dpmcp_set_irq_enable() - Set overall interrupt state.
6018 - * @mc_io: Pointer to MC portal's I/O object
6019 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6020 - * @token: Token of DPMCP object
6021 - * @irq_index: The interrupt index to configure
6022 - * @en: Interrupt state - enable = 1, disable = 0
6023 - *
6024 - * Allows GPP software to control when interrupts are generated.
6025 - * Each interrupt can have up to 32 causes. The enable/disable control's the
6026 - * overall interrupt state. if the interrupt is disabled no causes will cause
6027 - * an interrupt.
6028 - *
6029 - * Return: '0' on Success; Error code otherwise.
6030 - */
6031 -int dpmcp_set_irq_enable(struct fsl_mc_io *mc_io,
6032 - u32 cmd_flags,
6033 - u16 token,
6034 - u8 irq_index,
6035 - u8 en)
6036 -{
6037 - struct mc_command cmd = { 0 };
6038 - struct dpmcp_cmd_set_irq_enable *cmd_params;
6039 -
6040 - /* prepare command */
6041 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ_ENABLE,
6042 - cmd_flags, token);
6043 - cmd_params = (struct dpmcp_cmd_set_irq_enable *)cmd.params;
6044 - cmd_params->enable = en & DPMCP_ENABLE;
6045 - cmd_params->irq_index = irq_index;
6046 -
6047 - /* send command to mc*/
6048 - return mc_send_command(mc_io, &cmd);
6049 -}
6050 -
6051 -/**
6052 - * dpmcp_get_irq_enable() - Get overall interrupt state
6053 - * @mc_io: Pointer to MC portal's I/O object
6054 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6055 - * @token: Token of DPMCP object
6056 - * @irq_index: The interrupt index to configure
6057 - * @en: Returned interrupt state - enable = 1, disable = 0
6058 - *
6059 - * Return: '0' on Success; Error code otherwise.
6060 - */
6061 -int dpmcp_get_irq_enable(struct fsl_mc_io *mc_io,
6062 - u32 cmd_flags,
6063 - u16 token,
6064 - u8 irq_index,
6065 - u8 *en)
6066 -{
6067 - struct mc_command cmd = { 0 };
6068 - struct dpmcp_cmd_get_irq_enable *cmd_params;
6069 - struct dpmcp_rsp_get_irq_enable *rsp_params;
6070 - int err;
6071 -
6072 - /* prepare command */
6073 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_ENABLE,
6074 - cmd_flags, token);
6075 - cmd_params = (struct dpmcp_cmd_get_irq_enable *)cmd.params;
6076 - cmd_params->irq_index = irq_index;
6077 -
6078 - /* send command to mc*/
6079 - err = mc_send_command(mc_io, &cmd);
6080 - if (err)
6081 - return err;
6082 -
6083 - /* retrieve response parameters */
6084 - rsp_params = (struct dpmcp_rsp_get_irq_enable *)cmd.params;
6085 - *en = rsp_params->enabled & DPMCP_ENABLE;
6086 - return 0;
6087 -}
6088 -
6089 -/**
6090 - * dpmcp_set_irq_mask() - Set interrupt mask.
6091 - * @mc_io: Pointer to MC portal's I/O object
6092 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6093 - * @token: Token of DPMCP object
6094 - * @irq_index: The interrupt index to configure
6095 - * @mask: Event mask to trigger interrupt;
6096 - * each bit:
6097 - * 0 = ignore event
6098 - * 1 = consider event for asserting IRQ
6099 - *
6100 - * Every interrupt can have up to 32 causes and the interrupt model supports
6101 - * masking/unmasking each cause independently
6102 - *
6103 - * Return: '0' on Success; Error code otherwise.
6104 - */
6105 -int dpmcp_set_irq_mask(struct fsl_mc_io *mc_io,
6106 - u32 cmd_flags,
6107 - u16 token,
6108 - u8 irq_index,
6109 - u32 mask)
6110 -{
6111 - struct mc_command cmd = { 0 };
6112 - struct dpmcp_cmd_set_irq_mask *cmd_params;
6113 -
6114 - /* prepare command */
6115 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ_MASK,
6116 - cmd_flags, token);
6117 - cmd_params = (struct dpmcp_cmd_set_irq_mask *)cmd.params;
6118 - cmd_params->mask = cpu_to_le32(mask);
6119 - cmd_params->irq_index = irq_index;
6120 -
6121 - /* send command to mc*/
6122 - return mc_send_command(mc_io, &cmd);
6123 -}
6124 -
6125 -/**
6126 - * dpmcp_get_irq_mask() - Get interrupt mask.
6127 - * @mc_io: Pointer to MC portal's I/O object
6128 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6129 - * @token: Token of DPMCP object
6130 - * @irq_index: The interrupt index to configure
6131 - * @mask: Returned event mask to trigger interrupt
6132 - *
6133 - * Every interrupt can have up to 32 causes and the interrupt model supports
6134 - * masking/unmasking each cause independently
6135 - *
6136 - * Return: '0' on Success; Error code otherwise.
6137 - */
6138 -int dpmcp_get_irq_mask(struct fsl_mc_io *mc_io,
6139 - u32 cmd_flags,
6140 - u16 token,
6141 - u8 irq_index,
6142 - u32 *mask)
6143 -{
6144 - struct mc_command cmd = { 0 };
6145 - struct dpmcp_cmd_get_irq_mask *cmd_params;
6146 - struct dpmcp_rsp_get_irq_mask *rsp_params;
6147 -
6148 - int err;
6149 -
6150 - /* prepare command */
6151 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_MASK,
6152 - cmd_flags, token);
6153 - cmd_params = (struct dpmcp_cmd_get_irq_mask *)cmd.params;
6154 - cmd_params->irq_index = irq_index;
6155 -
6156 - /* send command to mc*/
6157 - err = mc_send_command(mc_io, &cmd);
6158 - if (err)
6159 - return err;
6160 -
6161 - /* retrieve response parameters */
6162 - rsp_params = (struct dpmcp_rsp_get_irq_mask *)cmd.params;
6163 - *mask = le32_to_cpu(rsp_params->mask);
6164 -
6165 - return 0;
6166 -}
6167 -
6168 -/**
6169 - * dpmcp_get_irq_status() - Get the current status of any pending interrupts.
6170 - *
6171 - * @mc_io: Pointer to MC portal's I/O object
6172 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6173 - * @token: Token of DPMCP object
6174 - * @irq_index: The interrupt index to configure
6175 - * @status: Returned interrupts status - one bit per cause:
6176 - * 0 = no interrupt pending
6177 - * 1 = interrupt pending
6178 - *
6179 - * Return: '0' on Success; Error code otherwise.
6180 - */
6181 -int dpmcp_get_irq_status(struct fsl_mc_io *mc_io,
6182 - u32 cmd_flags,
6183 - u16 token,
6184 - u8 irq_index,
6185 - u32 *status)
6186 -{
6187 - struct mc_command cmd = { 0 };
6188 - struct dpmcp_cmd_get_irq_status *cmd_params;
6189 - struct dpmcp_rsp_get_irq_status *rsp_params;
6190 - int err;
6191 -
6192 - /* prepare command */
6193 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_STATUS,
6194 - cmd_flags, token);
6195 - cmd_params = (struct dpmcp_cmd_get_irq_status *)cmd.params;
6196 - cmd_params->status = cpu_to_le32(*status);
6197 - cmd_params->irq_index = irq_index;
6198 -
6199 - /* send command to mc*/
6200 - err = mc_send_command(mc_io, &cmd);
6201 - if (err)
6202 - return err;
6203 -
6204 - /* retrieve response parameters */
6205 - rsp_params = (struct dpmcp_rsp_get_irq_status *)cmd.params;
6206 - *status = le32_to_cpu(rsp_params->status);
6207 -
6208 - return 0;
6209 -}
6210 -
6211 -/**
6212 - * dpmcp_get_attributes - Retrieve DPMCP attributes.
6213 - *
6214 - * @mc_io: Pointer to MC portal's I/O object
6215 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6216 - * @token: Token of DPMCP object
6217 - * @attr: Returned object's attributes
6218 - *
6219 - * Return: '0' on Success; Error code otherwise.
6220 - */
6221 -int dpmcp_get_attributes(struct fsl_mc_io *mc_io,
6222 - u32 cmd_flags,
6223 - u16 token,
6224 - struct dpmcp_attr *attr)
6225 -{
6226 - struct mc_command cmd = { 0 };
6227 - struct dpmcp_rsp_get_attributes *rsp_params;
6228 - int err;
6229 -
6230 - /* prepare command */
6231 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_ATTR,
6232 - cmd_flags, token);
6233 + cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_API_VERSION,
6234 + cmd_flags, 0);
6235
6236 - /* send command to mc*/
6237 + /* send command to mc */
6238 err = mc_send_command(mc_io, &cmd);
6239 if (err)
6240 return err;
6241
6242 /* retrieve response parameters */
6243 - rsp_params = (struct dpmcp_rsp_get_attributes *)cmd.params;
6244 - attr->id = le32_to_cpu(rsp_params->id);
6245 - attr->version.major = le16_to_cpu(rsp_params->version_major);
6246 - attr->version.minor = le16_to_cpu(rsp_params->version_minor);
6247 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
6248
6249 return 0;
6250 }
6251 diff --git a/drivers/staging/fsl-mc/bus/dpmcp.h b/drivers/staging/fsl-mc/bus/dpmcp.h
6252 index fe79d4d9..f616031e 100644
6253 --- a/drivers/staging/fsl-mc/bus/dpmcp.h
6254 +++ b/drivers/staging/fsl-mc/bus/dpmcp.h
6255 @@ -1,4 +1,5 @@
6256 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
6257 +/*
6258 + * Copyright 2013-2016 Freescale Semiconductor Inc.
6259 *
6260 * Redistribution and use in source and binary forms, with or without
6261 * modification, are permitted provided that the following conditions are met:
6262 @@ -11,7 +12,6 @@
6263 * names of any contributors may be used to endorse or promote products
6264 * derived from this software without specific prior written permission.
6265 *
6266 - *
6267 * ALTERNATIVELY, this software may be distributed under the terms of the
6268 * GNU General Public License ("GPL") as published by the Free Software
6269 * Foundation, either version 2 of that License or (at your option) any
6270 @@ -32,128 +32,29 @@
6271 #ifndef __FSL_DPMCP_H
6272 #define __FSL_DPMCP_H
6273
6274 -/* Data Path Management Command Portal API
6275 +/*
6276 + * Data Path Management Command Portal API
6277 * Contains initialization APIs and runtime control APIs for DPMCP
6278 */
6279
6280 struct fsl_mc_io;
6281
6282 int dpmcp_open(struct fsl_mc_io *mc_io,
6283 - uint32_t cmd_flags,
6284 + u32 cmd_flags,
6285 int dpmcp_id,
6286 - uint16_t *token);
6287 -
6288 -/* Get portal ID from pool */
6289 -#define DPMCP_GET_PORTAL_ID_FROM_POOL (-1)
6290 + u16 *token);
6291
6292 int dpmcp_close(struct fsl_mc_io *mc_io,
6293 - uint32_t cmd_flags,
6294 - uint16_t token);
6295 -
6296 -/**
6297 - * struct dpmcp_cfg - Structure representing DPMCP configuration
6298 - * @portal_id: Portal ID; 'DPMCP_GET_PORTAL_ID_FROM_POOL' to get the portal ID
6299 - * from pool
6300 - */
6301 -struct dpmcp_cfg {
6302 - int portal_id;
6303 -};
6304 -
6305 -int dpmcp_create(struct fsl_mc_io *mc_io,
6306 - uint32_t cmd_flags,
6307 - const struct dpmcp_cfg *cfg,
6308 - uint16_t *token);
6309 + u32 cmd_flags,
6310 + u16 token);
6311
6312 -int dpmcp_destroy(struct fsl_mc_io *mc_io,
6313 - uint32_t cmd_flags,
6314 - uint16_t token);
6315 +int dpmcp_get_api_version(struct fsl_mc_io *mc_io,
6316 + u32 cmd_flags,
6317 + u16 *major_ver,
6318 + u16 *minor_ver);
6319
6320 int dpmcp_reset(struct fsl_mc_io *mc_io,
6321 - uint32_t cmd_flags,
6322 - uint16_t token);
6323 -
6324 -/* IRQ */
6325 -/* IRQ Index */
6326 -#define DPMCP_IRQ_INDEX 0
6327 -/* irq event - Indicates that the link state changed */
6328 -#define DPMCP_IRQ_EVENT_CMD_DONE 0x00000001
6329 -
6330 -/**
6331 - * struct dpmcp_irq_cfg - IRQ configuration
6332 - * @paddr: Address that must be written to signal a message-based interrupt
6333 - * @val: Value to write into irq_addr address
6334 - * @irq_num: A user defined number associated with this IRQ
6335 - */
6336 -struct dpmcp_irq_cfg {
6337 - uint64_t paddr;
6338 - uint32_t val;
6339 - int irq_num;
6340 -};
6341 -
6342 -int dpmcp_set_irq(struct fsl_mc_io *mc_io,
6343 - uint32_t cmd_flags,
6344 - uint16_t token,
6345 - uint8_t irq_index,
6346 - struct dpmcp_irq_cfg *irq_cfg);
6347 -
6348 -int dpmcp_get_irq(struct fsl_mc_io *mc_io,
6349 - uint32_t cmd_flags,
6350 - uint16_t token,
6351 - uint8_t irq_index,
6352 - int *type,
6353 - struct dpmcp_irq_cfg *irq_cfg);
6354 -
6355 -int dpmcp_set_irq_enable(struct fsl_mc_io *mc_io,
6356 - uint32_t cmd_flags,
6357 - uint16_t token,
6358 - uint8_t irq_index,
6359 - uint8_t en);
6360 -
6361 -int dpmcp_get_irq_enable(struct fsl_mc_io *mc_io,
6362 - uint32_t cmd_flags,
6363 - uint16_t token,
6364 - uint8_t irq_index,
6365 - uint8_t *en);
6366 -
6367 -int dpmcp_set_irq_mask(struct fsl_mc_io *mc_io,
6368 - uint32_t cmd_flags,
6369 - uint16_t token,
6370 - uint8_t irq_index,
6371 - uint32_t mask);
6372 -
6373 -int dpmcp_get_irq_mask(struct fsl_mc_io *mc_io,
6374 - uint32_t cmd_flags,
6375 - uint16_t token,
6376 - uint8_t irq_index,
6377 - uint32_t *mask);
6378 -
6379 -int dpmcp_get_irq_status(struct fsl_mc_io *mc_io,
6380 - uint32_t cmd_flags,
6381 - uint16_t token,
6382 - uint8_t irq_index,
6383 - uint32_t *status);
6384 -
6385 -/**
6386 - * struct dpmcp_attr - Structure representing DPMCP attributes
6387 - * @id: DPMCP object ID
6388 - * @version: DPMCP version
6389 - */
6390 -struct dpmcp_attr {
6391 - int id;
6392 - /**
6393 - * struct version - Structure representing DPMCP version
6394 - * @major: DPMCP major version
6395 - * @minor: DPMCP minor version
6396 - */
6397 - struct {
6398 - uint16_t major;
6399 - uint16_t minor;
6400 - } version;
6401 -};
6402 -
6403 -int dpmcp_get_attributes(struct fsl_mc_io *mc_io,
6404 - uint32_t cmd_flags,
6405 - uint16_t token,
6406 - struct dpmcp_attr *attr);
6407 + u32 cmd_flags,
6408 + u16 token);
6409
6410 #endif /* __FSL_DPMCP_H */
6411 diff --git a/drivers/staging/fsl-mc/bus/dpmng-cmd.h b/drivers/staging/fsl-mc/bus/dpmng-cmd.h
6412 index a7b77d58..cdddfb80 100644
6413 --- a/drivers/staging/fsl-mc/bus/dpmng-cmd.h
6414 +++ b/drivers/staging/fsl-mc/bus/dpmng-cmd.h
6415 @@ -12,7 +12,6 @@
6416 * names of any contributors may be used to endorse or promote products
6417 * derived from this software without specific prior written permission.
6418 *
6419 - *
6420 * ALTERNATIVELY, this software may be distributed under the terms of the
6421 * GNU General Public License ("GPL") as published by the Free Software
6422 * Foundation, either version 2 of that License or (at your option) any
6423 @@ -41,13 +40,14 @@
6424 #ifndef __FSL_DPMNG_CMD_H
6425 #define __FSL_DPMNG_CMD_H
6426
6427 -/* Command IDs */
6428 -#define DPMNG_CMDID_GET_CONT_ID 0x830
6429 -#define DPMNG_CMDID_GET_VERSION 0x831
6430 +/* Command versioning */
6431 +#define DPMNG_CMD_BASE_VERSION 1
6432 +#define DPMNG_CMD_ID_OFFSET 4
6433
6434 -struct dpmng_rsp_get_container_id {
6435 - __le32 container_id;
6436 -};
6437 +#define DPMNG_CMD(id) ((id << DPMNG_CMD_ID_OFFSET) | DPMNG_CMD_BASE_VERSION)
6438 +
6439 +/* Command IDs */
6440 +#define DPMNG_CMDID_GET_VERSION DPMNG_CMD(0x831)
6441
6442 struct dpmng_rsp_get_version {
6443 __le32 revision;
6444 diff --git a/drivers/staging/fsl-mc/bus/dpmng.c b/drivers/staging/fsl-mc/bus/dpmng.c
6445 index 96b1d677..ad5d5bbe 100644
6446 --- a/drivers/staging/fsl-mc/bus/dpmng.c
6447 +++ b/drivers/staging/fsl-mc/bus/dpmng.c
6448 @@ -1,4 +1,5 @@
6449 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
6450 +/*
6451 + * Copyright 2013-2016 Freescale Semiconductor Inc.
6452 *
6453 * Redistribution and use in source and binary forms, with or without
6454 * modification, are permitted provided that the following conditions are met:
6455 @@ -11,7 +12,6 @@
6456 * names of any contributors may be used to endorse or promote products
6457 * derived from this software without specific prior written permission.
6458 *
6459 - *
6460 * ALTERNATIVELY, this software may be distributed under the terms of the
6461 * GNU General Public License ("GPL") as published by the Free Software
6462 * Foundation, either version 2 of that License or (at your option) any
6463 @@ -72,36 +72,3 @@ int mc_get_version(struct fsl_mc_io *mc_io,
6464 }
6465 EXPORT_SYMBOL(mc_get_version);
6466
6467 -/**
6468 - * dpmng_get_container_id() - Get container ID associated with a given portal.
6469 - * @mc_io: Pointer to MC portal's I/O object
6470 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6471 - * @container_id: Requested container ID
6472 - *
6473 - * Return: '0' on Success; Error code otherwise.
6474 - */
6475 -int dpmng_get_container_id(struct fsl_mc_io *mc_io,
6476 - u32 cmd_flags,
6477 - int *container_id)
6478 -{
6479 - struct mc_command cmd = { 0 };
6480 - struct dpmng_rsp_get_container_id *rsp_params;
6481 - int err;
6482 -
6483 - /* prepare command */
6484 - cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_CONT_ID,
6485 - cmd_flags,
6486 - 0);
6487 -
6488 - /* send command to mc*/
6489 - err = mc_send_command(mc_io, &cmd);
6490 - if (err)
6491 - return err;
6492 -
6493 - /* retrieve response parameters */
6494 - rsp_params = (struct dpmng_rsp_get_container_id *)cmd.params;
6495 - *container_id = le32_to_cpu(rsp_params->container_id);
6496 -
6497 - return 0;
6498 -}
6499 -
6500 diff --git a/drivers/staging/fsl-mc/bus/dprc-cmd.h b/drivers/staging/fsl-mc/bus/dprc-cmd.h
6501 index 009d6567..b7d8c345 100644
6502 --- a/drivers/staging/fsl-mc/bus/dprc-cmd.h
6503 +++ b/drivers/staging/fsl-mc/bus/dprc-cmd.h
6504 @@ -12,7 +12,6 @@
6505 * names of any contributors may be used to endorse or promote products
6506 * derived from this software without specific prior written permission.
6507 *
6508 - *
6509 * ALTERNATIVELY, this software may be distributed under the terms of the
6510 * GNU General Public License ("GPL") as published by the Free Software
6511 * Foundation, either version 2 of that License or (at your option) any
6512 @@ -42,48 +41,39 @@
6513 #define _FSL_DPRC_CMD_H
6514
6515 /* Minimal supported DPRC Version */
6516 -#define DPRC_MIN_VER_MAJOR 5
6517 +#define DPRC_MIN_VER_MAJOR 6
6518 #define DPRC_MIN_VER_MINOR 0
6519
6520 +/* Command versioning */
6521 +#define DPRC_CMD_BASE_VERSION 1
6522 +#define DPRC_CMD_ID_OFFSET 4
6523 +
6524 +#define DPRC_CMD(id) ((id << DPRC_CMD_ID_OFFSET) | DPRC_CMD_BASE_VERSION)
6525 +
6526 /* Command IDs */
6527 -#define DPRC_CMDID_CLOSE 0x800
6528 -#define DPRC_CMDID_OPEN 0x805
6529 -#define DPRC_CMDID_CREATE 0x905
6530 -
6531 -#define DPRC_CMDID_GET_ATTR 0x004
6532 -#define DPRC_CMDID_RESET_CONT 0x005
6533 -
6534 -#define DPRC_CMDID_SET_IRQ 0x010
6535 -#define DPRC_CMDID_GET_IRQ 0x011
6536 -#define DPRC_CMDID_SET_IRQ_ENABLE 0x012
6537 -#define DPRC_CMDID_GET_IRQ_ENABLE 0x013
6538 -#define DPRC_CMDID_SET_IRQ_MASK 0x014
6539 -#define DPRC_CMDID_GET_IRQ_MASK 0x015
6540 -#define DPRC_CMDID_GET_IRQ_STATUS 0x016
6541 -#define DPRC_CMDID_CLEAR_IRQ_STATUS 0x017
6542 -
6543 -#define DPRC_CMDID_CREATE_CONT 0x151
6544 -#define DPRC_CMDID_DESTROY_CONT 0x152
6545 -#define DPRC_CMDID_SET_RES_QUOTA 0x155
6546 -#define DPRC_CMDID_GET_RES_QUOTA 0x156
6547 -#define DPRC_CMDID_ASSIGN 0x157
6548 -#define DPRC_CMDID_UNASSIGN 0x158
6549 -#define DPRC_CMDID_GET_OBJ_COUNT 0x159
6550 -#define DPRC_CMDID_GET_OBJ 0x15A
6551 -#define DPRC_CMDID_GET_RES_COUNT 0x15B
6552 -#define DPRC_CMDID_GET_RES_IDS 0x15C
6553 -#define DPRC_CMDID_GET_OBJ_REG 0x15E
6554 -#define DPRC_CMDID_SET_OBJ_IRQ 0x15F
6555 -#define DPRC_CMDID_GET_OBJ_IRQ 0x160
6556 -#define DPRC_CMDID_SET_OBJ_LABEL 0x161
6557 -#define DPRC_CMDID_GET_OBJ_DESC 0x162
6558 -
6559 -#define DPRC_CMDID_CONNECT 0x167
6560 -#define DPRC_CMDID_DISCONNECT 0x168
6561 -#define DPRC_CMDID_GET_POOL 0x169
6562 -#define DPRC_CMDID_GET_POOL_COUNT 0x16A
6563 -
6564 -#define DPRC_CMDID_GET_CONNECTION 0x16C
6565 +#define DPRC_CMDID_CLOSE DPRC_CMD(0x800)
6566 +#define DPRC_CMDID_OPEN DPRC_CMD(0x805)
6567 +#define DPRC_CMDID_GET_API_VERSION DPRC_CMD(0xa05)
6568 +
6569 +#define DPRC_CMDID_GET_ATTR DPRC_CMD(0x004)
6570 +#define DPRC_CMDID_RESET_CONT DPRC_CMD(0x005)
6571 +
6572 +#define DPRC_CMDID_SET_IRQ DPRC_CMD(0x010)
6573 +#define DPRC_CMDID_GET_IRQ DPRC_CMD(0x011)
6574 +#define DPRC_CMDID_SET_IRQ_ENABLE DPRC_CMD(0x012)
6575 +#define DPRC_CMDID_GET_IRQ_ENABLE DPRC_CMD(0x013)
6576 +#define DPRC_CMDID_SET_IRQ_MASK DPRC_CMD(0x014)
6577 +#define DPRC_CMDID_GET_IRQ_MASK DPRC_CMD(0x015)
6578 +#define DPRC_CMDID_GET_IRQ_STATUS DPRC_CMD(0x016)
6579 +#define DPRC_CMDID_CLEAR_IRQ_STATUS DPRC_CMD(0x017)
6580 +
6581 +#define DPRC_CMDID_GET_CONT_ID DPRC_CMD(0x830)
6582 +#define DPRC_CMDID_GET_OBJ_COUNT DPRC_CMD(0x159)
6583 +#define DPRC_CMDID_GET_OBJ DPRC_CMD(0x15A)
6584 +#define DPRC_CMDID_GET_RES_COUNT DPRC_CMD(0x15B)
6585 +#define DPRC_CMDID_GET_OBJ_REG DPRC_CMD(0x15E)
6586 +#define DPRC_CMDID_SET_OBJ_IRQ DPRC_CMD(0x15F)
6587 +#define DPRC_CMDID_GET_OBJ_IRQ DPRC_CMD(0x160)
6588
6589 struct dprc_cmd_open {
6590 __le32 container_id;
6591 @@ -199,9 +189,6 @@ struct dprc_rsp_get_attributes {
6592 /* response word 1 */
6593 __le32 options;
6594 __le32 portal_id;
6595 - /* response word 2 */
6596 - __le16 version_major;
6597 - __le16 version_minor;
6598 };
6599
6600 struct dprc_cmd_set_res_quota {
6601 @@ -367,11 +354,16 @@ struct dprc_cmd_get_obj_region {
6602
6603 struct dprc_rsp_get_obj_region {
6604 /* response word 0 */
6605 - __le64 pad;
6606 + __le64 pad0;
6607 /* response word 1 */
6608 - __le64 base_addr;
6609 + __le32 base_addr;
6610 + __le32 pad1;
6611 /* response word 2 */
6612 __le32 size;
6613 + u8 type;
6614 + u8 pad2[3];
6615 + /* response word 3 */
6616 + __le32 flags;
6617 };
6618
6619 struct dprc_cmd_set_obj_label {
6620 diff --git a/drivers/staging/fsl-mc/bus/dprc-driver.c b/drivers/staging/fsl-mc/bus/dprc-driver.c
6621 index c5ee4639..f6e6211b 100644
6622 --- a/drivers/staging/fsl-mc/bus/dprc-driver.c
6623 +++ b/drivers/staging/fsl-mc/bus/dprc-driver.c
6624 @@ -1,7 +1,7 @@
6625 /*
6626 * Freescale data path resource container (DPRC) driver
6627 *
6628 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
6629 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
6630 * Author: German Rivera <German.Rivera@freescale.com>
6631 *
6632 * This file is licensed under the terms of the GNU General Public
6633 @@ -160,6 +160,8 @@ static void check_plugged_state_change(struct fsl_mc_device *mc_dev,
6634 * dprc_add_new_devices - Adds devices to the logical bus for a DPRC
6635 *
6636 * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object
6637 + * @driver_override: driver override to apply to new objects found in the
6638 + * DPRC, or NULL, if none.
6639 * @obj_desc_array: array of device descriptors for child devices currently
6640 * present in the physical DPRC.
6641 * @num_child_objects_in_mc: number of entries in obj_desc_array
6642 @@ -169,6 +171,7 @@ static void check_plugged_state_change(struct fsl_mc_device *mc_dev,
6643 * in the physical DPRC.
6644 */
6645 static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev,
6646 + const char *driver_override,
6647 struct dprc_obj_desc *obj_desc_array,
6648 int num_child_objects_in_mc)
6649 {
6650 @@ -188,11 +191,12 @@ static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev,
6651 child_dev = fsl_mc_device_lookup(obj_desc, mc_bus_dev);
6652 if (child_dev) {
6653 check_plugged_state_change(child_dev, obj_desc);
6654 + put_device(&child_dev->dev);
6655 continue;
6656 }
6657
6658 error = fsl_mc_device_add(obj_desc, NULL, &mc_bus_dev->dev,
6659 - &child_dev);
6660 + driver_override, &child_dev);
6661 if (error < 0)
6662 continue;
6663 }
6664 @@ -202,6 +206,8 @@ static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev,
6665 * dprc_scan_objects - Discover objects in a DPRC
6666 *
6667 * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object
6668 + * @driver_override: driver override to apply to new objects found in the
6669 + * DPRC, or NULL, if none.
6670 * @total_irq_count: total number of IRQs needed by objects in the DPRC.
6671 *
6672 * Detects objects added and removed from a DPRC and synchronizes the
6673 @@ -217,6 +223,7 @@ static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev,
6674 * of the device drivers for the non-allocatable devices.
6675 */
6676 int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev,
6677 + const char *driver_override,
6678 unsigned int *total_irq_count)
6679 {
6680 int num_child_objects;
6681 @@ -297,7 +304,7 @@ int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev,
6682 dprc_remove_devices(mc_bus_dev, child_obj_desc_array,
6683 num_child_objects);
6684
6685 - dprc_add_new_devices(mc_bus_dev, child_obj_desc_array,
6686 + dprc_add_new_devices(mc_bus_dev, driver_override, child_obj_desc_array,
6687 num_child_objects);
6688
6689 if (child_obj_desc_array)
6690 @@ -328,7 +335,7 @@ int dprc_scan_container(struct fsl_mc_device *mc_bus_dev)
6691 * Discover objects in the DPRC:
6692 */
6693 mutex_lock(&mc_bus->scan_mutex);
6694 - error = dprc_scan_objects(mc_bus_dev, &irq_count);
6695 + error = dprc_scan_objects(mc_bus_dev, NULL, &irq_count);
6696 mutex_unlock(&mc_bus->scan_mutex);
6697 if (error < 0)
6698 goto error;
6699 @@ -415,7 +422,7 @@ static irqreturn_t dprc_irq0_handler_thread(int irq_num, void *arg)
6700 DPRC_IRQ_EVENT_OBJ_CREATED)) {
6701 unsigned int irq_count;
6702
6703 - error = dprc_scan_objects(mc_dev, &irq_count);
6704 + error = dprc_scan_objects(mc_dev, NULL, &irq_count);
6705 if (error < 0) {
6706 /*
6707 * If the error is -ENXIO, we ignore it, as it indicates
6708 @@ -505,7 +512,7 @@ static int register_dprc_irq_handler(struct fsl_mc_device *mc_dev)
6709 dprc_irq0_handler,
6710 dprc_irq0_handler_thread,
6711 IRQF_NO_SUSPEND | IRQF_ONESHOT,
6712 - "FSL MC DPRC irq0",
6713 + dev_name(&mc_dev->dev),
6714 &mc_dev->dev);
6715 if (error < 0) {
6716 dev_err(&mc_dev->dev,
6717 @@ -597,6 +604,7 @@ static int dprc_probe(struct fsl_mc_device *mc_dev)
6718 struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev);
6719 bool mc_io_created = false;
6720 bool msi_domain_set = false;
6721 + u16 major_ver, minor_ver;
6722
6723 if (WARN_ON(strcmp(mc_dev->obj_desc.type, "dprc") != 0))
6724 return -EINVAL;
6725 @@ -669,13 +677,21 @@ static int dprc_probe(struct fsl_mc_device *mc_dev)
6726 goto error_cleanup_open;
6727 }
6728
6729 - if (mc_bus->dprc_attr.version.major < DPRC_MIN_VER_MAJOR ||
6730 - (mc_bus->dprc_attr.version.major == DPRC_MIN_VER_MAJOR &&
6731 - mc_bus->dprc_attr.version.minor < DPRC_MIN_VER_MINOR)) {
6732 + error = dprc_get_api_version(mc_dev->mc_io, 0,
6733 + &major_ver,
6734 + &minor_ver);
6735 + if (error < 0) {
6736 + dev_err(&mc_dev->dev, "dprc_get_api_version() failed: %d\n",
6737 + error);
6738 + goto error_cleanup_open;
6739 + }
6740 +
6741 + if (major_ver < DPRC_MIN_VER_MAJOR ||
6742 + (major_ver == DPRC_MIN_VER_MAJOR &&
6743 + minor_ver < DPRC_MIN_VER_MINOR)) {
6744 dev_err(&mc_dev->dev,
6745 "ERROR: DPRC version %d.%d not supported\n",
6746 - mc_bus->dprc_attr.version.major,
6747 - mc_bus->dprc_attr.version.minor);
6748 + major_ver, minor_ver);
6749 error = -ENOTSUPP;
6750 goto error_cleanup_open;
6751 }
6752 diff --git a/drivers/staging/fsl-mc/bus/dprc.c b/drivers/staging/fsl-mc/bus/dprc.c
6753 index 9fea3def..764cd3fb 100644
6754 --- a/drivers/staging/fsl-mc/bus/dprc.c
6755 +++ b/drivers/staging/fsl-mc/bus/dprc.c
6756 @@ -1,4 +1,5 @@
6757 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
6758 +/*
6759 + * Copyright 2013-2016 Freescale Semiconductor Inc.
6760 *
6761 * Redistribution and use in source and binary forms, with or without
6762 * modification, are permitted provided that the following conditions are met:
6763 @@ -11,7 +12,6 @@
6764 * names of any contributors may be used to endorse or promote products
6765 * derived from this software without specific prior written permission.
6766 *
6767 - *
6768 * ALTERNATIVELY, this software may be distributed under the terms of the
6769 * GNU General Public License ("GPL") as published by the Free Software
6770 * Foundation, either version 2 of that License or (at your option) any
6771 @@ -99,93 +99,6 @@ int dprc_close(struct fsl_mc_io *mc_io,
6772 }
6773 EXPORT_SYMBOL(dprc_close);
6774
6775 -/**
6776 - * dprc_create_container() - Create child container
6777 - * @mc_io: Pointer to MC portal's I/O object
6778 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6779 - * @token: Token of DPRC object
6780 - * @cfg: Child container configuration
6781 - * @child_container_id: Returned child container ID
6782 - * @child_portal_offset: Returned child portal offset from MC portal base
6783 - *
6784 - * Return: '0' on Success; Error code otherwise.
6785 - */
6786 -int dprc_create_container(struct fsl_mc_io *mc_io,
6787 - u32 cmd_flags,
6788 - u16 token,
6789 - struct dprc_cfg *cfg,
6790 - int *child_container_id,
6791 - u64 *child_portal_offset)
6792 -{
6793 - struct mc_command cmd = { 0 };
6794 - struct dprc_cmd_create_container *cmd_params;
6795 - struct dprc_rsp_create_container *rsp_params;
6796 - int err;
6797 -
6798 - /* prepare command */
6799 - cmd_params = (struct dprc_cmd_create_container *)cmd.params;
6800 - cmd_params->options = cpu_to_le32(cfg->options);
6801 - cmd_params->icid = cpu_to_le16(cfg->icid);
6802 - cmd_params->portal_id = cpu_to_le32(cfg->portal_id);
6803 - strncpy(cmd_params->label, cfg->label, 16);
6804 - cmd_params->label[15] = '\0';
6805 -
6806 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_CREATE_CONT,
6807 - cmd_flags, token);
6808 -
6809 - /* send command to mc*/
6810 - err = mc_send_command(mc_io, &cmd);
6811 - if (err)
6812 - return err;
6813 -
6814 - /* retrieve response parameters */
6815 - rsp_params = (struct dprc_rsp_create_container *)cmd.params;
6816 - *child_container_id = le32_to_cpu(rsp_params->child_container_id);
6817 - *child_portal_offset = le64_to_cpu(rsp_params->child_portal_addr);
6818 -
6819 - return 0;
6820 -}
6821 -
6822 -/**
6823 - * dprc_destroy_container() - Destroy child container.
6824 - * @mc_io: Pointer to MC portal's I/O object
6825 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6826 - * @token: Token of DPRC object
6827 - * @child_container_id: ID of the container to destroy
6828 - *
6829 - * This function terminates the child container, so following this call the
6830 - * child container ID becomes invalid.
6831 - *
6832 - * Notes:
6833 - * - All resources and objects of the destroyed container are returned to the
6834 - * parent container or destroyed if were created be the destroyed container.
6835 - * - This function destroy all the child containers of the specified
6836 - * container prior to destroying the container itself.
6837 - *
6838 - * warning: Only the parent container is allowed to destroy a child policy
6839 - * Container 0 can't be destroyed
6840 - *
6841 - * Return: '0' on Success; Error code otherwise.
6842 - *
6843 - */
6844 -int dprc_destroy_container(struct fsl_mc_io *mc_io,
6845 - u32 cmd_flags,
6846 - u16 token,
6847 - int child_container_id)
6848 -{
6849 - struct mc_command cmd = { 0 };
6850 - struct dprc_cmd_destroy_container *cmd_params;
6851 -
6852 - /* prepare command */
6853 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_DESTROY_CONT,
6854 - cmd_flags, token);
6855 - cmd_params = (struct dprc_cmd_destroy_container *)cmd.params;
6856 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
6857 -
6858 - /* send command to mc*/
6859 - return mc_send_command(mc_io, &cmd);
6860 -}
6861 -
6862 /**
6863 * dprc_reset_container - Reset child container.
6864 * @mc_io: Pointer to MC portal's I/O object
6865 @@ -565,279 +478,6 @@ int dprc_get_attributes(struct fsl_mc_io *mc_io,
6866 attr->icid = le16_to_cpu(rsp_params->icid);
6867 attr->options = le32_to_cpu(rsp_params->options);
6868 attr->portal_id = le32_to_cpu(rsp_params->portal_id);
6869 - attr->version.major = le16_to_cpu(rsp_params->version_major);
6870 - attr->version.minor = le16_to_cpu(rsp_params->version_minor);
6871 -
6872 - return 0;
6873 -}
6874 -
6875 -/**
6876 - * dprc_set_res_quota() - Set allocation policy for a specific resource/object
6877 - * type in a child container
6878 - * @mc_io: Pointer to MC portal's I/O object
6879 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6880 - * @token: Token of DPRC object
6881 - * @child_container_id: ID of the child container
6882 - * @type: Resource/object type
6883 - * @quota: Sets the maximum number of resources of the selected type
6884 - * that the child container is allowed to allocate from its parent;
6885 - * when quota is set to -1, the policy is the same as container's
6886 - * general policy.
6887 - *
6888 - * Allocation policy determines whether or not a container may allocate
6889 - * resources from its parent. Each container has a 'global' allocation policy
6890 - * that is set when the container is created.
6891 - *
6892 - * This function sets allocation policy for a specific resource type.
6893 - * The default policy for all resource types matches the container's 'global'
6894 - * allocation policy.
6895 - *
6896 - * Return: '0' on Success; Error code otherwise.
6897 - *
6898 - * @warning Only the parent container is allowed to change a child policy.
6899 - */
6900 -int dprc_set_res_quota(struct fsl_mc_io *mc_io,
6901 - u32 cmd_flags,
6902 - u16 token,
6903 - int child_container_id,
6904 - char *type,
6905 - u16 quota)
6906 -{
6907 - struct mc_command cmd = { 0 };
6908 - struct dprc_cmd_set_res_quota *cmd_params;
6909 -
6910 - /* prepare command */
6911 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_RES_QUOTA,
6912 - cmd_flags, token);
6913 - cmd_params = (struct dprc_cmd_set_res_quota *)cmd.params;
6914 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
6915 - cmd_params->quota = cpu_to_le16(quota);
6916 - strncpy(cmd_params->type, type, 16);
6917 - cmd_params->type[15] = '\0';
6918 -
6919 - /* send command to mc*/
6920 - return mc_send_command(mc_io, &cmd);
6921 -}
6922 -
6923 -/**
6924 - * dprc_get_res_quota() - Gets the allocation policy of a specific
6925 - * resource/object type in a child container
6926 - * @mc_io: Pointer to MC portal's I/O object
6927 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6928 - * @token: Token of DPRC object
6929 - * @child_container_id; ID of the child container
6930 - * @type: resource/object type
6931 - * @quota: Returnes the maximum number of resources of the selected type
6932 - * that the child container is allowed to allocate from the parent;
6933 - * when quota is set to -1, the policy is the same as container's
6934 - * general policy.
6935 - *
6936 - * Return: '0' on Success; Error code otherwise.
6937 - */
6938 -int dprc_get_res_quota(struct fsl_mc_io *mc_io,
6939 - u32 cmd_flags,
6940 - u16 token,
6941 - int child_container_id,
6942 - char *type,
6943 - u16 *quota)
6944 -{
6945 - struct mc_command cmd = { 0 };
6946 - struct dprc_cmd_get_res_quota *cmd_params;
6947 - struct dprc_rsp_get_res_quota *rsp_params;
6948 - int err;
6949 -
6950 - /* prepare command */
6951 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_QUOTA,
6952 - cmd_flags, token);
6953 - cmd_params = (struct dprc_cmd_get_res_quota *)cmd.params;
6954 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
6955 - strncpy(cmd_params->type, type, 16);
6956 - cmd_params->type[15] = '\0';
6957 -
6958 - /* send command to mc*/
6959 - err = mc_send_command(mc_io, &cmd);
6960 - if (err)
6961 - return err;
6962 -
6963 - /* retrieve response parameters */
6964 - rsp_params = (struct dprc_rsp_get_res_quota *)cmd.params;
6965 - *quota = le16_to_cpu(rsp_params->quota);
6966 -
6967 - return 0;
6968 -}
6969 -
6970 -/**
6971 - * dprc_assign() - Assigns objects or resource to a child container.
6972 - * @mc_io: Pointer to MC portal's I/O object
6973 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6974 - * @token: Token of DPRC object
6975 - * @container_id: ID of the child container
6976 - * @res_req: Describes the type and amount of resources to
6977 - * assign to the given container
6978 - *
6979 - * Assignment is usually done by a parent (this DPRC) to one of its child
6980 - * containers.
6981 - *
6982 - * According to the DPRC allocation policy, the assigned resources may be taken
6983 - * (allocated) from the container's ancestors, if not enough resources are
6984 - * available in the container itself.
6985 - *
6986 - * The type of assignment depends on the dprc_res_req options, as follows:
6987 - * - DPRC_RES_REQ_OPT_EXPLICIT: indicates that assigned resources should have
6988 - * the explicit base ID specified at the id_base_align field of res_req.
6989 - * - DPRC_RES_REQ_OPT_ALIGNED: indicates that the assigned resources should be
6990 - * aligned to the value given at id_base_align field of res_req.
6991 - * - DPRC_RES_REQ_OPT_PLUGGED: Relevant only for object assignment,
6992 - * and indicates that the object must be set to the plugged state.
6993 - *
6994 - * A container may use this function with its own ID in order to change a
6995 - * object state to plugged or unplugged.
6996 - *
6997 - * If IRQ information has been set in the child DPRC, it will signal an
6998 - * interrupt following every change in its object assignment.
6999 - *
7000 - * Return: '0' on Success; Error code otherwise.
7001 - */
7002 -int dprc_assign(struct fsl_mc_io *mc_io,
7003 - u32 cmd_flags,
7004 - u16 token,
7005 - int container_id,
7006 - struct dprc_res_req *res_req)
7007 -{
7008 - struct mc_command cmd = { 0 };
7009 - struct dprc_cmd_assign *cmd_params;
7010 -
7011 - /* prepare command */
7012 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_ASSIGN,
7013 - cmd_flags, token);
7014 - cmd_params = (struct dprc_cmd_assign *)cmd.params;
7015 - cmd_params->container_id = cpu_to_le32(container_id);
7016 - cmd_params->options = cpu_to_le32(res_req->options);
7017 - cmd_params->num = cpu_to_le32(res_req->num);
7018 - cmd_params->id_base_align = cpu_to_le32(res_req->id_base_align);
7019 - strncpy(cmd_params->type, res_req->type, 16);
7020 - cmd_params->type[15] = '\0';
7021 -
7022 - /* send command to mc*/
7023 - return mc_send_command(mc_io, &cmd);
7024 -}
7025 -
7026 -/**
7027 - * dprc_unassign() - Un-assigns objects or resources from a child container
7028 - * and moves them into this (parent) DPRC.
7029 - * @mc_io: Pointer to MC portal's I/O object
7030 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7031 - * @token: Token of DPRC object
7032 - * @child_container_id: ID of the child container
7033 - * @res_req: Describes the type and amount of resources to un-assign from
7034 - * the child container
7035 - *
7036 - * Un-assignment of objects can succeed only if the object is not in the
7037 - * plugged or opened state.
7038 - *
7039 - * Return: '0' on Success; Error code otherwise.
7040 - */
7041 -int dprc_unassign(struct fsl_mc_io *mc_io,
7042 - u32 cmd_flags,
7043 - u16 token,
7044 - int child_container_id,
7045 - struct dprc_res_req *res_req)
7046 -{
7047 - struct mc_command cmd = { 0 };
7048 - struct dprc_cmd_unassign *cmd_params;
7049 -
7050 - /* prepare command */
7051 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_UNASSIGN,
7052 - cmd_flags,
7053 - token);
7054 - cmd_params = (struct dprc_cmd_unassign *)cmd.params;
7055 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
7056 - cmd_params->options = cpu_to_le32(res_req->options);
7057 - cmd_params->num = cpu_to_le32(res_req->num);
7058 - cmd_params->id_base_align = cpu_to_le32(res_req->id_base_align);
7059 - strncpy(cmd_params->type, res_req->type, 16);
7060 - cmd_params->type[15] = '\0';
7061 -
7062 - /* send command to mc*/
7063 - return mc_send_command(mc_io, &cmd);
7064 -}
7065 -
7066 -/**
7067 - * dprc_get_pool_count() - Get the number of dprc's pools
7068 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7069 - * @mc_io: Pointer to MC portal's I/O object
7070 - * @token: Token of DPRC object
7071 - * @pool_count: Returned number of resource pools in the dprc
7072 - *
7073 - * Return: '0' on Success; Error code otherwise.
7074 - */
7075 -int dprc_get_pool_count(struct fsl_mc_io *mc_io,
7076 - u32 cmd_flags,
7077 - u16 token,
7078 - int *pool_count)
7079 -{
7080 - struct mc_command cmd = { 0 };
7081 - struct dprc_rsp_get_pool_count *rsp_params;
7082 - int err;
7083 -
7084 - /* prepare command */
7085 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_POOL_COUNT,
7086 - cmd_flags, token);
7087 -
7088 - /* send command to mc*/
7089 - err = mc_send_command(mc_io, &cmd);
7090 - if (err)
7091 - return err;
7092 -
7093 - /* retrieve response parameters */
7094 - rsp_params = (struct dprc_rsp_get_pool_count *)cmd.params;
7095 - *pool_count = le32_to_cpu(rsp_params->pool_count);
7096 -
7097 - return 0;
7098 -}
7099 -
7100 -/**
7101 - * dprc_get_pool() - Get the type (string) of a certain dprc's pool
7102 - * @mc_io: Pointer to MC portal's I/O object
7103 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7104 - * @token: Token of DPRC object
7105 - * @pool_index; Index of the pool to be queried (< pool_count)
7106 - * @type: The type of the pool
7107 - *
7108 - * The pool types retrieved one by one by incrementing
7109 - * pool_index up to (not including) the value of pool_count returned
7110 - * from dprc_get_pool_count(). dprc_get_pool_count() must
7111 - * be called prior to dprc_get_pool().
7112 - *
7113 - * Return: '0' on Success; Error code otherwise.
7114 - */
7115 -int dprc_get_pool(struct fsl_mc_io *mc_io,
7116 - u32 cmd_flags,
7117 - u16 token,
7118 - int pool_index,
7119 - char *type)
7120 -{
7121 - struct mc_command cmd = { 0 };
7122 - struct dprc_cmd_get_pool *cmd_params;
7123 - struct dprc_rsp_get_pool *rsp_params;
7124 - int err;
7125 -
7126 - /* prepare command */
7127 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_POOL,
7128 - cmd_flags,
7129 - token);
7130 - cmd_params = (struct dprc_cmd_get_pool *)cmd.params;
7131 - cmd_params->pool_index = cpu_to_le32(pool_index);
7132 -
7133 - /* send command to mc*/
7134 - err = mc_send_command(mc_io, &cmd);
7135 - if (err)
7136 - return err;
7137 -
7138 - /* retrieve response parameters */
7139 - rsp_params = (struct dprc_rsp_get_pool *)cmd.params;
7140 - strncpy(type, rsp_params->type, 16);
7141 - type[15] = '\0';
7142
7143 return 0;
7144 }
7145 @@ -933,64 +573,6 @@ int dprc_get_obj(struct fsl_mc_io *mc_io,
7146 }
7147 EXPORT_SYMBOL(dprc_get_obj);
7148
7149 -/**
7150 - * dprc_get_obj_desc() - Get object descriptor.
7151 - *
7152 - * @mc_io: Pointer to MC portal's I/O object
7153 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7154 - * @token: Token of DPRC object
7155 - * @obj_type: The type of the object to get its descriptor.
7156 - * @obj_id: The id of the object to get its descriptor
7157 - * @obj_desc: The returned descriptor to fill and return to the user
7158 - *
7159 - * Return: '0' on Success; Error code otherwise.
7160 - *
7161 - */
7162 -int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
7163 - u32 cmd_flags,
7164 - u16 token,
7165 - char *obj_type,
7166 - int obj_id,
7167 - struct dprc_obj_desc *obj_desc)
7168 -{
7169 - struct mc_command cmd = { 0 };
7170 - struct dprc_cmd_get_obj_desc *cmd_params;
7171 - struct dprc_rsp_get_obj_desc *rsp_params;
7172 - int err;
7173 -
7174 - /* prepare command */
7175 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_DESC,
7176 - cmd_flags,
7177 - token);
7178 - cmd_params = (struct dprc_cmd_get_obj_desc *)cmd.params;
7179 - cmd_params->obj_id = cpu_to_le32(obj_id);
7180 - strncpy(cmd_params->type, obj_type, 16);
7181 - cmd_params->type[15] = '\0';
7182 -
7183 - /* send command to mc*/
7184 - err = mc_send_command(mc_io, &cmd);
7185 - if (err)
7186 - return err;
7187 -
7188 - /* retrieve response parameters */
7189 - rsp_params = (struct dprc_rsp_get_obj_desc *)cmd.params;
7190 - obj_desc->id = le32_to_cpu(rsp_params->id);
7191 - obj_desc->vendor = le16_to_cpu(rsp_params->vendor);
7192 - obj_desc->irq_count = rsp_params->irq_count;
7193 - obj_desc->region_count = rsp_params->region_count;
7194 - obj_desc->state = le32_to_cpu(rsp_params->state);
7195 - obj_desc->ver_major = le16_to_cpu(rsp_params->version_major);
7196 - obj_desc->ver_minor = le16_to_cpu(rsp_params->version_minor);
7197 - obj_desc->flags = le16_to_cpu(rsp_params->flags);
7198 - strncpy(obj_desc->type, rsp_params->type, 16);
7199 - obj_desc->type[15] = '\0';
7200 - strncpy(obj_desc->label, rsp_params->label, 16);
7201 - obj_desc->label[15] = '\0';
7202 -
7203 - return 0;
7204 -}
7205 -EXPORT_SYMBOL(dprc_get_obj_desc);
7206 -
7207 /**
7208 * dprc_set_obj_irq() - Set IRQ information for object to trigger an interrupt.
7209 * @mc_io: Pointer to MC portal's I/O object
7210 @@ -1129,52 +711,6 @@ int dprc_get_res_count(struct fsl_mc_io *mc_io,
7211 }
7212 EXPORT_SYMBOL(dprc_get_res_count);
7213
7214 -/**
7215 - * dprc_get_res_ids() - Obtains IDs of free resources in the container
7216 - * @mc_io: Pointer to MC portal's I/O object
7217 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7218 - * @token: Token of DPRC object
7219 - * @type: pool type
7220 - * @range_desc: range descriptor
7221 - *
7222 - * Return: '0' on Success; Error code otherwise.
7223 - */
7224 -int dprc_get_res_ids(struct fsl_mc_io *mc_io,
7225 - u32 cmd_flags,
7226 - u16 token,
7227 - char *type,
7228 - struct dprc_res_ids_range_desc *range_desc)
7229 -{
7230 - struct mc_command cmd = { 0 };
7231 - struct dprc_cmd_get_res_ids *cmd_params;
7232 - struct dprc_rsp_get_res_ids *rsp_params;
7233 - int err;
7234 -
7235 - /* prepare command */
7236 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_IDS,
7237 - cmd_flags, token);
7238 - cmd_params = (struct dprc_cmd_get_res_ids *)cmd.params;
7239 - cmd_params->iter_status = range_desc->iter_status;
7240 - cmd_params->base_id = cpu_to_le32(range_desc->base_id);
7241 - cmd_params->last_id = cpu_to_le32(range_desc->last_id);
7242 - strncpy(cmd_params->type, type, 16);
7243 - cmd_params->type[15] = '\0';
7244 -
7245 - /* send command to mc*/
7246 - err = mc_send_command(mc_io, &cmd);
7247 - if (err)
7248 - return err;
7249 -
7250 - /* retrieve response parameters */
7251 - rsp_params = (struct dprc_rsp_get_res_ids *)cmd.params;
7252 - range_desc->iter_status = rsp_params->iter_status;
7253 - range_desc->base_id = le32_to_cpu(rsp_params->base_id);
7254 - range_desc->last_id = le32_to_cpu(rsp_params->last_id);
7255 -
7256 - return 0;
7257 -}
7258 -EXPORT_SYMBOL(dprc_get_res_ids);
7259 -
7260 /**
7261 * dprc_get_obj_region() - Get region information for a specified object.
7262 * @mc_io: Pointer to MC portal's I/O object
7263 @@ -1216,160 +752,66 @@ int dprc_get_obj_region(struct fsl_mc_io *mc_io,
7264
7265 /* retrieve response parameters */
7266 rsp_params = (struct dprc_rsp_get_obj_region *)cmd.params;
7267 - region_desc->base_offset = le64_to_cpu(rsp_params->base_addr);
7268 + region_desc->base_offset = le32_to_cpu(rsp_params->base_addr);
7269 region_desc->size = le32_to_cpu(rsp_params->size);
7270 + region_desc->type = rsp_params->type;
7271 + region_desc->flags = le32_to_cpu(rsp_params->flags);
7272
7273 return 0;
7274 }
7275 EXPORT_SYMBOL(dprc_get_obj_region);
7276
7277 /**
7278 - * dprc_set_obj_label() - Set object label.
7279 - * @mc_io: Pointer to MC portal's I/O object
7280 + * dprc_get_api_version - Get Data Path Resource Container API version
7281 + * @mc_io: Pointer to Mc portal's I/O object
7282 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7283 - * @token: Token of DPRC object
7284 - * @obj_type: Object's type
7285 - * @obj_id: Object's ID
7286 - * @label: The required label. The maximum length is 16 chars.
7287 + * @major_ver: Major version of Data Path Resource Container API
7288 + * @minor_ver: Minor version of Data Path Resource Container API
7289 *
7290 * Return: '0' on Success; Error code otherwise.
7291 */
7292 -int dprc_set_obj_label(struct fsl_mc_io *mc_io,
7293 - u32 cmd_flags,
7294 - u16 token,
7295 - char *obj_type,
7296 - int obj_id,
7297 - char *label)
7298 +int dprc_get_api_version(struct fsl_mc_io *mc_io,
7299 + u32 cmd_flags,
7300 + u16 *major_ver,
7301 + u16 *minor_ver)
7302 {
7303 struct mc_command cmd = { 0 };
7304 - struct dprc_cmd_set_obj_label *cmd_params;
7305 + int err;
7306
7307 /* prepare command */
7308 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_OBJ_LABEL,
7309 - cmd_flags,
7310 - token);
7311 - cmd_params = (struct dprc_cmd_set_obj_label *)cmd.params;
7312 - cmd_params->obj_id = cpu_to_le32(obj_id);
7313 - strncpy(cmd_params->label, label, 16);
7314 - cmd_params->label[15] = '\0';
7315 - strncpy(cmd_params->obj_type, obj_type, 16);
7316 - cmd_params->obj_type[15] = '\0';
7317 + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_API_VERSION,
7318 + cmd_flags, 0);
7319
7320 - /* send command to mc*/
7321 - return mc_send_command(mc_io, &cmd);
7322 -}
7323 -EXPORT_SYMBOL(dprc_set_obj_label);
7324 -
7325 -/**
7326 - * dprc_connect() - Connect two endpoints to create a network link between them
7327 - * @mc_io: Pointer to MC portal's I/O object
7328 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7329 - * @token: Token of DPRC object
7330 - * @endpoint1: Endpoint 1 configuration parameters
7331 - * @endpoint2: Endpoint 2 configuration parameters
7332 - * @cfg: Connection configuration. The connection configuration is ignored for
7333 - * connections made to DPMAC objects, where rate is retrieved from the
7334 - * MAC configuration.
7335 - *
7336 - * Return: '0' on Success; Error code otherwise.
7337 - */
7338 -int dprc_connect(struct fsl_mc_io *mc_io,
7339 - u32 cmd_flags,
7340 - u16 token,
7341 - const struct dprc_endpoint *endpoint1,
7342 - const struct dprc_endpoint *endpoint2,
7343 - const struct dprc_connection_cfg *cfg)
7344 -{
7345 - struct mc_command cmd = { 0 };
7346 - struct dprc_cmd_connect *cmd_params;
7347 + /* send command to mc */
7348 + err = mc_send_command(mc_io, &cmd);
7349 + if (err)
7350 + return err;
7351
7352 - /* prepare command */
7353 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_CONNECT,
7354 - cmd_flags,
7355 - token);
7356 - cmd_params = (struct dprc_cmd_connect *)cmd.params;
7357 - cmd_params->ep1_id = cpu_to_le32(endpoint1->id);
7358 - cmd_params->ep1_interface_id = cpu_to_le32(endpoint1->if_id);
7359 - cmd_params->ep2_id = cpu_to_le32(endpoint2->id);
7360 - cmd_params->ep2_interface_id = cpu_to_le32(endpoint2->if_id);
7361 - strncpy(cmd_params->ep1_type, endpoint1->type, 16);
7362 - cmd_params->ep1_type[15] = '\0';
7363 - cmd_params->max_rate = cpu_to_le32(cfg->max_rate);
7364 - cmd_params->committed_rate = cpu_to_le32(cfg->committed_rate);
7365 - strncpy(cmd_params->ep2_type, endpoint2->type, 16);
7366 - cmd_params->ep2_type[15] = '\0';
7367 + /* retrieve response parameters */
7368 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
7369
7370 - /* send command to mc*/
7371 - return mc_send_command(mc_io, &cmd);
7372 + return 0;
7373 }
7374
7375 /**
7376 - * dprc_disconnect() - Disconnect one endpoint to remove its network connection
7377 - * @mc_io: Pointer to MC portal's I/O object
7378 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7379 - * @token: Token of DPRC object
7380 - * @endpoint: Endpoint configuration parameters
7381 + * dprc_get_container_id - Get container ID associated with a given portal.
7382 + * @mc_io: Pointer to Mc portal's I/O object
7383 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7384 + * @container_id: Requested container id
7385 *
7386 * Return: '0' on Success; Error code otherwise.
7387 */
7388 -int dprc_disconnect(struct fsl_mc_io *mc_io,
7389 - u32 cmd_flags,
7390 - u16 token,
7391 - const struct dprc_endpoint *endpoint)
7392 -{
7393 - struct mc_command cmd = { 0 };
7394 - struct dprc_cmd_disconnect *cmd_params;
7395 -
7396 - /* prepare command */
7397 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_DISCONNECT,
7398 - cmd_flags,
7399 - token);
7400 - cmd_params = (struct dprc_cmd_disconnect *)cmd.params;
7401 - cmd_params->id = cpu_to_le32(endpoint->id);
7402 - cmd_params->interface_id = cpu_to_le32(endpoint->if_id);
7403 - strncpy(cmd_params->type, endpoint->type, 16);
7404 - cmd_params->type[15] = '\0';
7405 -
7406 - /* send command to mc*/
7407 - return mc_send_command(mc_io, &cmd);
7408 -}
7409 -
7410 -/**
7411 - * dprc_get_connection() - Get connected endpoint and link status if connection
7412 - * exists.
7413 - * @mc_io: Pointer to MC portal's I/O object
7414 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7415 - * @token: Token of DPRC object
7416 - * @endpoint1: Endpoint 1 configuration parameters
7417 - * @endpoint2: Returned endpoint 2 configuration parameters
7418 - * @state: Returned link state:
7419 - * 1 - link is up;
7420 - * 0 - link is down;
7421 - * -1 - no connection (endpoint2 information is irrelevant)
7422 - *
7423 - * Return: '0' on Success; -ENAVAIL if connection does not exist.
7424 - */
7425 -int dprc_get_connection(struct fsl_mc_io *mc_io,
7426 - u32 cmd_flags,
7427 - u16 token,
7428 - const struct dprc_endpoint *endpoint1,
7429 - struct dprc_endpoint *endpoint2,
7430 - int *state)
7431 +int dprc_get_container_id(struct fsl_mc_io *mc_io,
7432 + u32 cmd_flags,
7433 + int *container_id)
7434 {
7435 struct mc_command cmd = { 0 };
7436 - struct dprc_cmd_get_connection *cmd_params;
7437 - struct dprc_rsp_get_connection *rsp_params;
7438 int err;
7439
7440 /* prepare command */
7441 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONNECTION,
7442 + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONT_ID,
7443 cmd_flags,
7444 - token);
7445 - cmd_params = (struct dprc_cmd_get_connection *)cmd.params;
7446 - cmd_params->ep1_id = cpu_to_le32(endpoint1->id);
7447 - cmd_params->ep1_interface_id = cpu_to_le32(endpoint1->if_id);
7448 - strncpy(cmd_params->ep1_type, endpoint1->type, 16);
7449 - cmd_params->ep1_type[15] = '\0';
7450 + 0);
7451
7452 /* send command to mc*/
7453 err = mc_send_command(mc_io, &cmd);
7454 @@ -1377,12 +819,7 @@ int dprc_get_connection(struct fsl_mc_io *mc_io,
7455 return err;
7456
7457 /* retrieve response parameters */
7458 - rsp_params = (struct dprc_rsp_get_connection *)cmd.params;
7459 - endpoint2->id = le32_to_cpu(rsp_params->ep2_id);
7460 - endpoint2->if_id = le32_to_cpu(rsp_params->ep2_interface_id);
7461 - strncpy(endpoint2->type, rsp_params->ep2_type, 16);
7462 - endpoint2->type[15] = '\0';
7463 - *state = le32_to_cpu(rsp_params->state);
7464 + *container_id = (int)mc_cmd_read_object_id(&cmd);
7465
7466 return 0;
7467 }
7468 diff --git a/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c b/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c
7469 index e93ab53b..ce07096c 100644
7470 --- a/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c
7471 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c
7472 @@ -1,7 +1,7 @@
7473 /*
7474 - * Freescale MC object device allocator driver
7475 + * fsl-mc object allocator driver
7476 *
7477 - * Copyright (C) 2013 Freescale Semiconductor, Inc.
7478 + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
7479 *
7480 * This file is licensed under the terms of the GNU General Public
7481 * License version 2. This program is licensed "as is" without any
7482 @@ -12,9 +12,9 @@
7483 #include <linux/msi.h>
7484 #include "../include/mc-bus.h"
7485 #include "../include/mc-sys.h"
7486 -#include "../include/dpbp-cmd.h"
7487 -#include "../include/dpcon-cmd.h"
7488
7489 +#include "dpbp-cmd.h"
7490 +#include "dpcon-cmd.h"
7491 #include "fsl-mc-private.h"
7492
7493 #define FSL_MC_IS_ALLOCATABLE(_obj_type) \
7494 @@ -23,15 +23,12 @@
7495 strcmp(_obj_type, "dpcon") == 0)
7496
7497 /**
7498 - * fsl_mc_resource_pool_add_device - add allocatable device to a resource
7499 - * pool of a given MC bus
7500 + * fsl_mc_resource_pool_add_device - add allocatable object to a resource
7501 + * pool of a given fsl-mc bus
7502 *
7503 - * @mc_bus: pointer to the MC bus
7504 - * @pool_type: MC bus pool type
7505 - * @mc_dev: Pointer to allocatable MC object device
7506 - *
7507 - * It adds an allocatable MC object device to a container's resource pool of
7508 - * the given resource type
7509 + * @mc_bus: pointer to the fsl-mc bus
7510 + * @pool_type: pool type
7511 + * @mc_dev: pointer to allocatable fsl-mc device
7512 */
7513 static int __must_check fsl_mc_resource_pool_add_device(struct fsl_mc_bus
7514 *mc_bus,
7515 @@ -95,10 +92,10 @@ static int __must_check fsl_mc_resource_pool_add_device(struct fsl_mc_bus
7516 * fsl_mc_resource_pool_remove_device - remove an allocatable device from a
7517 * resource pool
7518 *
7519 - * @mc_dev: Pointer to allocatable MC object device
7520 + * @mc_dev: pointer to allocatable fsl-mc device
7521 *
7522 - * It permanently removes an allocatable MC object device from the resource
7523 - * pool, the device is currently in, as long as it is in the pool's free list.
7524 + * It permanently removes an allocatable fsl-mc device from the resource
7525 + * pool. It's an error if the device is in use.
7526 */
7527 static int __must_check fsl_mc_resource_pool_remove_device(struct fsl_mc_device
7528 *mc_dev)
7529 @@ -255,17 +252,18 @@ void fsl_mc_resource_free(struct fsl_mc_resource *resource)
7530 EXPORT_SYMBOL_GPL(fsl_mc_resource_free);
7531
7532 /**
7533 - * fsl_mc_object_allocate - Allocates a MC object device of the given
7534 - * pool type from a given MC bus
7535 + * fsl_mc_object_allocate - Allocates an fsl-mc object of the given
7536 + * pool type from a given fsl-mc bus instance
7537 *
7538 - * @mc_dev: MC device for which the MC object device is to be allocated
7539 - * @pool_type: MC bus resource pool type
7540 - * @new_mc_dev: Pointer to area where the pointer to the allocated
7541 - * MC object device is to be returned
7542 + * @mc_dev: fsl-mc device which is used in conjunction with the
7543 + * allocated object
7544 + * @pool_type: pool type
7545 + * @new_mc_dev: pointer to area where the pointer to the allocated device
7546 + * is to be returned
7547 *
7548 - * This function allocates a MC object device from the device's parent DPRC,
7549 - * from the corresponding MC bus' pool of allocatable MC object devices of
7550 - * the given resource type. mc_dev cannot be a DPRC itself.
7551 + * Allocatable objects are always used in conjunction with some functional
7552 + * device. This function allocates an object of the specified type from
7553 + * the DPRC containing the functional device.
7554 *
7555 * NOTE: pool_type must be different from FSL_MC_POOL_MCP, since MC
7556 * portals are allocated using fsl_mc_portal_allocate(), instead of
7557 @@ -312,10 +310,9 @@ int __must_check fsl_mc_object_allocate(struct fsl_mc_device *mc_dev,
7558 EXPORT_SYMBOL_GPL(fsl_mc_object_allocate);
7559
7560 /**
7561 - * fsl_mc_object_free - Returns an allocatable MC object device to the
7562 - * corresponding resource pool of a given MC bus.
7563 - *
7564 - * @mc_adev: Pointer to the MC object device
7565 + * fsl_mc_object_free - Returns an fsl-mc object to the resource
7566 + * pool where it came from.
7567 + * @mc_adev: Pointer to the fsl-mc device
7568 */
7569 void fsl_mc_object_free(struct fsl_mc_device *mc_adev)
7570 {
7571 @@ -332,8 +329,14 @@ void fsl_mc_object_free(struct fsl_mc_device *mc_adev)
7572 EXPORT_SYMBOL_GPL(fsl_mc_object_free);
7573
7574 /*
7575 - * Initialize the interrupt pool associated with a MC bus.
7576 - * It allocates a block of IRQs from the GIC-ITS
7577 + * A DPRC and the devices in the DPRC all share the same GIC-ITS device
7578 + * ID. A block of IRQs is pre-allocated and maintained in a pool
7579 + * from which devices can allocate them when needed.
7580 + */
7581 +
7582 +/*
7583 + * Initialize the interrupt pool associated with an fsl-mc bus.
7584 + * It allocates a block of IRQs from the GIC-ITS.
7585 */
7586 int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus,
7587 unsigned int irq_count)
7588 @@ -395,7 +398,7 @@ int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus,
7589 EXPORT_SYMBOL_GPL(fsl_mc_populate_irq_pool);
7590
7591 /**
7592 - * Teardown the interrupt pool associated with an MC bus.
7593 + * Teardown the interrupt pool associated with an fsl-mc bus.
7594 * It frees the IRQs that were allocated to the pool, back to the GIC-ITS.
7595 */
7596 void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus)
7597 @@ -422,11 +425,7 @@ void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus)
7598 EXPORT_SYMBOL_GPL(fsl_mc_cleanup_irq_pool);
7599
7600 /**
7601 - * It allocates the IRQs required by a given MC object device. The
7602 - * IRQs are allocated from the interrupt pool associated with the
7603 - * MC bus that contains the device, if the device is not a DPRC device.
7604 - * Otherwise, the IRQs are allocated from the interrupt pool associated
7605 - * with the MC bus that represents the DPRC device itself.
7606 + * Allocate the IRQs required by a given fsl-mc device.
7607 */
7608 int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev)
7609 {
7610 @@ -495,8 +494,7 @@ int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev)
7611 EXPORT_SYMBOL_GPL(fsl_mc_allocate_irqs);
7612
7613 /*
7614 - * It frees the IRQs that were allocated for a MC object device, by
7615 - * returning them to the corresponding interrupt pool.
7616 + * Frees the IRQs that were allocated for an fsl-mc device.
7617 */
7618 void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev)
7619 {
7620 @@ -605,7 +603,7 @@ static int fsl_mc_allocator_probe(struct fsl_mc_device *mc_dev)
7621 return error;
7622
7623 dev_dbg(&mc_dev->dev,
7624 - "Allocatable MC object device bound to fsl_mc_allocator driver");
7625 + "Allocatable fsl-mc device bound to fsl_mc_allocator driver");
7626 return 0;
7627 }
7628
7629 @@ -627,7 +625,7 @@ static int fsl_mc_allocator_remove(struct fsl_mc_device *mc_dev)
7630 }
7631
7632 dev_dbg(&mc_dev->dev,
7633 - "Allocatable MC object device unbound from fsl_mc_allocator driver");
7634 + "Allocatable fsl-mc device unbound from fsl_mc_allocator driver");
7635 return 0;
7636 }
7637
7638 diff --git a/drivers/staging/fsl-mc/bus/fsl-mc-bus.c b/drivers/staging/fsl-mc/bus/fsl-mc-bus.c
7639 index 44f64b6f..30a48df3 100644
7640 --- a/drivers/staging/fsl-mc/bus/fsl-mc-bus.c
7641 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-bus.c
7642 @@ -1,7 +1,7 @@
7643 /*
7644 * Freescale Management Complex (MC) bus driver
7645 *
7646 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
7647 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
7648 * Author: German Rivera <German.Rivera@freescale.com>
7649 *
7650 * This file is licensed under the terms of the GNU General Public
7651 @@ -9,6 +9,8 @@
7652 * warranty of any kind, whether express or implied.
7653 */
7654
7655 +#define pr_fmt(fmt) "fsl-mc: " fmt
7656 +
7657 #include <linux/module.h>
7658 #include <linux/of_device.h>
7659 #include <linux/of_address.h>
7660 @@ -25,8 +27,6 @@
7661 #include "fsl-mc-private.h"
7662 #include "dprc-cmd.h"
7663
7664 -static struct kmem_cache *mc_dev_cache;
7665 -
7666 /**
7667 * Default DMA mask for devices on a fsl-mc bus
7668 */
7669 @@ -34,7 +34,7 @@ static struct kmem_cache *mc_dev_cache;
7670
7671 /**
7672 * struct fsl_mc - Private data of a "fsl,qoriq-mc" platform device
7673 - * @root_mc_bus_dev: MC object device representing the root DPRC
7674 + * @root_mc_bus_dev: fsl-mc device representing the root DPRC
7675 * @num_translation_ranges: number of entries in addr_translation_ranges
7676 * @translation_ranges: array of bus to system address translation ranges
7677 */
7678 @@ -62,8 +62,8 @@ struct fsl_mc_addr_translation_range {
7679
7680 /**
7681 * fsl_mc_bus_match - device to driver matching callback
7682 - * @dev: the MC object device structure to match against
7683 - * @drv: the device driver to search for matching MC object device id
7684 + * @dev: the fsl-mc device to match against
7685 + * @drv: the device driver to search for matching fsl-mc object type
7686 * structures
7687 *
7688 * Returns 1 on success, 0 otherwise.
7689 @@ -75,8 +75,11 @@ static int fsl_mc_bus_match(struct device *dev, struct device_driver *drv)
7690 struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(drv);
7691 bool found = false;
7692
7693 - if (WARN_ON(!fsl_mc_bus_exists()))
7694 + /* When driver_override is set, only bind to the matching driver */
7695 + if (mc_dev->driver_override) {
7696 + found = !strcmp(mc_dev->driver_override, mc_drv->driver.name);
7697 goto out;
7698 + }
7699
7700 if (!mc_drv->match_id_table)
7701 goto out;
7702 @@ -91,7 +94,7 @@ static int fsl_mc_bus_match(struct device *dev, struct device_driver *drv)
7703
7704 /*
7705 * Traverse the match_id table of the given driver, trying to find
7706 - * a matching for the given MC object device.
7707 + * a matching for the given device.
7708 */
7709 for (id = mc_drv->match_id_table; id->vendor != 0x0; id++) {
7710 if (id->vendor == mc_dev->obj_desc.vendor &&
7711 @@ -132,23 +135,141 @@ static ssize_t modalias_show(struct device *dev, struct device_attribute *attr,
7712 }
7713 static DEVICE_ATTR_RO(modalias);
7714
7715 +static ssize_t rescan_store(struct device *dev,
7716 + struct device_attribute *attr,
7717 + const char *buf, size_t count)
7718 +{
7719 + unsigned long val;
7720 + unsigned int irq_count;
7721 + struct fsl_mc_device *root_mc_dev;
7722 + struct fsl_mc_bus *root_mc_bus;
7723 +
7724 + if (!fsl_mc_is_root_dprc(dev))
7725 + return -EINVAL;
7726 +
7727 + root_mc_dev = to_fsl_mc_device(dev);
7728 + root_mc_bus = to_fsl_mc_bus(root_mc_dev);
7729 +
7730 + if (kstrtoul(buf, 0, &val) < 0)
7731 + return -EINVAL;
7732 +
7733 + if (val) {
7734 + mutex_lock(&root_mc_bus->scan_mutex);
7735 + dprc_scan_objects(root_mc_dev, NULL, &irq_count);
7736 + mutex_unlock(&root_mc_bus->scan_mutex);
7737 + }
7738 +
7739 + return count;
7740 +}
7741 +static DEVICE_ATTR_WO(rescan);
7742 +
7743 +static ssize_t driver_override_store(struct device *dev,
7744 + struct device_attribute *attr,
7745 + const char *buf, size_t count)
7746 +{
7747 + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
7748 + const char *driver_override, *old = mc_dev->driver_override;
7749 + char *cp;
7750 +
7751 + if (WARN_ON(dev->bus != &fsl_mc_bus_type))
7752 + return -EINVAL;
7753 +
7754 + if (count >= (PAGE_SIZE - 1))
7755 + return -EINVAL;
7756 +
7757 + driver_override = kstrndup(buf, count, GFP_KERNEL);
7758 + if (!driver_override)
7759 + return -ENOMEM;
7760 +
7761 + cp = strchr(driver_override, '\n');
7762 + if (cp)
7763 + *cp = '\0';
7764 +
7765 + if (strlen(driver_override)) {
7766 + mc_dev->driver_override = driver_override;
7767 + } else {
7768 + kfree(driver_override);
7769 + mc_dev->driver_override = NULL;
7770 + }
7771 +
7772 + kfree(old);
7773 +
7774 + return count;
7775 +}
7776 +
7777 +static ssize_t driver_override_show(struct device *dev,
7778 + struct device_attribute *attr, char *buf)
7779 +{
7780 + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
7781 +
7782 + return snprintf(buf, PAGE_SIZE, "%s\n", mc_dev->driver_override);
7783 +}
7784 +static DEVICE_ATTR_RW(driver_override);
7785 +
7786 static struct attribute *fsl_mc_dev_attrs[] = {
7787 &dev_attr_modalias.attr,
7788 + &dev_attr_rescan.attr,
7789 + &dev_attr_driver_override.attr,
7790 NULL,
7791 };
7792
7793 ATTRIBUTE_GROUPS(fsl_mc_dev);
7794
7795 +static int scan_fsl_mc_bus(struct device *dev, void *data)
7796 +{
7797 + unsigned int irq_count;
7798 + struct fsl_mc_device *root_mc_dev;
7799 + struct fsl_mc_bus *root_mc_bus;
7800 +
7801 + if (fsl_mc_is_root_dprc(dev)) {
7802 + root_mc_dev = to_fsl_mc_device(dev);
7803 + root_mc_bus = to_fsl_mc_bus(root_mc_dev);
7804 + mutex_lock(&root_mc_bus->scan_mutex);
7805 + dprc_scan_objects(root_mc_dev, NULL, &irq_count);
7806 + mutex_unlock(&root_mc_bus->scan_mutex);
7807 + }
7808 +
7809 + return 0;
7810 +}
7811 +
7812 +static ssize_t bus_rescan_store(struct bus_type *bus,
7813 + const char *buf, size_t count)
7814 +{
7815 + unsigned long val;
7816 +
7817 + if (kstrtoul(buf, 0, &val) < 0)
7818 + return -EINVAL;
7819 +
7820 + if (val)
7821 + bus_for_each_dev(bus, NULL, NULL, scan_fsl_mc_bus);
7822 +
7823 + return count;
7824 +}
7825 +static BUS_ATTR(rescan, (S_IWUSR | S_IWGRP), NULL, bus_rescan_store);
7826 +
7827 +static struct attribute *fsl_mc_bus_attrs[] = {
7828 + &bus_attr_rescan.attr,
7829 + NULL,
7830 +};
7831 +
7832 +static const struct attribute_group fsl_mc_bus_group = {
7833 + .attrs = fsl_mc_bus_attrs,
7834 +};
7835 +
7836 +static const struct attribute_group *fsl_mc_bus_groups[] = {
7837 + &fsl_mc_bus_group,
7838 + NULL,
7839 +};
7840 +
7841 struct bus_type fsl_mc_bus_type = {
7842 .name = "fsl-mc",
7843 .match = fsl_mc_bus_match,
7844 .uevent = fsl_mc_bus_uevent,
7845 .dev_groups = fsl_mc_dev_groups,
7846 + .bus_groups = fsl_mc_bus_groups,
7847 };
7848 EXPORT_SYMBOL_GPL(fsl_mc_bus_type);
7849
7850 -static atomic_t root_dprc_count = ATOMIC_INIT(0);
7851 -
7852 static int fsl_mc_driver_probe(struct device *dev)
7853 {
7854 struct fsl_mc_driver *mc_drv;
7855 @@ -164,8 +285,7 @@ static int fsl_mc_driver_probe(struct device *dev)
7856
7857 error = mc_drv->probe(mc_dev);
7858 if (error < 0) {
7859 - dev_err(dev, "MC object device probe callback failed: %d\n",
7860 - error);
7861 + dev_err(dev, "%s failed: %d\n", __func__, error);
7862 return error;
7863 }
7864
7865 @@ -183,9 +303,7 @@ static int fsl_mc_driver_remove(struct device *dev)
7866
7867 error = mc_drv->remove(mc_dev);
7868 if (error < 0) {
7869 - dev_err(dev,
7870 - "MC object device remove callback failed: %d\n",
7871 - error);
7872 + dev_err(dev, "%s failed: %d\n", __func__, error);
7873 return error;
7874 }
7875
7876 @@ -232,8 +350,6 @@ int __fsl_mc_driver_register(struct fsl_mc_driver *mc_driver,
7877 return error;
7878 }
7879
7880 - pr_info("MC object device driver %s registered\n",
7881 - mc_driver->driver.name);
7882 return 0;
7883 }
7884 EXPORT_SYMBOL_GPL(__fsl_mc_driver_register);
7885 @@ -248,15 +364,6 @@ void fsl_mc_driver_unregister(struct fsl_mc_driver *mc_driver)
7886 }
7887 EXPORT_SYMBOL_GPL(fsl_mc_driver_unregister);
7888
7889 -/**
7890 - * fsl_mc_bus_exists - check if a root dprc exists
7891 - */
7892 -bool fsl_mc_bus_exists(void)
7893 -{
7894 - return atomic_read(&root_dprc_count) > 0;
7895 -}
7896 -EXPORT_SYMBOL_GPL(fsl_mc_bus_exists);
7897 -
7898 /**
7899 * fsl_mc_get_root_dprc - function to traverse to the root dprc
7900 */
7901 @@ -315,21 +422,6 @@ static int get_dprc_icid(struct fsl_mc_io *mc_io,
7902 return error;
7903 }
7904
7905 -static int get_dprc_version(struct fsl_mc_io *mc_io,
7906 - int container_id, u16 *major, u16 *minor)
7907 -{
7908 - struct dprc_attributes attr;
7909 - int error;
7910 -
7911 - error = get_dprc_attr(mc_io, container_id, &attr);
7912 - if (error == 0) {
7913 - *major = attr.version.major;
7914 - *minor = attr.version.minor;
7915 - }
7916 -
7917 - return error;
7918 -}
7919 -
7920 static int translate_mc_addr(struct fsl_mc_device *mc_dev,
7921 enum dprc_region_type mc_region_type,
7922 u64 mc_offset, phys_addr_t *phys_addr)
7923 @@ -451,18 +543,37 @@ bool fsl_mc_is_root_dprc(struct device *dev)
7924 return dev == root_dprc_dev;
7925 }
7926
7927 +static void fsl_mc_device_release(struct device *dev)
7928 +{
7929 + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
7930 + struct fsl_mc_bus *mc_bus = NULL;
7931 +
7932 + kfree(mc_dev->regions);
7933 +
7934 + if (strcmp(mc_dev->obj_desc.type, "dprc") == 0)
7935 + mc_bus = to_fsl_mc_bus(mc_dev);
7936 +
7937 + if (mc_bus)
7938 + kfree(mc_bus);
7939 + else
7940 + kfree(mc_dev);
7941 +}
7942 +
7943 /**
7944 - * Add a newly discovered MC object device to be visible in Linux
7945 + * Add a newly discovered fsl-mc device to be visible in Linux
7946 */
7947 int fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
7948 struct fsl_mc_io *mc_io,
7949 struct device *parent_dev,
7950 + const char *driver_override,
7951 struct fsl_mc_device **new_mc_dev)
7952 {
7953 int error;
7954 struct fsl_mc_device *mc_dev = NULL;
7955 struct fsl_mc_bus *mc_bus = NULL;
7956 struct fsl_mc_device *parent_mc_dev;
7957 + struct device *fsl_mc_platform_dev;
7958 + struct device_node *fsl_mc_platform_node;
7959
7960 if (dev_is_fsl_mc(parent_dev))
7961 parent_mc_dev = to_fsl_mc_device(parent_dev);
7962 @@ -473,7 +584,7 @@ int fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
7963 /*
7964 * Allocate an MC bus device object:
7965 */
7966 - mc_bus = devm_kzalloc(parent_dev, sizeof(*mc_bus), GFP_KERNEL);
7967 + mc_bus = kzalloc(sizeof(*mc_bus), GFP_KERNEL);
7968 if (!mc_bus)
7969 return -ENOMEM;
7970
7971 @@ -482,16 +593,30 @@ int fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
7972 /*
7973 * Allocate a regular fsl_mc_device object:
7974 */
7975 - mc_dev = kmem_cache_zalloc(mc_dev_cache, GFP_KERNEL);
7976 + mc_dev = kzalloc(sizeof(*mc_dev), GFP_KERNEL);
7977 if (!mc_dev)
7978 return -ENOMEM;
7979 }
7980
7981 mc_dev->obj_desc = *obj_desc;
7982 mc_dev->mc_io = mc_io;
7983 +
7984 + if (driver_override) {
7985 + /*
7986 + * We trust driver_override, so we don't need to use
7987 + * kstrndup() here
7988 + */
7989 + mc_dev->driver_override = kstrdup(driver_override, GFP_KERNEL);
7990 + if (!mc_dev->driver_override) {
7991 + error = -ENOMEM;
7992 + goto error_cleanup_dev;
7993 + }
7994 + }
7995 +
7996 device_initialize(&mc_dev->dev);
7997 mc_dev->dev.parent = parent_dev;
7998 mc_dev->dev.bus = &fsl_mc_bus_type;
7999 + mc_dev->dev.release = fsl_mc_device_release;
8000 dev_set_name(&mc_dev->dev, "%s.%d", obj_desc->type, obj_desc->id);
8001
8002 if (strcmp(obj_desc->type, "dprc") == 0) {
8003 @@ -524,8 +649,6 @@ int fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
8004 }
8005
8006 mc_io2 = mc_io;
8007 -
8008 - atomic_inc(&root_dprc_count);
8009 }
8010
8011 error = get_dprc_icid(mc_io2, obj_desc->id, &mc_dev->icid);
8012 @@ -533,8 +656,8 @@ int fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
8013 goto error_cleanup_dev;
8014 } else {
8015 /*
8016 - * A non-DPRC MC object device has to be a child of another
8017 - * MC object (specifically a DPRC object)
8018 + * A non-DPRC object has to be a child of a DPRC, use the
8019 + * parent's ICID and interrupt domain.
8020 */
8021 mc_dev->icid = parent_mc_dev->icid;
8022 mc_dev->dma_mask = FSL_MC_DEFAULT_DMA_MASK;
8023 @@ -556,9 +679,14 @@ int fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
8024 goto error_cleanup_dev;
8025 }
8026
8027 - /* Objects are coherent, unless 'no shareability' flag set. */
8028 - if (!(obj_desc->flags & DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY))
8029 - arch_setup_dma_ops(&mc_dev->dev, 0, 0, NULL, true);
8030 + fsl_mc_platform_dev = &mc_dev->dev;
8031 + while (dev_is_fsl_mc(fsl_mc_platform_dev))
8032 + fsl_mc_platform_dev = fsl_mc_platform_dev->parent;
8033 + fsl_mc_platform_node = fsl_mc_platform_dev->of_node;
8034 +
8035 + /* Set up the iommu configuration for the devices. */
8036 + fsl_mc_dma_configure(mc_dev, fsl_mc_platform_node,
8037 + !(obj_desc->flags & DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY));
8038
8039 /*
8040 * The device-specific probe callback will get invoked by device_add()
8041 @@ -571,9 +699,7 @@ int fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
8042 goto error_cleanup_dev;
8043 }
8044
8045 - (void)get_device(&mc_dev->dev);
8046 - dev_dbg(parent_dev, "Added MC object device %s\n",
8047 - dev_name(&mc_dev->dev));
8048 + dev_dbg(parent_dev, "added %s\n", dev_name(&mc_dev->dev));
8049
8050 *new_mc_dev = mc_dev;
8051 return 0;
8052 @@ -581,47 +707,34 @@ int fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
8053 error_cleanup_dev:
8054 kfree(mc_dev->regions);
8055 if (mc_bus)
8056 - devm_kfree(parent_dev, mc_bus);
8057 + kfree(mc_bus);
8058 else
8059 - kmem_cache_free(mc_dev_cache, mc_dev);
8060 + kfree(mc_dev);
8061
8062 return error;
8063 }
8064 EXPORT_SYMBOL_GPL(fsl_mc_device_add);
8065
8066 /**
8067 - * fsl_mc_device_remove - Remove a MC object device from being visible to
8068 + * fsl_mc_device_remove - Remove an fsl-mc device from being visible to
8069 * Linux
8070 *
8071 - * @mc_dev: Pointer to a MC object device object
8072 + * @mc_dev: Pointer to an fsl-mc device
8073 */
8074 void fsl_mc_device_remove(struct fsl_mc_device *mc_dev)
8075 {
8076 - struct fsl_mc_bus *mc_bus = NULL;
8077 -
8078 - kfree(mc_dev->regions);
8079 + kfree(mc_dev->driver_override);
8080 + mc_dev->driver_override = NULL;
8081
8082 /*
8083 * The device-specific remove callback will get invoked by device_del()
8084 */
8085 device_del(&mc_dev->dev);
8086 - put_device(&mc_dev->dev);
8087
8088 - if (strcmp(mc_dev->obj_desc.type, "dprc") == 0) {
8089 - mc_bus = to_fsl_mc_bus(mc_dev);
8090 + if (strcmp(mc_dev->obj_desc.type, "dprc") != 0)
8091 + mc_dev->dev.iommu_fwspec = NULL;
8092
8093 - if (fsl_mc_is_root_dprc(&mc_dev->dev)) {
8094 - if (atomic_read(&root_dprc_count) > 0)
8095 - atomic_dec(&root_dprc_count);
8096 - else
8097 - WARN_ON(1);
8098 - }
8099 - }
8100 -
8101 - if (mc_bus)
8102 - devm_kfree(mc_dev->dev.parent, mc_bus);
8103 - else
8104 - kmem_cache_free(mc_dev_cache, mc_dev);
8105 + put_device(&mc_dev->dev);
8106 }
8107 EXPORT_SYMBOL_GPL(fsl_mc_device_remove);
8108
8109 @@ -629,8 +742,7 @@ static int parse_mc_ranges(struct device *dev,
8110 int *paddr_cells,
8111 int *mc_addr_cells,
8112 int *mc_size_cells,
8113 - const __be32 **ranges_start,
8114 - u8 *num_ranges)
8115 + const __be32 **ranges_start)
8116 {
8117 const __be32 *prop;
8118 int range_tuple_cell_count;
8119 @@ -643,8 +755,6 @@ static int parse_mc_ranges(struct device *dev,
8120 dev_warn(dev,
8121 "missing or empty ranges property for device tree node '%s'\n",
8122 mc_node->name);
8123 -
8124 - *num_ranges = 0;
8125 return 0;
8126 }
8127
8128 @@ -671,8 +781,7 @@ static int parse_mc_ranges(struct device *dev,
8129 return -EINVAL;
8130 }
8131
8132 - *num_ranges = ranges_len / tuple_len;
8133 - return 0;
8134 + return ranges_len / tuple_len;
8135 }
8136
8137 static int get_mc_addr_translation_ranges(struct device *dev,
8138 @@ -680,7 +789,7 @@ static int get_mc_addr_translation_ranges(struct device *dev,
8139 **ranges,
8140 u8 *num_ranges)
8141 {
8142 - int error;
8143 + int ret;
8144 int paddr_cells;
8145 int mc_addr_cells;
8146 int mc_size_cells;
8147 @@ -688,16 +797,16 @@ static int get_mc_addr_translation_ranges(struct device *dev,
8148 const __be32 *ranges_start;
8149 const __be32 *cell;
8150
8151 - error = parse_mc_ranges(dev,
8152 + ret = parse_mc_ranges(dev,
8153 &paddr_cells,
8154 &mc_addr_cells,
8155 &mc_size_cells,
8156 - &ranges_start,
8157 - num_ranges);
8158 - if (error < 0)
8159 - return error;
8160 + &ranges_start);
8161 + if (ret < 0)
8162 + return ret;
8163
8164 - if (!(*num_ranges)) {
8165 + *num_ranges = ret;
8166 + if (!ret) {
8167 /*
8168 * Missing or empty ranges property ("ranges;") for the
8169 * 'fsl,qoriq-mc' node. In this case, identity mapping
8170 @@ -749,8 +858,6 @@ static int fsl_mc_bus_probe(struct platform_device *pdev)
8171 struct mc_version mc_version;
8172 struct resource res;
8173
8174 - dev_info(&pdev->dev, "Root MC bus device probed");
8175 -
8176 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
8177 if (!mc)
8178 return -ENOMEM;
8179 @@ -783,8 +890,7 @@ static int fsl_mc_bus_probe(struct platform_device *pdev)
8180 goto error_cleanup_mc_io;
8181 }
8182
8183 - dev_info(&pdev->dev,
8184 - "Freescale Management Complex Firmware version: %u.%u.%u\n",
8185 + dev_info(&pdev->dev, "MC firmware version: %u.%u.%u\n",
8186 mc_version.major, mc_version.minor, mc_version.revision);
8187
8188 error = get_mc_addr_translation_ranges(&pdev->dev,
8189 @@ -793,16 +899,17 @@ static int fsl_mc_bus_probe(struct platform_device *pdev)
8190 if (error < 0)
8191 goto error_cleanup_mc_io;
8192
8193 - error = dpmng_get_container_id(mc_io, 0, &container_id);
8194 + error = dprc_get_container_id(mc_io, 0, &container_id);
8195 if (error < 0) {
8196 dev_err(&pdev->dev,
8197 - "dpmng_get_container_id() failed: %d\n", error);
8198 + "dprc_get_container_id() failed: %d\n", error);
8199 goto error_cleanup_mc_io;
8200 }
8201
8202 memset(&obj_desc, 0, sizeof(struct dprc_obj_desc));
8203 - error = get_dprc_version(mc_io, container_id,
8204 - &obj_desc.ver_major, &obj_desc.ver_minor);
8205 + error = dprc_get_api_version(mc_io, 0,
8206 + &obj_desc.ver_major,
8207 + &obj_desc.ver_minor);
8208 if (error < 0)
8209 goto error_cleanup_mc_io;
8210
8211 @@ -812,7 +919,8 @@ static int fsl_mc_bus_probe(struct platform_device *pdev)
8212 obj_desc.irq_count = 1;
8213 obj_desc.region_count = 0;
8214
8215 - error = fsl_mc_device_add(&obj_desc, mc_io, &pdev->dev, &mc_bus_dev);
8216 + error = fsl_mc_device_add(&obj_desc, mc_io, &pdev->dev, NULL,
8217 + &mc_bus_dev);
8218 if (error < 0)
8219 goto error_cleanup_mc_io;
8220
8221 @@ -840,7 +948,6 @@ static int fsl_mc_bus_remove(struct platform_device *pdev)
8222 fsl_destroy_mc_io(mc->root_mc_bus_dev->mc_io);
8223 mc->root_mc_bus_dev->mc_io = NULL;
8224
8225 - dev_info(&pdev->dev, "Root MC bus device removed");
8226 return 0;
8227 }
8228
8229 @@ -865,22 +972,12 @@ static int __init fsl_mc_bus_driver_init(void)
8230 {
8231 int error;
8232
8233 - mc_dev_cache = kmem_cache_create("fsl_mc_device",
8234 - sizeof(struct fsl_mc_device), 0, 0,
8235 - NULL);
8236 - if (!mc_dev_cache) {
8237 - pr_err("Could not create fsl_mc_device cache\n");
8238 - return -ENOMEM;
8239 - }
8240 -
8241 error = bus_register(&fsl_mc_bus_type);
8242 if (error < 0) {
8243 - pr_err("fsl-mc bus type registration failed: %d\n", error);
8244 + pr_err("bus type registration failed: %d\n", error);
8245 goto error_cleanup_cache;
8246 }
8247
8248 - pr_info("fsl-mc bus type registered\n");
8249 -
8250 error = platform_driver_register(&fsl_mc_bus_driver);
8251 if (error < 0) {
8252 pr_err("platform_driver_register() failed: %d\n", error);
8253 @@ -914,7 +1011,6 @@ static int __init fsl_mc_bus_driver_init(void)
8254 bus_unregister(&fsl_mc_bus_type);
8255
8256 error_cleanup_cache:
8257 - kmem_cache_destroy(mc_dev_cache);
8258 return error;
8259 }
8260 postcore_initcall(fsl_mc_bus_driver_init);
8261 diff --git a/drivers/staging/fsl-mc/bus/fsl-mc-iommu.c b/drivers/staging/fsl-mc/bus/fsl-mc-iommu.c
8262 new file mode 100644
8263 index 00000000..86b2cd84
8264 --- /dev/null
8265 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-iommu.c
8266 @@ -0,0 +1,104 @@
8267 +/*
8268 + * Copyright 2016-17 NXP
8269 + * Author: Nipun Gupta <nipun.gupta@nxp.com>
8270 + *
8271 + * This file is licensed under the terms of the GNU General Public
8272 + * License version 2. This program is licensed "as is" without any
8273 + * warranty of any kind, whether express or implied.
8274 + */
8275 +
8276 +#include <linux/iommu.h>
8277 +#include <linux/of.h>
8278 +#include <linux/of_iommu.h>
8279 +#include "../include/mc.h"
8280 +
8281 +/* Setup the IOMMU for the DPRC container */
8282 +static const struct iommu_ops
8283 +*fsl_mc_iommu_configure(struct fsl_mc_device *mc_dev,
8284 + struct device_node *fsl_mc_platform_node)
8285 +{
8286 + struct of_phandle_args iommu_spec;
8287 + const struct iommu_ops *ops;
8288 + u32 iommu_phandle;
8289 + struct device_node *iommu_node;
8290 + const __be32 *map = NULL;
8291 + int iommu_cells, map_len, ret;
8292 +
8293 + map = of_get_property(fsl_mc_platform_node, "iommu-map", &map_len);
8294 + if (!map)
8295 + return NULL;
8296 +
8297 + ops = mc_dev->dev.bus->iommu_ops;
8298 + if (!ops || !ops->of_xlate)
8299 + return NULL;
8300 +
8301 + iommu_phandle = be32_to_cpup(map + 1);
8302 + iommu_node = of_find_node_by_phandle(iommu_phandle);
8303 +
8304 + if (of_property_read_u32(iommu_node, "#iommu-cells", &iommu_cells)) {
8305 + pr_err("%s: missing #iommu-cells property\n", iommu_node->name);
8306 + return NULL;
8307 + }
8308 +
8309 + /* Initialize the fwspec */
8310 + ret = iommu_fwspec_init(&mc_dev->dev, &iommu_node->fwnode, ops);
8311 + if (ret)
8312 + return NULL;
8313 +
8314 + /*
8315 + * Fill in the required stream-id before calling the iommu's
8316 + * ops->xlate callback.
8317 + */
8318 + iommu_spec.np = iommu_node;
8319 + iommu_spec.args[0] = mc_dev->icid;
8320 + iommu_spec.args_count = 1;
8321 +
8322 + ret = ops->of_xlate(&mc_dev->dev, &iommu_spec);
8323 + if (ret)
8324 + return NULL;
8325 +
8326 + of_node_put(iommu_spec.np);
8327 +
8328 + return ops;
8329 +}
8330 +
8331 +/* Set up DMA configuration for fsl-mc devices */
8332 +void fsl_mc_dma_configure(struct fsl_mc_device *mc_dev,
8333 + struct device_node *fsl_mc_platform_node, int coherent)
8334 +{
8335 + const struct iommu_ops *ops;
8336 +
8337 + ops = fsl_mc_iommu_configure(mc_dev, fsl_mc_platform_node);
8338 +
8339 + mc_dev->dev.coherent_dma_mask = DMA_BIT_MASK(48);
8340 + mc_dev->dev.dma_mask = &mc_dev->dev.coherent_dma_mask;
8341 + arch_setup_dma_ops(&mc_dev->dev, 0,
8342 + mc_dev->dev.coherent_dma_mask + 1, ops, coherent);
8343 +}
8344 +
8345 +/* Macro to get the container device of a MC device */
8346 +#define fsl_mc_cont_dev(_dev) ((to_fsl_mc_device(_dev)->flags & \
8347 + FSL_MC_IS_DPRC) ? (_dev) : ((_dev)->parent))
8348 +
8349 +/* Macro to check if a device is a container device */
8350 +#define is_cont_dev(_dev) (to_fsl_mc_device(_dev)->flags & FSL_MC_IS_DPRC)
8351 +
8352 +/* Get the IOMMU group for device on fsl-mc bus */
8353 +struct iommu_group *fsl_mc_device_group(struct device *dev)
8354 +{
8355 + struct device *cont_dev = fsl_mc_cont_dev(dev);
8356 + struct iommu_group *group;
8357 +
8358 + /* Container device is responsible for creating the iommu group */
8359 + if (is_cont_dev(dev)) {
8360 + group = iommu_group_alloc();
8361 + if (IS_ERR(group))
8362 + return NULL;
8363 + } else {
8364 + get_device(cont_dev);
8365 + group = iommu_group_get(cont_dev);
8366 + put_device(cont_dev);
8367 + }
8368 +
8369 + return group;
8370 +}
8371 diff --git a/drivers/staging/fsl-mc/bus/fsl-mc-msi.c b/drivers/staging/fsl-mc/bus/fsl-mc-msi.c
8372 index 3d46b1b1..b8b2c86e 100644
8373 --- a/drivers/staging/fsl-mc/bus/fsl-mc-msi.c
8374 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-msi.c
8375 @@ -1,7 +1,7 @@
8376 /*
8377 * Freescale Management Complex (MC) bus driver MSI support
8378 *
8379 - * Copyright (C) 2015 Freescale Semiconductor, Inc.
8380 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
8381 * Author: German Rivera <German.Rivera@freescale.com>
8382 *
8383 * This file is licensed under the terms of the GNU General Public
8384 @@ -17,6 +17,7 @@
8385 #include <linux/irqdomain.h>
8386 #include <linux/msi.h>
8387 #include "../include/mc-bus.h"
8388 +#include "fsl-mc-private.h"
8389
8390 /*
8391 * Generate a unique ID identifying the interrupt (only used within the MSI
8392 diff --git a/drivers/staging/fsl-mc/bus/fsl-mc-private.h b/drivers/staging/fsl-mc/bus/fsl-mc-private.h
8393 index d459c267..e08b8843 100644
8394 --- a/drivers/staging/fsl-mc/bus/fsl-mc-private.h
8395 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-private.h
8396 @@ -10,13 +10,15 @@
8397 #ifndef _FSL_MC_PRIVATE_H_
8398 #define _FSL_MC_PRIVATE_H_
8399
8400 +#include "../include/mc.h"
8401 +#include "../include/mc-bus.h"
8402 +
8403 int __must_check fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
8404 struct fsl_mc_io *mc_io,
8405 struct device *parent_dev,
8406 + const char *driver_override,
8407 struct fsl_mc_device **new_mc_dev);
8408
8409 -void fsl_mc_device_remove(struct fsl_mc_device *mc_dev);
8410 -
8411 int __init dprc_driver_init(void);
8412
8413 void dprc_driver_exit(void);
8414 diff --git a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
8415 index 7a6ac640..49127acb 100644
8416 --- a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
8417 +++ b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
8418 @@ -1,7 +1,7 @@
8419 /*
8420 * Freescale Management Complex (MC) bus driver MSI support
8421 *
8422 - * Copyright (C) 2015 Freescale Semiconductor, Inc.
8423 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
8424 * Author: German Rivera <German.Rivera@freescale.com>
8425 *
8426 * This file is licensed under the terms of the GNU General Public
8427 @@ -17,9 +17,10 @@
8428 #include <linux/of.h>
8429 #include <linux/of_irq.h>
8430 #include "../include/mc-bus.h"
8431 +#include "fsl-mc-private.h"
8432
8433 static struct irq_chip its_msi_irq_chip = {
8434 - .name = "fsl-mc-bus-msi",
8435 + .name = "ITS-fMSI",
8436 .irq_mask = irq_chip_mask_parent,
8437 .irq_unmask = irq_chip_unmask_parent,
8438 .irq_eoi = irq_chip_eoi_parent,
8439 @@ -51,7 +52,7 @@ static int its_fsl_mc_msi_prepare(struct irq_domain *msi_domain,
8440 return msi_info->ops->msi_prepare(msi_domain->parent, dev, nvec, info);
8441 }
8442
8443 -static struct msi_domain_ops its_fsl_mc_msi_ops = {
8444 +static struct msi_domain_ops its_fsl_mc_msi_ops __ro_after_init = {
8445 .msi_prepare = its_fsl_mc_msi_prepare,
8446 };
8447
8448 @@ -94,8 +95,8 @@ int __init its_fsl_mc_msi_init(void)
8449 continue;
8450 }
8451
8452 - WARN_ON(mc_msi_domain->
8453 - host_data != &its_fsl_mc_msi_domain_info);
8454 + WARN_ON(mc_msi_domain->host_data !=
8455 + &its_fsl_mc_msi_domain_info);
8456
8457 pr_info("fsl-mc MSI: %s domain created\n", np->full_name);
8458 }
8459 diff --git a/drivers/staging/fsl-mc/bus/mc-io.c b/drivers/staging/fsl-mc/bus/mc-io.c
8460 index 798c965f..d66b87f0 100644
8461 --- a/drivers/staging/fsl-mc/bus/mc-io.c
8462 +++ b/drivers/staging/fsl-mc/bus/mc-io.c
8463 @@ -1,4 +1,5 @@
8464 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
8465 +/*
8466 + * Copyright 2013-2016 Freescale Semiconductor Inc.
8467 *
8468 * Redistribution and use in source and binary forms, with or without
8469 * modification, are permitted provided that the following conditions are met:
8470 @@ -11,7 +12,6 @@
8471 * names of any contributors may be used to endorse or promote products
8472 * derived from this software without specific prior written permission.
8473 *
8474 - *
8475 * ALTERNATIVELY, this software may be distributed under the terms of the
8476 * GNU General Public License ("GPL") as published by the Free Software
8477 * Foundation, either version 2 of that License or (at your option) any
8478 diff --git a/drivers/staging/fsl-mc/bus/mc-ioctl.h b/drivers/staging/fsl-mc/bus/mc-ioctl.h
8479 new file mode 100644
8480 index 00000000..8ac502a1
8481 --- /dev/null
8482 +++ b/drivers/staging/fsl-mc/bus/mc-ioctl.h
8483 @@ -0,0 +1,22 @@
8484 +/*
8485 + * Freescale Management Complex (MC) ioclt interface
8486 + *
8487 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
8488 + * Author: Lijun Pan <Lijun.Pan@freescale.com>
8489 + *
8490 + * This file is licensed under the terms of the GNU General Public
8491 + * License version 2. This program is licensed "as is" without any
8492 + * warranty of any kind, whether express or implied.
8493 + */
8494 +#ifndef _FSL_MC_IOCTL_H_
8495 +#define _FSL_MC_IOCTL_H_
8496 +
8497 +#include <linux/ioctl.h>
8498 +#include "../include/mc-sys.h"
8499 +
8500 +#define RESTOOL_IOCTL_TYPE 'R'
8501 +
8502 +#define RESTOOL_SEND_MC_COMMAND \
8503 + _IOWR(RESTOOL_IOCTL_TYPE, 0xE0, struct mc_command)
8504 +
8505 +#endif /* _FSL_MC_IOCTL_H_ */
8506 diff --git a/drivers/staging/fsl-mc/bus/mc-restool.c b/drivers/staging/fsl-mc/bus/mc-restool.c
8507 new file mode 100644
8508 index 00000000..d5330b68
8509 --- /dev/null
8510 +++ b/drivers/staging/fsl-mc/bus/mc-restool.c
8511 @@ -0,0 +1,405 @@
8512 +/*
8513 + * Freescale Management Complex (MC) restool driver
8514 + *
8515 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
8516 + * Author: Lijun Pan <Lijun.Pan@freescale.com>
8517 + *
8518 + * This file is licensed under the terms of the GNU General Public
8519 + * License version 2. This program is licensed "as is" without any
8520 + * warranty of any kind, whether express or implied.
8521 + */
8522 +
8523 +#include "../include/mc.h"
8524 +#include <linux/module.h>
8525 +#include <linux/fs.h>
8526 +#include <linux/miscdevice.h>
8527 +#include <linux/mm.h>
8528 +#include <linux/slab.h>
8529 +#include <linux/uaccess.h>
8530 +#include <linux/mutex.h>
8531 +#include <linux/platform_device.h>
8532 +#include "mc-ioctl.h"
8533 +#include "../include/mc-sys.h"
8534 +#include "../include/mc-bus.h"
8535 +#include "../include/mc-cmd.h"
8536 +#include "../include/dpmng.h"
8537 +
8538 +/**
8539 + * Maximum number of DPRCs that can be opened at the same time
8540 + */
8541 +#define MAX_DPRC_HANDLES 64
8542 +
8543 +/**
8544 + * restool_misc - information associated with the newly added miscdevice
8545 + * @misc: newly created miscdevice associated with root dprc
8546 + * @miscdevt: device id of this miscdevice
8547 + * @list: a linked list node representing this miscdevcie
8548 + * @static_mc_io: pointer to the static MC I/O object used by the restool
8549 + * @dynamic_instance_count: number of dynamically created instances
8550 + * @static_instance_in_use: static instance is in use or not
8551 + * @mutex: mutex lock to serialze the open/release operations
8552 + * @dev: root dprc associated with this miscdevice
8553 + */
8554 +struct restool_misc {
8555 + struct miscdevice misc;
8556 + dev_t miscdevt;
8557 + struct list_head list;
8558 + struct fsl_mc_io *static_mc_io;
8559 + u32 dynamic_instance_count;
8560 + bool static_instance_in_use;
8561 + struct mutex mutex; /* serialze the open/release operations */
8562 + struct device *dev;
8563 +};
8564 +
8565 +/**
8566 + * struct fsl_mc - Private data of a "fsl,qoriq-mc" platform device
8567 + * @root_mc_bus_dev: fsl-mc device representing the root DPRC
8568 + * @num_translation_ranges: number of entries in addr_translation_ranges
8569 + * @translation_ranges: array of bus to system address translation ranges
8570 + */
8571 +struct fsl_mc {
8572 + struct fsl_mc_device *root_mc_bus_dev;
8573 + u8 num_translation_ranges;
8574 + struct fsl_mc_addr_translation_range *translation_ranges;
8575 +};
8576 +
8577 +/*
8578 + * initialize a global list to link all
8579 + * the miscdevice nodes (struct restool_misc)
8580 + */
8581 +static LIST_HEAD(misc_list);
8582 +static DEFINE_MUTEX(misc_list_mutex);
8583 +
8584 +static int fsl_mc_restool_dev_open(struct inode *inode, struct file *filep)
8585 +{
8586 + struct fsl_mc_device *root_mc_dev;
8587 + int error;
8588 + struct fsl_mc_io *dynamic_mc_io = NULL;
8589 + struct restool_misc *restool_misc = NULL;
8590 + struct restool_misc *restool_misc_cursor;
8591 +
8592 + mutex_lock(&misc_list_mutex);
8593 +
8594 + list_for_each_entry(restool_misc_cursor, &misc_list, list) {
8595 + if (restool_misc_cursor->miscdevt == inode->i_rdev) {
8596 + restool_misc = restool_misc_cursor;
8597 + break;
8598 + }
8599 + }
8600 +
8601 + mutex_unlock(&misc_list_mutex);
8602 +
8603 + if (!restool_misc)
8604 + return -EINVAL;
8605 +
8606 + if (WARN_ON(!restool_misc->dev))
8607 + return -EINVAL;
8608 +
8609 + mutex_lock(&restool_misc->mutex);
8610 +
8611 + if (!restool_misc->static_instance_in_use) {
8612 + restool_misc->static_instance_in_use = true;
8613 + filep->private_data = restool_misc->static_mc_io;
8614 + } else {
8615 + dynamic_mc_io = kzalloc(sizeof(*dynamic_mc_io), GFP_KERNEL);
8616 + if (!dynamic_mc_io) {
8617 + error = -ENOMEM;
8618 + goto err_unlock;
8619 + }
8620 +
8621 + root_mc_dev = to_fsl_mc_device(restool_misc->dev);
8622 + error = fsl_mc_portal_allocate(root_mc_dev, 0, &dynamic_mc_io);
8623 + if (error < 0) {
8624 + pr_err("Not able to allocate MC portal\n");
8625 + goto free_dynamic_mc_io;
8626 + }
8627 + ++restool_misc->dynamic_instance_count;
8628 + filep->private_data = dynamic_mc_io;
8629 + }
8630 +
8631 + mutex_unlock(&restool_misc->mutex);
8632 +
8633 + return 0;
8634 +
8635 +free_dynamic_mc_io:
8636 + kfree(dynamic_mc_io);
8637 +err_unlock:
8638 + mutex_unlock(&restool_misc->mutex);
8639 +
8640 + return error;
8641 +}
8642 +
8643 +static int fsl_mc_restool_dev_release(struct inode *inode, struct file *filep)
8644 +{
8645 + struct fsl_mc_io *local_mc_io = filep->private_data;
8646 + struct restool_misc *restool_misc = NULL;
8647 + struct restool_misc *restool_misc_cursor;
8648 +
8649 + if (WARN_ON(!filep->private_data))
8650 + return -EINVAL;
8651 +
8652 + mutex_lock(&misc_list_mutex);
8653 +
8654 + list_for_each_entry(restool_misc_cursor, &misc_list, list) {
8655 + if (restool_misc_cursor->miscdevt == inode->i_rdev) {
8656 + restool_misc = restool_misc_cursor;
8657 + break;
8658 + }
8659 + }
8660 +
8661 + mutex_unlock(&misc_list_mutex);
8662 +
8663 + if (!restool_misc)
8664 + return -EINVAL;
8665 +
8666 + mutex_lock(&restool_misc->mutex);
8667 +
8668 + if (WARN_ON(restool_misc->dynamic_instance_count == 0 &&
8669 + !restool_misc->static_instance_in_use)) {
8670 + mutex_unlock(&restool_misc->mutex);
8671 + return -EINVAL;
8672 + }
8673 +
8674 + /* Globally clean up opened/untracked handles */
8675 + fsl_mc_portal_reset(local_mc_io);
8676 +
8677 + /*
8678 + * must check
8679 + * whether local_mc_io is dynamic or static instance
8680 + * Otherwise it will free up the reserved portal by accident
8681 + * or even not free up the dynamic allocated portal
8682 + * if 2 or more instances running concurrently
8683 + */
8684 + if (local_mc_io == restool_misc->static_mc_io) {
8685 + restool_misc->static_instance_in_use = false;
8686 + } else {
8687 + fsl_mc_portal_free(local_mc_io);
8688 + kfree(filep->private_data);
8689 + --restool_misc->dynamic_instance_count;
8690 + }
8691 +
8692 + filep->private_data = NULL;
8693 + mutex_unlock(&restool_misc->mutex);
8694 +
8695 + return 0;
8696 +}
8697 +
8698 +static int restool_send_mc_command(unsigned long arg,
8699 + struct fsl_mc_io *local_mc_io)
8700 +{
8701 + int error;
8702 + struct mc_command mc_cmd;
8703 +
8704 + if (copy_from_user(&mc_cmd, (void __user *)arg, sizeof(mc_cmd)))
8705 + return -EFAULT;
8706 +
8707 + /*
8708 + * Send MC command to the MC:
8709 + */
8710 + error = mc_send_command(local_mc_io, &mc_cmd);
8711 + if (error < 0)
8712 + return error;
8713 +
8714 + if (copy_to_user((void __user *)arg, &mc_cmd, sizeof(mc_cmd)))
8715 + return -EFAULT;
8716 +
8717 + return 0;
8718 +}
8719 +
8720 +static long
8721 +fsl_mc_restool_dev_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
8722 +{
8723 + int error;
8724 +
8725 + switch (cmd) {
8726 + case RESTOOL_SEND_MC_COMMAND:
8727 + error = restool_send_mc_command(arg, file->private_data);
8728 + break;
8729 + default:
8730 + pr_err("%s: unexpected ioctl call number\n", __func__);
8731 + error = -EINVAL;
8732 + }
8733 +
8734 + return error;
8735 +}
8736 +
8737 +static const struct file_operations fsl_mc_restool_dev_fops = {
8738 + .owner = THIS_MODULE,
8739 + .open = fsl_mc_restool_dev_open,
8740 + .release = fsl_mc_restool_dev_release,
8741 + .unlocked_ioctl = fsl_mc_restool_dev_ioctl,
8742 +};
8743 +
8744 +static int restool_add_device_file(struct device *dev)
8745 +{
8746 + u32 name1 = 0;
8747 + char name2[20] = {0};
8748 + int error;
8749 + struct fsl_mc_device *root_mc_dev;
8750 + struct restool_misc *restool_misc;
8751 +
8752 + if (dev->bus == &platform_bus_type && dev->driver_data) {
8753 + if (sscanf(dev_name(dev), "%x.%s", &name1, name2) != 2)
8754 + return -EINVAL;
8755 +
8756 + if (strcmp(name2, "fsl-mc") == 0)
8757 + pr_debug("platform's root dprc name is: %s\n",
8758 + dev_name(&(((struct fsl_mc *)
8759 + (dev->driver_data))->root_mc_bus_dev->dev)));
8760 + }
8761 +
8762 + if (!fsl_mc_is_root_dprc(dev))
8763 + return 0;
8764 +
8765 + restool_misc = kzalloc(sizeof(*restool_misc), GFP_KERNEL);
8766 + if (!restool_misc)
8767 + return -ENOMEM;
8768 +
8769 + restool_misc->dev = dev;
8770 + root_mc_dev = to_fsl_mc_device(dev);
8771 + error = fsl_mc_portal_allocate(root_mc_dev, 0,
8772 + &restool_misc->static_mc_io);
8773 + if (error < 0) {
8774 + pr_err("Not able to allocate MC portal\n");
8775 + goto free_restool_misc;
8776 + }
8777 +
8778 + restool_misc->misc.minor = MISC_DYNAMIC_MINOR;
8779 + restool_misc->misc.name = dev_name(dev);
8780 + restool_misc->misc.fops = &fsl_mc_restool_dev_fops;
8781 +
8782 + error = misc_register(&restool_misc->misc);
8783 + if (error < 0) {
8784 + pr_err("misc_register() failed: %d\n", error);
8785 + goto free_portal;
8786 + }
8787 +
8788 + restool_misc->miscdevt = restool_misc->misc.this_device->devt;
8789 + mutex_init(&restool_misc->mutex);
8790 + mutex_lock(&misc_list_mutex);
8791 + list_add(&restool_misc->list, &misc_list);
8792 + mutex_unlock(&misc_list_mutex);
8793 +
8794 + pr_info("/dev/%s driver registered\n", dev_name(dev));
8795 +
8796 + return 0;
8797 +
8798 +free_portal:
8799 + fsl_mc_portal_free(restool_misc->static_mc_io);
8800 +free_restool_misc:
8801 + kfree(restool_misc);
8802 +
8803 + return error;
8804 +}
8805 +
8806 +static int restool_bus_notifier(struct notifier_block *nb,
8807 + unsigned long action, void *data)
8808 +{
8809 + int error;
8810 + struct device *dev = data;
8811 +
8812 + switch (action) {
8813 + case BUS_NOTIFY_ADD_DEVICE:
8814 + error = restool_add_device_file(dev);
8815 + if (error)
8816 + return error;
8817 + break;
8818 + case BUS_NOTIFY_DEL_DEVICE:
8819 + case BUS_NOTIFY_REMOVED_DEVICE:
8820 + case BUS_NOTIFY_BIND_DRIVER:
8821 + case BUS_NOTIFY_BOUND_DRIVER:
8822 + case BUS_NOTIFY_UNBIND_DRIVER:
8823 + case BUS_NOTIFY_UNBOUND_DRIVER:
8824 + break;
8825 + default:
8826 + pr_err("%s: unrecognized device action from %s\n", __func__,
8827 + dev_name(dev));
8828 + return -EINVAL;
8829 + }
8830 +
8831 + return 0;
8832 +}
8833 +
8834 +static int add_to_restool(struct device *dev, void *data)
8835 +{
8836 + return restool_add_device_file(dev);
8837 +}
8838 +
8839 +static int __init fsl_mc_restool_driver_init(void)
8840 +{
8841 + int error;
8842 + struct notifier_block *nb;
8843 +
8844 + nb = kzalloc(sizeof(*nb), GFP_KERNEL);
8845 + if (!nb)
8846 + return -ENOMEM;
8847 +
8848 + nb->notifier_call = restool_bus_notifier;
8849 + error = bus_register_notifier(&fsl_mc_bus_type, nb);
8850 + if (error)
8851 + goto free_nb;
8852 +
8853 + /*
8854 + * This driver runs after fsl-mc bus driver runs.
8855 + * Hence, many of the root dprcs are already attached to fsl-mc bus
8856 + * In order to make sure we find all the root dprcs,
8857 + * we need to scan the fsl_mc_bus_type.
8858 + */
8859 + error = bus_for_each_dev(&fsl_mc_bus_type, NULL, NULL, add_to_restool);
8860 + if (error) {
8861 + bus_unregister_notifier(&fsl_mc_bus_type, nb);
8862 + kfree(nb);
8863 + pr_err("restool driver registration failure\n");
8864 + return error;
8865 + }
8866 +
8867 + return 0;
8868 +
8869 +free_nb:
8870 + kfree(nb);
8871 + return error;
8872 +}
8873 +
8874 +module_init(fsl_mc_restool_driver_init);
8875 +
8876 +static void __exit fsl_mc_restool_driver_exit(void)
8877 +{
8878 + struct restool_misc *restool_misc;
8879 + struct restool_misc *restool_misc_tmp;
8880 + char name1[20] = {0};
8881 + u32 name2 = 0;
8882 +
8883 + list_for_each_entry_safe(restool_misc, restool_misc_tmp,
8884 + &misc_list, list) {
8885 + if (sscanf(restool_misc->misc.name, "%4s.%u", name1, &name2)
8886 + != 2)
8887 + continue;
8888 +
8889 + pr_debug("name1=%s,name2=%u\n", name1, name2);
8890 + pr_debug("misc-device: %s\n", restool_misc->misc.name);
8891 + if (strcmp(name1, "dprc") != 0)
8892 + continue;
8893 +
8894 + if (WARN_ON(!restool_misc->static_mc_io))
8895 + return;
8896 +
8897 + if (WARN_ON(restool_misc->dynamic_instance_count != 0))
8898 + return;
8899 +
8900 + if (WARN_ON(restool_misc->static_instance_in_use))
8901 + return;
8902 +
8903 + misc_deregister(&restool_misc->misc);
8904 + pr_info("/dev/%s driver unregistered\n",
8905 + restool_misc->misc.name);
8906 + fsl_mc_portal_free(restool_misc->static_mc_io);
8907 + list_del(&restool_misc->list);
8908 + kfree(restool_misc);
8909 + }
8910 +}
8911 +
8912 +module_exit(fsl_mc_restool_driver_exit);
8913 +
8914 +MODULE_AUTHOR("Freescale Semiconductor Inc.");
8915 +MODULE_DESCRIPTION("Freescale's MC restool driver");
8916 +MODULE_LICENSE("GPL");
8917 diff --git a/drivers/staging/fsl-mc/bus/mc-sys.c b/drivers/staging/fsl-mc/bus/mc-sys.c
8918 index 285917c7..cf63c7b6 100644
8919 --- a/drivers/staging/fsl-mc/bus/mc-sys.c
8920 +++ b/drivers/staging/fsl-mc/bus/mc-sys.c
8921 @@ -1,4 +1,5 @@
8922 -/* Copyright 2013-2014 Freescale Semiconductor Inc.
8923 +/*
8924 + * Copyright 2013-2016 Freescale Semiconductor Inc.
8925 *
8926 * I/O services to send MC commands to the MC hardware
8927 *
8928 @@ -13,7 +14,6 @@
8929 * names of any contributors may be used to endorse or promote products
8930 * derived from this software without specific prior written permission.
8931 *
8932 - *
8933 * ALTERNATIVELY, this software may be distributed under the terms of the
8934 * GNU General Public License ("GPL") as published by the Free Software
8935 * Foundation, either version 2 of that License or (at your option) any
8936 @@ -46,7 +46,7 @@
8937 /**
8938 * Timeout in milliseconds to wait for the completion of an MC command
8939 */
8940 -#define MC_CMD_COMPLETION_TIMEOUT_MS 500
8941 +#define MC_CMD_COMPLETION_TIMEOUT_MS 15000
8942
8943 /*
8944 * usleep_range() min and max values used to throttle down polling
8945 @@ -67,7 +67,7 @@ static u16 mc_cmd_hdr_read_cmdid(struct mc_command *cmd)
8946 struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header;
8947 u16 cmd_id = le16_to_cpu(hdr->cmd_id);
8948
8949 - return (cmd_id & MC_CMD_HDR_CMDID_MASK) >> MC_CMD_HDR_CMDID_SHIFT;
8950 + return cmd_id;
8951 }
8952
8953 static int mc_status_to_error(enum mc_cmd_status status)
8954 @@ -200,7 +200,7 @@ static int mc_polling_wait_preemptible(struct fsl_mc_io *mc_io,
8955
8956 if (time_after_eq(jiffies, jiffies_until_timeout)) {
8957 dev_dbg(mc_io->dev,
8958 - "MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n",
8959 + "MC command timed out (portal: %#llx, dprc handle: %#x, command: %#x)\n",
8960 mc_io->portal_phys_addr,
8961 (unsigned int)mc_cmd_hdr_read_token(cmd),
8962 (unsigned int)mc_cmd_hdr_read_cmdid(cmd));
8963 @@ -240,7 +240,7 @@ static int mc_polling_wait_atomic(struct fsl_mc_io *mc_io,
8964 timeout_usecs -= MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS;
8965 if (timeout_usecs == 0) {
8966 dev_dbg(mc_io->dev,
8967 - "MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n",
8968 + "MC command timed out (portal: %#llx, dprc handle: %#x, command: %#x)\n",
8969 mc_io->portal_phys_addr,
8970 (unsigned int)mc_cmd_hdr_read_token(cmd),
8971 (unsigned int)mc_cmd_hdr_read_cmdid(cmd));
8972 @@ -294,7 +294,7 @@ int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd)
8973
8974 if (status != MC_CMD_STATUS_OK) {
8975 dev_dbg(mc_io->dev,
8976 - "MC command failed: portal: %#llx, obj handle: %#x, command: %#x, status: %s (%#x)\n",
8977 + "MC command failed: portal: %#llx, dprc handle: %#x, command: %#x, status: %s (%#x)\n",
8978 mc_io->portal_phys_addr,
8979 (unsigned int)mc_cmd_hdr_read_token(cmd),
8980 (unsigned int)mc_cmd_hdr_read_cmdid(cmd),
8981 diff --git a/drivers/staging/fsl-mc/include/dpaa2-fd.h b/drivers/staging/fsl-mc/include/dpaa2-fd.h
8982 new file mode 100644
8983 index 00000000..72328415
8984 --- /dev/null
8985 +++ b/drivers/staging/fsl-mc/include/dpaa2-fd.h
8986 @@ -0,0 +1,706 @@
8987 +/*
8988 + * Copyright 2014-2016 Freescale Semiconductor Inc.
8989 + * Copyright 2016 NXP
8990 + *
8991 + * Redistribution and use in source and binary forms, with or without
8992 + * modification, are permitted provided that the following conditions are met:
8993 + * * Redistributions of source code must retain the above copyright
8994 + * notice, this list of conditions and the following disclaimer.
8995 + * * Redistributions in binary form must reproduce the above copyright
8996 + * notice, this list of conditions and the following disclaimer in the
8997 + * documentation and/or other materials provided with the distribution.
8998 + * * Neither the name of Freescale Semiconductor nor the
8999 + * names of its contributors may be used to endorse or promote products
9000 + * derived from this software without specific prior written permission.
9001 + *
9002 + * ALTERNATIVELY, this software may be distributed under the terms of the
9003 + * GNU General Public License ("GPL") as published by the Free Software
9004 + * Foundation, either version 2 of that License or (at your option) any
9005 + * later version.
9006 + *
9007 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9008 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9009 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9010 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9011 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9012 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9013 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9014 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9015 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9016 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9017 + */
9018 +#ifndef __FSL_DPAA2_FD_H
9019 +#define __FSL_DPAA2_FD_H
9020 +
9021 +#include <linux/kernel.h>
9022 +
9023 +/**
9024 + * DOC: DPAA2 FD - Frame Descriptor APIs for DPAA2
9025 + *
9026 + * Frame Descriptors (FDs) are used to describe frame data in the DPAA2.
9027 + * Frames can be enqueued and dequeued to Frame Queues (FQs) which are consumed
9028 + * by the various DPAA accelerators (WRIOP, SEC, PME, DCE)
9029 + *
9030 + * There are three types of frames: single, scatter gather, and frame lists.
9031 + *
9032 + * The set of APIs in this file must be used to create, manipulate and
9033 + * query Frame Descriptors.
9034 + */
9035 +
9036 +/**
9037 + * struct dpaa2_fd - Struct describing FDs
9038 + * @words: for easier/faster copying the whole FD structure
9039 + * @addr: address in the FD
9040 + * @len: length in the FD
9041 + * @bpid: buffer pool ID
9042 + * @format_offset: format, offset, and short-length fields
9043 + * @frc: frame context
9044 + * @ctrl: control bits...including dd, sc, va, err, etc
9045 + * @flc: flow context address
9046 + *
9047 + * This structure represents the basic Frame Descriptor used in the system.
9048 + */
9049 +struct dpaa2_fd {
9050 + union {
9051 + u32 words[8];
9052 + struct dpaa2_fd_simple {
9053 + __le64 addr;
9054 + __le32 len;
9055 + __le16 bpid;
9056 + __le16 format_offset;
9057 + __le32 frc;
9058 + __le32 ctrl;
9059 + __le64 flc;
9060 + } simple;
9061 + };
9062 +};
9063 +
9064 +#define FD_SHORT_LEN_FLAG_MASK 0x1
9065 +#define FD_SHORT_LEN_FLAG_SHIFT 14
9066 +#define FD_SHORT_LEN_MASK 0x3FFFF
9067 +#define FD_OFFSET_MASK 0x0FFF
9068 +#define FD_FORMAT_MASK 0x3
9069 +#define FD_FORMAT_SHIFT 12
9070 +#define FD_BPID_MASK 0x3FFF
9071 +#define SG_SHORT_LEN_FLAG_MASK 0x1
9072 +#define SG_SHORT_LEN_FLAG_SHIFT 14
9073 +#define SG_SHORT_LEN_MASK 0x1FFFF
9074 +#define SG_OFFSET_MASK 0x0FFF
9075 +#define SG_FORMAT_MASK 0x3
9076 +#define SG_FORMAT_SHIFT 12
9077 +#define SG_BPID_MASK 0x3FFF
9078 +#define SG_FINAL_FLAG_MASK 0x1
9079 +#define SG_FINAL_FLAG_SHIFT 15
9080 +#define FL_SHORT_LEN_FLAG_MASK 0x1
9081 +#define FL_SHORT_LEN_FLAG_SHIFT 14
9082 +#define FL_SHORT_LEN_MASK 0x3FFFF
9083 +#define FL_OFFSET_MASK 0x0FFF
9084 +#define FL_FORMAT_MASK 0x3
9085 +#define FL_FORMAT_SHIFT 12
9086 +#define FL_BPID_MASK 0x3FFF
9087 +#define FL_FINAL_FLAG_MASK 0x1
9088 +#define FL_FINAL_FLAG_SHIFT 15
9089 +
9090 +/* Error bits in FD CTRL */
9091 +#define FD_CTRL_ERR_MASK 0x000000FF
9092 +#define FD_CTRL_UFD 0x00000004
9093 +#define FD_CTRL_SBE 0x00000008
9094 +#define FD_CTRL_FLC 0x00000010
9095 +#define FD_CTRL_FSE 0x00000020
9096 +#define FD_CTRL_FAERR 0x00000040
9097 +
9098 +/* Annotation bits in FD CTRL */
9099 +#define FD_CTRL_PTA 0x00800000
9100 +#define FD_CTRL_PTV1 0x00400000
9101 +
9102 +enum dpaa2_fd_format {
9103 + dpaa2_fd_single = 0,
9104 + dpaa2_fd_list,
9105 + dpaa2_fd_sg
9106 +};
9107 +
9108 +/**
9109 + * dpaa2_fd_get_addr() - get the addr field of frame descriptor
9110 + * @fd: the given frame descriptor
9111 + *
9112 + * Return the address in the frame descriptor.
9113 + */
9114 +static inline dma_addr_t dpaa2_fd_get_addr(const struct dpaa2_fd *fd)
9115 +{
9116 + return (dma_addr_t)le64_to_cpu(fd->simple.addr);
9117 +}
9118 +
9119 +/**
9120 + * dpaa2_fd_set_addr() - Set the addr field of frame descriptor
9121 + * @fd: the given frame descriptor
9122 + * @addr: the address needs to be set in frame descriptor
9123 + */
9124 +static inline void dpaa2_fd_set_addr(struct dpaa2_fd *fd, dma_addr_t addr)
9125 +{
9126 + fd->simple.addr = cpu_to_le64(addr);
9127 +}
9128 +
9129 +/**
9130 + * dpaa2_fd_get_frc() - Get the frame context in the frame descriptor
9131 + * @fd: the given frame descriptor
9132 + *
9133 + * Return the frame context field in the frame descriptor.
9134 + */
9135 +static inline u32 dpaa2_fd_get_frc(const struct dpaa2_fd *fd)
9136 +{
9137 + return le32_to_cpu(fd->simple.frc);
9138 +}
9139 +
9140 +/**
9141 + * dpaa2_fd_set_frc() - Set the frame context in the frame descriptor
9142 + * @fd: the given frame descriptor
9143 + * @frc: the frame context needs to be set in frame descriptor
9144 + */
9145 +static inline void dpaa2_fd_set_frc(struct dpaa2_fd *fd, u32 frc)
9146 +{
9147 + fd->simple.frc = cpu_to_le32(frc);
9148 +}
9149 +
9150 +/**
9151 + * dpaa2_fd_get_ctrl() - Get the control bits in the frame descriptor
9152 + * @fd: the given frame descriptor
9153 + *
9154 + * Return the control bits field in the frame descriptor.
9155 + */
9156 +static inline u32 dpaa2_fd_get_ctrl(const struct dpaa2_fd *fd)
9157 +{
9158 + return le32_to_cpu(fd->simple.ctrl);
9159 +}
9160 +
9161 +/**
9162 + * dpaa2_fd_set_ctrl() - Set the control bits in the frame descriptor
9163 + * @fd: the given frame descriptor
9164 + * @ctrl: the control bits to be set in the frame descriptor
9165 + */
9166 +static inline void dpaa2_fd_set_ctrl(struct dpaa2_fd *fd, u32 ctrl)
9167 +{
9168 + fd->simple.ctrl = cpu_to_le32(ctrl);
9169 +}
9170 +
9171 +/**
9172 + * dpaa2_fd_get_flc() - Get the flow context in the frame descriptor
9173 + * @fd: the given frame descriptor
9174 + *
9175 + * Return the flow context in the frame descriptor.
9176 + */
9177 +static inline dma_addr_t dpaa2_fd_get_flc(const struct dpaa2_fd *fd)
9178 +{
9179 + return (dma_addr_t)le64_to_cpu(fd->simple.flc);
9180 +}
9181 +
9182 +/**
9183 + * dpaa2_fd_set_flc() - Set the flow context field of frame descriptor
9184 + * @fd: the given frame descriptor
9185 + * @flc_addr: the flow context needs to be set in frame descriptor
9186 + */
9187 +static inline void dpaa2_fd_set_flc(struct dpaa2_fd *fd, dma_addr_t flc_addr)
9188 +{
9189 + fd->simple.flc = cpu_to_le64(flc_addr);
9190 +}
9191 +
9192 +static inline bool dpaa2_fd_short_len(const struct dpaa2_fd *fd)
9193 +{
9194 + return !!((le16_to_cpu(fd->simple.format_offset) >>
9195 + FD_SHORT_LEN_FLAG_SHIFT) & FD_SHORT_LEN_FLAG_MASK);
9196 +}
9197 +
9198 +/**
9199 + * dpaa2_fd_get_len() - Get the length in the frame descriptor
9200 + * @fd: the given frame descriptor
9201 + *
9202 + * Return the length field in the frame descriptor.
9203 + */
9204 +static inline u32 dpaa2_fd_get_len(const struct dpaa2_fd *fd)
9205 +{
9206 + if (dpaa2_fd_short_len(fd))
9207 + return le32_to_cpu(fd->simple.len) & FD_SHORT_LEN_MASK;
9208 +
9209 + return le32_to_cpu(fd->simple.len);
9210 +}
9211 +
9212 +/**
9213 + * dpaa2_fd_set_len() - Set the length field of frame descriptor
9214 + * @fd: the given frame descriptor
9215 + * @len: the length needs to be set in frame descriptor
9216 + */
9217 +static inline void dpaa2_fd_set_len(struct dpaa2_fd *fd, u32 len)
9218 +{
9219 + fd->simple.len = cpu_to_le32(len);
9220 +}
9221 +
9222 +/**
9223 + * dpaa2_fd_get_offset() - Get the offset field in the frame descriptor
9224 + * @fd: the given frame descriptor
9225 + *
9226 + * Return the offset.
9227 + */
9228 +static inline uint16_t dpaa2_fd_get_offset(const struct dpaa2_fd *fd)
9229 +{
9230 + return le16_to_cpu(fd->simple.format_offset) & FD_OFFSET_MASK;
9231 +}
9232 +
9233 +/**
9234 + * dpaa2_fd_set_offset() - Set the offset field of frame descriptor
9235 + * @fd: the given frame descriptor
9236 + * @offset: the offset needs to be set in frame descriptor
9237 + */
9238 +static inline void dpaa2_fd_set_offset(struct dpaa2_fd *fd, uint16_t offset)
9239 +{
9240 + fd->simple.format_offset &= cpu_to_le16(~FD_OFFSET_MASK);
9241 + fd->simple.format_offset |= cpu_to_le16(offset);
9242 +}
9243 +
9244 +/**
9245 + * dpaa2_fd_get_format() - Get the format field in the frame descriptor
9246 + * @fd: the given frame descriptor
9247 + *
9248 + * Return the format.
9249 + */
9250 +static inline enum dpaa2_fd_format dpaa2_fd_get_format(
9251 + const struct dpaa2_fd *fd)
9252 +{
9253 + return (enum dpaa2_fd_format)((le16_to_cpu(fd->simple.format_offset)
9254 + >> FD_FORMAT_SHIFT) & FD_FORMAT_MASK);
9255 +}
9256 +
9257 +/**
9258 + * dpaa2_fd_set_format() - Set the format field of frame descriptor
9259 + * @fd: the given frame descriptor
9260 + * @format: the format needs to be set in frame descriptor
9261 + */
9262 +static inline void dpaa2_fd_set_format(struct dpaa2_fd *fd,
9263 + enum dpaa2_fd_format format)
9264 +{
9265 + fd->simple.format_offset &=
9266 + cpu_to_le16(~(FD_FORMAT_MASK << FD_FORMAT_SHIFT));
9267 + fd->simple.format_offset |= cpu_to_le16(format << FD_FORMAT_SHIFT);
9268 +}
9269 +
9270 +/**
9271 + * dpaa2_fd_get_bpid() - Get the bpid field in the frame descriptor
9272 + * @fd: the given frame descriptor
9273 + *
9274 + * Return the buffer pool id.
9275 + */
9276 +static inline uint16_t dpaa2_fd_get_bpid(const struct dpaa2_fd *fd)
9277 +{
9278 + return le16_to_cpu(fd->simple.bpid) & FD_BPID_MASK;
9279 +}
9280 +
9281 +/**
9282 + * dpaa2_fd_set_bpid() - Set the bpid field of frame descriptor
9283 + * @fd: the given frame descriptor
9284 + * @bpid: buffer pool id to be set
9285 + */
9286 +static inline void dpaa2_fd_set_bpid(struct dpaa2_fd *fd, uint16_t bpid)
9287 +{
9288 + fd->simple.bpid &= cpu_to_le16(~(FD_BPID_MASK));
9289 + fd->simple.bpid |= cpu_to_le16(bpid);
9290 +}
9291 +
9292 +/**
9293 + * struct dpaa2_sg_entry - the scatter-gathering structure
9294 + * @addr: address of the sg entry
9295 + * @len: length in this sg entry
9296 + * @bpid: buffer pool id
9297 + * @format_offset: format and offset fields
9298 + */
9299 +struct dpaa2_sg_entry {
9300 + __le64 addr;
9301 + __le32 len;
9302 + __le16 bpid;
9303 + __le16 format_offset;
9304 +};
9305 +
9306 +enum dpaa2_sg_format {
9307 + dpaa2_sg_single = 0,
9308 + dpaa2_sg_frame_data,
9309 + dpaa2_sg_sgt_ext
9310 +};
9311 +
9312 +/* Accessors for SG entry fields */
9313 +
9314 +/**
9315 + * dpaa2_sg_get_addr() - Get the address from SG entry
9316 + * @sg: the given scatter-gathering object
9317 + *
9318 + * Return the address.
9319 + */
9320 +static inline dma_addr_t dpaa2_sg_get_addr(const struct dpaa2_sg_entry *sg)
9321 +{
9322 + return le64_to_cpu((dma_addr_t)sg->addr);
9323 +}
9324 +
9325 +/**
9326 + * dpaa2_sg_set_addr() - Set the address in SG entry
9327 + * @sg: the given scatter-gathering object
9328 + * @addr: the address to be set
9329 + */
9330 +static inline void dpaa2_sg_set_addr(struct dpaa2_sg_entry *sg, dma_addr_t addr)
9331 +{
9332 + sg->addr = cpu_to_le64(addr);
9333 +}
9334 +
9335 +static inline bool dpaa2_sg_short_len(const struct dpaa2_sg_entry *sg)
9336 +{
9337 + return !!((le16_to_cpu(sg->format_offset) >> SG_SHORT_LEN_FLAG_SHIFT)
9338 + & SG_SHORT_LEN_FLAG_MASK);
9339 +}
9340 +
9341 +/**
9342 + * dpaa2_sg_get_len() - Get the length in SG entry
9343 + * @sg: the given scatter-gathering object
9344 + *
9345 + * Return the length.
9346 + */
9347 +static inline u32 dpaa2_sg_get_len(const struct dpaa2_sg_entry *sg)
9348 +{
9349 + if (dpaa2_sg_short_len(sg))
9350 + return le32_to_cpu(sg->len) & SG_SHORT_LEN_MASK;
9351 +
9352 + return le32_to_cpu(sg->len);
9353 +}
9354 +
9355 +/**
9356 + * dpaa2_sg_set_len() - Set the length in SG entry
9357 + * @sg: the given scatter-gathering object
9358 + * @len: the length to be set
9359 + */
9360 +static inline void dpaa2_sg_set_len(struct dpaa2_sg_entry *sg, u32 len)
9361 +{
9362 + sg->len = cpu_to_le32(len);
9363 +}
9364 +
9365 +/**
9366 + * dpaa2_sg_get_offset() - Get the offset in SG entry
9367 + * @sg: the given scatter-gathering object
9368 + *
9369 + * Return the offset.
9370 + */
9371 +static inline u16 dpaa2_sg_get_offset(const struct dpaa2_sg_entry *sg)
9372 +{
9373 + return le16_to_cpu(sg->format_offset) & SG_OFFSET_MASK;
9374 +}
9375 +
9376 +/**
9377 + * dpaa2_sg_set_offset() - Set the offset in SG entry
9378 + * @sg: the given scatter-gathering object
9379 + * @offset: the offset to be set
9380 + */
9381 +static inline void dpaa2_sg_set_offset(struct dpaa2_sg_entry *sg,
9382 + u16 offset)
9383 +{
9384 + sg->format_offset &= cpu_to_le16(~SG_OFFSET_MASK);
9385 + sg->format_offset |= cpu_to_le16(offset);
9386 +}
9387 +
9388 +/**
9389 + * dpaa2_sg_get_format() - Get the SG format in SG entry
9390 + * @sg: the given scatter-gathering object
9391 + *
9392 + * Return the format.
9393 + */
9394 +static inline enum dpaa2_sg_format
9395 + dpaa2_sg_get_format(const struct dpaa2_sg_entry *sg)
9396 +{
9397 + return (enum dpaa2_sg_format)((le16_to_cpu(sg->format_offset)
9398 + >> SG_FORMAT_SHIFT) & SG_FORMAT_MASK);
9399 +}
9400 +
9401 +/**
9402 + * dpaa2_sg_set_format() - Set the SG format in SG entry
9403 + * @sg: the given scatter-gathering object
9404 + * @format: the format to be set
9405 + */
9406 +static inline void dpaa2_sg_set_format(struct dpaa2_sg_entry *sg,
9407 + enum dpaa2_sg_format format)
9408 +{
9409 + sg->format_offset &= cpu_to_le16(~(SG_FORMAT_MASK << SG_FORMAT_SHIFT));
9410 + sg->format_offset |= cpu_to_le16(format << SG_FORMAT_SHIFT);
9411 +}
9412 +
9413 +/**
9414 + * dpaa2_sg_get_bpid() - Get the buffer pool id in SG entry
9415 + * @sg: the given scatter-gathering object
9416 + *
9417 + * Return the bpid.
9418 + */
9419 +static inline u16 dpaa2_sg_get_bpid(const struct dpaa2_sg_entry *sg)
9420 +{
9421 + return le16_to_cpu(sg->bpid) & SG_BPID_MASK;
9422 +}
9423 +
9424 +/**
9425 + * dpaa2_sg_set_bpid() - Set the buffer pool id in SG entry
9426 + * @sg: the given scatter-gathering object
9427 + * @bpid: the bpid to be set
9428 + */
9429 +static inline void dpaa2_sg_set_bpid(struct dpaa2_sg_entry *sg, u16 bpid)
9430 +{
9431 + sg->bpid &= cpu_to_le16(~(SG_BPID_MASK));
9432 + sg->bpid |= cpu_to_le16(bpid);
9433 +}
9434 +
9435 +/**
9436 + * dpaa2_sg_is_final() - Check final bit in SG entry
9437 + * @sg: the given scatter-gathering object
9438 + *
9439 + * Return bool.
9440 + */
9441 +static inline bool dpaa2_sg_is_final(const struct dpaa2_sg_entry *sg)
9442 +{
9443 + return !!(le16_to_cpu(sg->format_offset) >> SG_FINAL_FLAG_SHIFT);
9444 +}
9445 +
9446 +/**
9447 + * dpaa2_sg_set_final() - Set the final bit in SG entry
9448 + * @sg: the given scatter-gathering object
9449 + * @final: the final boolean to be set
9450 + */
9451 +static inline void dpaa2_sg_set_final(struct dpaa2_sg_entry *sg, bool final)
9452 +{
9453 + sg->format_offset &= cpu_to_le16(~(SG_FINAL_FLAG_MASK
9454 + << SG_FINAL_FLAG_SHIFT));
9455 + sg->format_offset |= cpu_to_le16(final << SG_FINAL_FLAG_SHIFT);
9456 +}
9457 +
9458 +/**
9459 + * struct dpaa2_fl_entry - structure for frame list entry.
9460 + * @addr: address in the FLE
9461 + * @len: length in the FLE
9462 + * @bpid: buffer pool ID
9463 + * @format_offset: format, offset, and short-length fields
9464 + * @frc: frame context
9465 + * @ctrl: control bits...including pta, pvt1, pvt2, err, etc
9466 + * @flc: flow context address
9467 + */
9468 +struct dpaa2_fl_entry {
9469 + __le64 addr;
9470 + __le32 len;
9471 + __le16 bpid;
9472 + __le16 format_offset;
9473 + __le32 frc;
9474 + __le32 ctrl;
9475 + __le64 flc;
9476 +};
9477 +
9478 +enum dpaa2_fl_format {
9479 + dpaa2_fl_single = 0,
9480 + dpaa2_fl_res,
9481 + dpaa2_fl_sg
9482 +};
9483 +
9484 +/**
9485 + * dpaa2_fl_get_addr() - get the addr field of FLE
9486 + * @fle: the given frame list entry
9487 + *
9488 + * Return the address in the frame list entry.
9489 + */
9490 +static inline dma_addr_t dpaa2_fl_get_addr(const struct dpaa2_fl_entry *fle)
9491 +{
9492 + return (dma_addr_t)le64_to_cpu(fle->addr);
9493 +}
9494 +
9495 +/**
9496 + * dpaa2_fl_set_addr() - Set the addr field of FLE
9497 + * @fle: the given frame list entry
9498 + * @addr: the address needs to be set in frame list entry
9499 + */
9500 +static inline void dpaa2_fl_set_addr(struct dpaa2_fl_entry *fle,
9501 + dma_addr_t addr)
9502 +{
9503 + fle->addr = cpu_to_le64(addr);
9504 +}
9505 +
9506 +/**
9507 + * dpaa2_fl_get_frc() - Get the frame context in the FLE
9508 + * @fle: the given frame list entry
9509 + *
9510 + * Return the frame context field in the frame lsit entry.
9511 + */
9512 +static inline u32 dpaa2_fl_get_frc(const struct dpaa2_fl_entry *fle)
9513 +{
9514 + return le32_to_cpu(fle->frc);
9515 +}
9516 +
9517 +/**
9518 + * dpaa2_fl_set_frc() - Set the frame context in the FLE
9519 + * @fle: the given frame list entry
9520 + * @frc: the frame context needs to be set in frame list entry
9521 + */
9522 +static inline void dpaa2_fl_set_frc(struct dpaa2_fl_entry *fle, u32 frc)
9523 +{
9524 + fle->frc = cpu_to_le32(frc);
9525 +}
9526 +
9527 +/**
9528 + * dpaa2_fl_get_ctrl() - Get the control bits in the FLE
9529 + * @fle: the given frame list entry
9530 + *
9531 + * Return the control bits field in the frame list entry.
9532 + */
9533 +static inline u32 dpaa2_fl_get_ctrl(const struct dpaa2_fl_entry *fle)
9534 +{
9535 + return le32_to_cpu(fle->ctrl);
9536 +}
9537 +
9538 +/**
9539 + * dpaa2_fl_set_ctrl() - Set the control bits in the FLE
9540 + * @fle: the given frame list entry
9541 + * @ctrl: the control bits to be set in the frame list entry
9542 + */
9543 +static inline void dpaa2_fl_set_ctrl(struct dpaa2_fl_entry *fle, u32 ctrl)
9544 +{
9545 + fle->ctrl = cpu_to_le32(ctrl);
9546 +}
9547 +
9548 +/**
9549 + * dpaa2_fl_get_flc() - Get the flow context in the FLE
9550 + * @fle: the given frame list entry
9551 + *
9552 + * Return the flow context in the frame list entry.
9553 + */
9554 +static inline dma_addr_t dpaa2_fl_get_flc(const struct dpaa2_fl_entry *fle)
9555 +{
9556 + return (dma_addr_t)le64_to_cpu(fle->flc);
9557 +}
9558 +
9559 +/**
9560 + * dpaa2_fl_set_flc() - Set the flow context field of FLE
9561 + * @fle: the given frame list entry
9562 + * @flc_addr: the flow context needs to be set in frame list entry
9563 + */
9564 +static inline void dpaa2_fl_set_flc(struct dpaa2_fl_entry *fle,
9565 + dma_addr_t flc_addr)
9566 +{
9567 + fle->flc = cpu_to_le64(flc_addr);
9568 +}
9569 +
9570 +static inline bool dpaa2_fl_short_len(const struct dpaa2_fl_entry *fle)
9571 +{
9572 + return !!((le16_to_cpu(fle->format_offset) >>
9573 + FL_SHORT_LEN_FLAG_SHIFT) & FL_SHORT_LEN_FLAG_MASK);
9574 +}
9575 +
9576 +/**
9577 + * dpaa2_fl_get_len() - Get the length in the FLE
9578 + * @fle: the given frame list entry
9579 + *
9580 + * Return the length field in the frame list entry.
9581 + */
9582 +static inline u32 dpaa2_fl_get_len(const struct dpaa2_fl_entry *fle)
9583 +{
9584 + if (dpaa2_fl_short_len(fle))
9585 + return le32_to_cpu(fle->len) & FL_SHORT_LEN_MASK;
9586 +
9587 + return le32_to_cpu(fle->len);
9588 +}
9589 +
9590 +/**
9591 + * dpaa2_fl_set_len() - Set the length field of FLE
9592 + * @fle: the given frame list entry
9593 + * @len: the length needs to be set in frame list entry
9594 + */
9595 +static inline void dpaa2_fl_set_len(struct dpaa2_fl_entry *fle, u32 len)
9596 +{
9597 + fle->len = cpu_to_le32(len);
9598 +}
9599 +
9600 +/**
9601 + * dpaa2_fl_get_offset() - Get the offset field in the frame list entry
9602 + * @fle: the given frame list entry
9603 + *
9604 + * Return the offset.
9605 + */
9606 +static inline u16 dpaa2_fl_get_offset(const struct dpaa2_fl_entry *fle)
9607 +{
9608 + return le16_to_cpu(fle->format_offset) & FL_OFFSET_MASK;
9609 +}
9610 +
9611 +/**
9612 + * dpaa2_fl_set_offset() - Set the offset field of FLE
9613 + * @fle: the given frame list entry
9614 + * @offset: the offset needs to be set in frame list entry
9615 + */
9616 +static inline void dpaa2_fl_set_offset(struct dpaa2_fl_entry *fle, u16 offset)
9617 +{
9618 + fle->format_offset &= cpu_to_le16(~FL_OFFSET_MASK);
9619 + fle->format_offset |= cpu_to_le16(offset);
9620 +}
9621 +
9622 +/**
9623 + * dpaa2_fl_get_format() - Get the format field in the FLE
9624 + * @fle: the given frame list entry
9625 + *
9626 + * Return the format.
9627 + */
9628 +static inline enum dpaa2_fl_format dpaa2_fl_get_format(
9629 + const struct dpaa2_fl_entry *fle)
9630 +{
9631 + return (enum dpaa2_fl_format)((le16_to_cpu(fle->format_offset) >>
9632 + FL_FORMAT_SHIFT) & FL_FORMAT_MASK);
9633 +}
9634 +
9635 +/**
9636 + * dpaa2_fl_set_format() - Set the format field of FLE
9637 + * @fle: the given frame list entry
9638 + * @format: the format needs to be set in frame list entry
9639 + */
9640 +static inline void dpaa2_fl_set_format(struct dpaa2_fl_entry *fle,
9641 + enum dpaa2_fl_format format)
9642 +{
9643 + fle->format_offset &= cpu_to_le16(~(FL_FORMAT_MASK << FL_FORMAT_SHIFT));
9644 + fle->format_offset |= cpu_to_le16(format << FL_FORMAT_SHIFT);
9645 +}
9646 +
9647 +/**
9648 + * dpaa2_fl_get_bpid() - Get the bpid field in the FLE
9649 + * @fle: the given frame list entry
9650 + *
9651 + * Return the buffer pool id.
9652 + */
9653 +static inline u16 dpaa2_fl_get_bpid(const struct dpaa2_fl_entry *fle)
9654 +{
9655 + return le16_to_cpu(fle->bpid) & FL_BPID_MASK;
9656 +}
9657 +
9658 +/**
9659 + * dpaa2_fl_set_bpid() - Set the bpid field of FLE
9660 + * @fle: the given frame list entry
9661 + * @bpid: buffer pool id to be set
9662 + */
9663 +static inline void dpaa2_fl_set_bpid(struct dpaa2_fl_entry *fle, u16 bpid)
9664 +{
9665 + fle->bpid &= cpu_to_le16(~(FL_BPID_MASK));
9666 + fle->bpid |= cpu_to_le16(bpid);
9667 +}
9668 +
9669 +/**
9670 + * dpaa2_fl_is_final() - Check final bit in FLE
9671 + * @fle: the given frame list entry
9672 + *
9673 + * Return bool.
9674 + */
9675 +static inline bool dpaa2_fl_is_final(const struct dpaa2_fl_entry *fle)
9676 +{
9677 + return !!(le16_to_cpu(fle->format_offset) >> FL_FINAL_FLAG_SHIFT);
9678 +}
9679 +
9680 +/**
9681 + * dpaa2_fl_set_final() - Set the final bit in FLE
9682 + * @fle: the given frame list entry
9683 + * @final: the final boolean to be set
9684 + */
9685 +static inline void dpaa2_fl_set_final(struct dpaa2_fl_entry *fle, bool final)
9686 +{
9687 + fle->format_offset &= cpu_to_le16(~(FL_FINAL_FLAG_MASK <<
9688 + FL_FINAL_FLAG_SHIFT));
9689 + fle->format_offset |= cpu_to_le16(final << FL_FINAL_FLAG_SHIFT);
9690 +}
9691 +
9692 +#endif /* __FSL_DPAA2_FD_H */
9693 diff --git a/drivers/staging/fsl-mc/include/dpaa2-global.h b/drivers/staging/fsl-mc/include/dpaa2-global.h
9694 new file mode 100644
9695 index 00000000..0326447f
9696 --- /dev/null
9697 +++ b/drivers/staging/fsl-mc/include/dpaa2-global.h
9698 @@ -0,0 +1,202 @@
9699 +/*
9700 + * Copyright 2014-2016 Freescale Semiconductor Inc.
9701 + * Copyright 2016 NXP
9702 + *
9703 + * Redistribution and use in source and binary forms, with or without
9704 + * modification, are permitted provided that the following conditions are met:
9705 + * * Redistributions of source code must retain the above copyright
9706 + * notice, this list of conditions and the following disclaimer.
9707 + * * Redistributions in binary form must reproduce the above copyright
9708 + * notice, this list of conditions and the following disclaimer in the
9709 + * documentation and/or other materials provided with the distribution.
9710 + * * Neither the name of Freescale Semiconductor nor the
9711 + * names of its contributors may be used to endorse or promote products
9712 + * derived from this software without specific prior written permission.
9713 + *
9714 + * ALTERNATIVELY, this software may be distributed under the terms of the
9715 + * GNU General Public License ("GPL") as published by the Free Software
9716 + * Foundation, either version 2 of that License or (at your option) any
9717 + * later version.
9718 + *
9719 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9720 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9721 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9722 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9723 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9724 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9725 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9726 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9727 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9728 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9729 + */
9730 +#ifndef __FSL_DPAA2_GLOBAL_H
9731 +#define __FSL_DPAA2_GLOBAL_H
9732 +
9733 +#include <linux/types.h>
9734 +#include <linux/cpumask.h>
9735 +#include "dpaa2-fd.h"
9736 +
9737 +struct dpaa2_dq {
9738 + union {
9739 + struct common {
9740 + u8 verb;
9741 + u8 reserved[63];
9742 + } common;
9743 + struct dq {
9744 + u8 verb;
9745 + u8 stat;
9746 + __le16 seqnum;
9747 + __le16 oprid;
9748 + u8 reserved;
9749 + u8 tok;
9750 + __le32 fqid;
9751 + u32 reserved2;
9752 + __le32 fq_byte_cnt;
9753 + __le32 fq_frm_cnt;
9754 + __le64 fqd_ctx;
9755 + u8 fd[32];
9756 + } dq;
9757 + struct scn {
9758 + u8 verb;
9759 + u8 stat;
9760 + u8 state;
9761 + u8 reserved;
9762 + __le32 rid_tok;
9763 + __le64 ctx;
9764 + } scn;
9765 + };
9766 +};
9767 +
9768 +/* Parsing frame dequeue results */
9769 +/* FQ empty */
9770 +#define DPAA2_DQ_STAT_FQEMPTY 0x80
9771 +/* FQ held active */
9772 +#define DPAA2_DQ_STAT_HELDACTIVE 0x40
9773 +/* FQ force eligible */
9774 +#define DPAA2_DQ_STAT_FORCEELIGIBLE 0x20
9775 +/* valid frame */
9776 +#define DPAA2_DQ_STAT_VALIDFRAME 0x10
9777 +/* FQ ODP enable */
9778 +#define DPAA2_DQ_STAT_ODPVALID 0x04
9779 +/* volatile dequeue */
9780 +#define DPAA2_DQ_STAT_VOLATILE 0x02
9781 +/* volatile dequeue command is expired */
9782 +#define DPAA2_DQ_STAT_EXPIRED 0x01
9783 +
9784 +#define DQ_FQID_MASK 0x00FFFFFF
9785 +#define DQ_FRAME_COUNT_MASK 0x00FFFFFF
9786 +
9787 +/**
9788 + * dpaa2_dq_flags() - Get the stat field of dequeue response
9789 + * @dq: the dequeue result.
9790 + */
9791 +static inline u32 dpaa2_dq_flags(const struct dpaa2_dq *dq)
9792 +{
9793 + return dq->dq.stat;
9794 +}
9795 +
9796 +/**
9797 + * dpaa2_dq_is_pull() - Check whether the dq response is from a pull
9798 + * command.
9799 + * @dq: the dequeue result
9800 + *
9801 + * Return 1 for volatile(pull) dequeue, 0 for static dequeue.
9802 + */
9803 +static inline int dpaa2_dq_is_pull(const struct dpaa2_dq *dq)
9804 +{
9805 + return (int)(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_VOLATILE);
9806 +}
9807 +
9808 +/**
9809 + * dpaa2_dq_is_pull_complete() - Check whether the pull command is completed.
9810 + * @dq: the dequeue result
9811 + *
9812 + * Return boolean.
9813 + */
9814 +static inline bool dpaa2_dq_is_pull_complete(const struct dpaa2_dq *dq)
9815 +{
9816 + return !!(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_EXPIRED);
9817 +}
9818 +
9819 +/**
9820 + * dpaa2_dq_seqnum() - Get the seqnum field in dequeue response
9821 + * @dq: the dequeue result
9822 + *
9823 + * seqnum is valid only if VALIDFRAME flag is TRUE
9824 + *
9825 + * Return seqnum.
9826 + */
9827 +static inline u16 dpaa2_dq_seqnum(const struct dpaa2_dq *dq)
9828 +{
9829 + return le16_to_cpu(dq->dq.seqnum);
9830 +}
9831 +
9832 +/**
9833 + * dpaa2_dq_odpid() - Get the odpid field in dequeue response
9834 + * @dq: the dequeue result
9835 + *
9836 + * odpid is valid only if ODPVALID flag is TRUE.
9837 + *
9838 + * Return odpid.
9839 + */
9840 +static inline u16 dpaa2_dq_odpid(const struct dpaa2_dq *dq)
9841 +{
9842 + return le16_to_cpu(dq->dq.oprid);
9843 +}
9844 +
9845 +/**
9846 + * dpaa2_dq_fqid() - Get the fqid in dequeue response
9847 + * @dq: the dequeue result
9848 + *
9849 + * Return fqid.
9850 + */
9851 +static inline u32 dpaa2_dq_fqid(const struct dpaa2_dq *dq)
9852 +{
9853 + return le32_to_cpu(dq->dq.fqid) & DQ_FQID_MASK;
9854 +}
9855 +
9856 +/**
9857 + * dpaa2_dq_byte_count() - Get the byte count in dequeue response
9858 + * @dq: the dequeue result
9859 + *
9860 + * Return the byte count remaining in the FQ.
9861 + */
9862 +static inline u32 dpaa2_dq_byte_count(const struct dpaa2_dq *dq)
9863 +{
9864 + return le32_to_cpu(dq->dq.fq_byte_cnt);
9865 +}
9866 +
9867 +/**
9868 + * dpaa2_dq_frame_count() - Get the frame count in dequeue response
9869 + * @dq: the dequeue result
9870 + *
9871 + * Return the frame count remaining in the FQ.
9872 + */
9873 +static inline u32 dpaa2_dq_frame_count(const struct dpaa2_dq *dq)
9874 +{
9875 + return le32_to_cpu(dq->dq.fq_frm_cnt) & DQ_FRAME_COUNT_MASK;
9876 +}
9877 +
9878 +/**
9879 + * dpaa2_dq_fd_ctx() - Get the frame queue context in dequeue response
9880 + * @dq: the dequeue result
9881 + *
9882 + * Return the frame queue context.
9883 + */
9884 +static inline u64 dpaa2_dq_fqd_ctx(const struct dpaa2_dq *dq)
9885 +{
9886 + return le64_to_cpu(dq->dq.fqd_ctx);
9887 +}
9888 +
9889 +/**
9890 + * dpaa2_dq_fd() - Get the frame descriptor in dequeue response
9891 + * @dq: the dequeue result
9892 + *
9893 + * Return the frame descriptor.
9894 + */
9895 +static inline const struct dpaa2_fd *dpaa2_dq_fd(const struct dpaa2_dq *dq)
9896 +{
9897 + return (const struct dpaa2_fd *)&dq->dq.fd[0];
9898 +}
9899 +
9900 +#endif /* __FSL_DPAA2_GLOBAL_H */
9901 diff --git a/drivers/staging/fsl-mc/include/dpaa2-io.h b/drivers/staging/fsl-mc/include/dpaa2-io.h
9902 new file mode 100644
9903 index 00000000..c7d1d997
9904 --- /dev/null
9905 +++ b/drivers/staging/fsl-mc/include/dpaa2-io.h
9906 @@ -0,0 +1,190 @@
9907 +/*
9908 + * Copyright 2014-2016 Freescale Semiconductor Inc.
9909 + * Copyright 2017 NXP
9910 + *
9911 + * Redistribution and use in source and binary forms, with or without
9912 + * modification, are permitted provided that the following conditions are met:
9913 + * * Redistributions of source code must retain the above copyright
9914 + * notice, this list of conditions and the following disclaimer.
9915 + * * Redistributions in binary form must reproduce the above copyright
9916 + * notice, this list of conditions and the following disclaimer in the
9917 + * documentation and/or other materials provided with the distribution.
9918 + * * Neither the name of Freescale Semiconductor nor the
9919 + * names of its contributors may be used to endorse or promote products
9920 + * derived from this software without specific prior written permission.
9921 + *
9922 + * ALTERNATIVELY, this software may be distributed under the terms of the
9923 + * GNU General Public License ("GPL") as published by the Free Software
9924 + * Foundation, either version 2 of that License or (at your option) any
9925 + * later version.
9926 + *
9927 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9928 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9929 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9930 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9931 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9932 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9933 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9934 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9935 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9936 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9937 + */
9938 +#ifndef __FSL_DPAA2_IO_H
9939 +#define __FSL_DPAA2_IO_H
9940 +
9941 +#include <linux/types.h>
9942 +#include <linux/cpumask.h>
9943 +
9944 +#include "dpaa2-fd.h"
9945 +#include "dpaa2-global.h"
9946 +
9947 +struct dpaa2_io;
9948 +struct dpaa2_io_store;
9949 +struct device;
9950 +
9951 +/**
9952 + * DOC: DPIO Service
9953 + *
9954 + * The DPIO service provides APIs for users to interact with the datapath
9955 + * by enqueueing and dequeing frame descriptors.
9956 + *
9957 + * The following set of APIs can be used to enqueue and dequeue frames
9958 + * as well as producing notification callbacks when data is available
9959 + * for dequeue.
9960 + */
9961 +
9962 +/**
9963 + * struct dpaa2_io_desc - The DPIO descriptor
9964 + * @receives_notifications: Use notificaton mode. Non-zero if the DPIO
9965 + * has a channel.
9966 + * @has_8prio: Set to non-zero for channel with 8 priority WQs. Ignored
9967 + * unless receives_notification is TRUE.
9968 + * @cpu: The cpu index that at least interrupt handlers will
9969 + * execute on.
9970 + * @stash_affinity: The stash affinity for this portal favour 'cpu'
9971 + * @regs_cena: The cache enabled regs.
9972 + * @regs_cinh: The cache inhibited regs
9973 + * @dpio_id: The dpio index
9974 + * @qman_version: The qman version
9975 + *
9976 + * Describes the attributes and features of the DPIO object.
9977 + */
9978 +struct dpaa2_io_desc {
9979 + int receives_notifications;
9980 + int has_8prio;
9981 + int cpu;
9982 + void *regs_cena;
9983 + void *regs_cinh;
9984 + int dpio_id;
9985 + u32 qman_version;
9986 +};
9987 +
9988 +struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc);
9989 +
9990 +void dpaa2_io_down(struct dpaa2_io *d);
9991 +
9992 +irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj);
9993 +
9994 +/**
9995 + * struct dpaa2_io_notification_ctx - The DPIO notification context structure
9996 + * @cb: The callback to be invoked when the notification arrives
9997 + * @is_cdan: Zero for FQDAN, non-zero for CDAN
9998 + * @id: FQID or channel ID, needed for rearm
9999 + * @desired_cpu: The cpu on which the notifications will show up. -1 means
10000 + * any CPU.
10001 + * @dpio_id: The dpio index
10002 + * @qman64: The 64-bit context value shows up in the FQDAN/CDAN.
10003 + * @node: The list node
10004 + * @dpio_private: The dpio object internal to dpio_service
10005 + *
10006 + * Used when a FQDAN/CDAN registration is made by drivers.
10007 + */
10008 +struct dpaa2_io_notification_ctx {
10009 + void (*cb)(struct dpaa2_io_notification_ctx *);
10010 + int is_cdan;
10011 + u32 id;
10012 + int desired_cpu;
10013 + int dpio_id;
10014 + u64 qman64;
10015 + struct list_head node;
10016 + void *dpio_private;
10017 +};
10018 +
10019 +int dpaa2_io_service_register(struct dpaa2_io *service,
10020 + struct dpaa2_io_notification_ctx *ctx);
10021 +void dpaa2_io_service_deregister(struct dpaa2_io *service,
10022 + struct dpaa2_io_notification_ctx *ctx);
10023 +int dpaa2_io_service_rearm(struct dpaa2_io *service,
10024 + struct dpaa2_io_notification_ctx *ctx);
10025 +
10026 +int dpaa2_io_service_pull_fq(struct dpaa2_io *d, u32 fqid,
10027 + struct dpaa2_io_store *s);
10028 +int dpaa2_io_service_pull_channel(struct dpaa2_io *d, u32 channelid,
10029 + struct dpaa2_io_store *s);
10030 +
10031 +int dpaa2_io_service_enqueue_fq(struct dpaa2_io *d, u32 fqid,
10032 + const struct dpaa2_fd *fd);
10033 +int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d, u32 qdid, u8 prio,
10034 + u16 qdbin, const struct dpaa2_fd *fd);
10035 +int dpaa2_io_service_release(struct dpaa2_io *d, u32 bpid,
10036 + const u64 *buffers, unsigned int num_buffers);
10037 +int dpaa2_io_service_acquire(struct dpaa2_io *d, u32 bpid,
10038 + u64 *buffers, unsigned int num_buffers);
10039 +
10040 +struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames,
10041 + struct device *dev);
10042 +void dpaa2_io_store_destroy(struct dpaa2_io_store *s);
10043 +struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last);
10044 +
10045 +#ifdef CONFIG_FSL_QBMAN_DEBUG
10046 +int dpaa2_io_query_fq_count(struct dpaa2_io *d, uint32_t fqid,
10047 + uint32_t *fcnt, uint32_t *bcnt);
10048 +int dpaa2_io_query_bp_count(struct dpaa2_io *d, uint32_t bpid,
10049 + uint32_t *num);
10050 +#endif
10051 +
10052 +
10053 +/***************/
10054 +/* CSCN */
10055 +/***************/
10056 +
10057 +/**
10058 + * struct dpaa2_cscn - The CSCN message format
10059 + * @verb: identifies the type of message (should be 0x27).
10060 + * @stat: status bits related to dequeuing response (not used)
10061 + * @state: bit 0 = 0/1 if CG is no/is congested
10062 + * @reserved: reserved byte
10063 + * @cgid: congest grp ID - the first 16 bits
10064 + * @ctx: context data
10065 + *
10066 + * Congestion management can be implemented in software through
10067 + * the use of Congestion State Change Notifications (CSCN). These
10068 + * are messages written by DPAA2 hardware to memory whenever the
10069 + * instantaneous count (I_CNT field in the CG) exceeds the
10070 + * Congestion State (CS) entrance threshold, signifying congestion
10071 + * entrance, or when the instantaneous count returns below exit
10072 + * threshold, signifying congestion exit. The format of the message
10073 + * is given by the dpaa2_cscn structure. Bit 0 of the state field
10074 + * represents congestion state written by the hardware.
10075 + */
10076 +struct dpaa2_cscn {
10077 + u8 verb;
10078 + u8 stat;
10079 + u8 state;
10080 + u8 reserved;
10081 + __le32 cgid;
10082 + __le64 ctx;
10083 +};
10084 +
10085 +#define DPAA2_CSCN_SIZE 64
10086 +#define DPAA2_CSCN_ALIGN 16
10087 +
10088 +#define DPAA2_CSCN_STATE_MASK 0x1
10089 +#define DPAA2_CSCN_CONGESTED 1
10090 +
10091 +static inline bool dpaa2_cscn_state_congested(struct dpaa2_cscn *cscn)
10092 +{
10093 + return ((cscn->state & DPAA2_CSCN_STATE_MASK) == DPAA2_CSCN_CONGESTED);
10094 +}
10095 +
10096 +#endif /* __FSL_DPAA2_IO_H */
10097 diff --git a/drivers/staging/fsl-mc/include/dpbp-cmd.h b/drivers/staging/fsl-mc/include/dpbp-cmd.h
10098 deleted file mode 100644
10099 index 2860411d..00000000
10100 --- a/drivers/staging/fsl-mc/include/dpbp-cmd.h
10101 +++ /dev/null
10102 @@ -1,185 +0,0 @@
10103 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
10104 - *
10105 - * Redistribution and use in source and binary forms, with or without
10106 - * modification, are permitted provided that the following conditions are met:
10107 - * * Redistributions of source code must retain the above copyright
10108 - * notice, this list of conditions and the following disclaimer.
10109 - * * Redistributions in binary form must reproduce the above copyright
10110 - * notice, this list of conditions and the following disclaimer in the
10111 - * documentation and/or other materials provided with the distribution.
10112 - * * Neither the name of the above-listed copyright holders nor the
10113 - * names of any contributors may be used to endorse or promote products
10114 - * derived from this software without specific prior written permission.
10115 - *
10116 - *
10117 - * ALTERNATIVELY, this software may be distributed under the terms of the
10118 - * GNU General Public License ("GPL") as published by the Free Software
10119 - * Foundation, either version 2 of that License or (at your option) any
10120 - * later version.
10121 - *
10122 - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
10123 - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10124 - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10125 - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
10126 - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
10127 - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
10128 - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
10129 - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
10130 - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
10131 - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
10132 - * POSSIBILITY OF SUCH DAMAGE.
10133 - */
10134 -#ifndef _FSL_DPBP_CMD_H
10135 -#define _FSL_DPBP_CMD_H
10136 -
10137 -/* DPBP Version */
10138 -#define DPBP_VER_MAJOR 2
10139 -#define DPBP_VER_MINOR 2
10140 -
10141 -/* Command IDs */
10142 -#define DPBP_CMDID_CLOSE 0x800
10143 -#define DPBP_CMDID_OPEN 0x804
10144 -#define DPBP_CMDID_CREATE 0x904
10145 -#define DPBP_CMDID_DESTROY 0x900
10146 -
10147 -#define DPBP_CMDID_ENABLE 0x002
10148 -#define DPBP_CMDID_DISABLE 0x003
10149 -#define DPBP_CMDID_GET_ATTR 0x004
10150 -#define DPBP_CMDID_RESET 0x005
10151 -#define DPBP_CMDID_IS_ENABLED 0x006
10152 -
10153 -#define DPBP_CMDID_SET_IRQ 0x010
10154 -#define DPBP_CMDID_GET_IRQ 0x011
10155 -#define DPBP_CMDID_SET_IRQ_ENABLE 0x012
10156 -#define DPBP_CMDID_GET_IRQ_ENABLE 0x013
10157 -#define DPBP_CMDID_SET_IRQ_MASK 0x014
10158 -#define DPBP_CMDID_GET_IRQ_MASK 0x015
10159 -#define DPBP_CMDID_GET_IRQ_STATUS 0x016
10160 -#define DPBP_CMDID_CLEAR_IRQ_STATUS 0x017
10161 -
10162 -#define DPBP_CMDID_SET_NOTIFICATIONS 0x01b0
10163 -#define DPBP_CMDID_GET_NOTIFICATIONS 0x01b1
10164 -
10165 -struct dpbp_cmd_open {
10166 - __le32 dpbp_id;
10167 -};
10168 -
10169 -#define DPBP_ENABLE 0x1
10170 -
10171 -struct dpbp_rsp_is_enabled {
10172 - u8 enabled;
10173 -};
10174 -
10175 -struct dpbp_cmd_set_irq {
10176 - /* cmd word 0 */
10177 - u8 irq_index;
10178 - u8 pad[3];
10179 - __le32 irq_val;
10180 - /* cmd word 1 */
10181 - __le64 irq_addr;
10182 - /* cmd word 2 */
10183 - __le32 irq_num;
10184 -};
10185 -
10186 -struct dpbp_cmd_get_irq {
10187 - __le32 pad;
10188 - u8 irq_index;
10189 -};
10190 -
10191 -struct dpbp_rsp_get_irq {
10192 - /* response word 0 */
10193 - __le32 irq_val;
10194 - __le32 pad;
10195 - /* response word 1 */
10196 - __le64 irq_addr;
10197 - /* response word 2 */
10198 - __le32 irq_num;
10199 - __le32 type;
10200 -};
10201 -
10202 -struct dpbp_cmd_set_irq_enable {
10203 - u8 enable;
10204 - u8 pad[3];
10205 - u8 irq_index;
10206 -};
10207 -
10208 -struct dpbp_cmd_get_irq_enable {
10209 - __le32 pad;
10210 - u8 irq_index;
10211 -};
10212 -
10213 -struct dpbp_rsp_get_irq_enable {
10214 - u8 enabled;
10215 -};
10216 -
10217 -struct dpbp_cmd_set_irq_mask {
10218 - __le32 mask;
10219 - u8 irq_index;
10220 -};
10221 -
10222 -struct dpbp_cmd_get_irq_mask {
10223 - __le32 pad;
10224 - u8 irq_index;
10225 -};
10226 -
10227 -struct dpbp_rsp_get_irq_mask {
10228 - __le32 mask;
10229 -};
10230 -
10231 -struct dpbp_cmd_get_irq_status {
10232 - __le32 status;
10233 - u8 irq_index;
10234 -};
10235 -
10236 -struct dpbp_rsp_get_irq_status {
10237 - __le32 status;
10238 -};
10239 -
10240 -struct dpbp_cmd_clear_irq_status {
10241 - __le32 status;
10242 - u8 irq_index;
10243 -};
10244 -
10245 -struct dpbp_rsp_get_attributes {
10246 - /* response word 0 */
10247 - __le16 pad;
10248 - __le16 bpid;
10249 - __le32 id;
10250 - /* response word 1 */
10251 - __le16 version_major;
10252 - __le16 version_minor;
10253 -};
10254 -
10255 -struct dpbp_cmd_set_notifications {
10256 - /* cmd word 0 */
10257 - __le32 depletion_entry;
10258 - __le32 depletion_exit;
10259 - /* cmd word 1 */
10260 - __le32 surplus_entry;
10261 - __le32 surplus_exit;
10262 - /* cmd word 2 */
10263 - __le16 options;
10264 - __le16 pad[3];
10265 - /* cmd word 3 */
10266 - __le64 message_ctx;
10267 - /* cmd word 4 */
10268 - __le64 message_iova;
10269 -};
10270 -
10271 -struct dpbp_rsp_get_notifications {
10272 - /* response word 0 */
10273 - __le32 depletion_entry;
10274 - __le32 depletion_exit;
10275 - /* response word 1 */
10276 - __le32 surplus_entry;
10277 - __le32 surplus_exit;
10278 - /* response word 2 */
10279 - __le16 options;
10280 - __le16 pad[3];
10281 - /* response word 3 */
10282 - __le64 message_ctx;
10283 - /* response word 4 */
10284 - __le64 message_iova;
10285 -};
10286 -
10287 -#endif /* _FSL_DPBP_CMD_H */
10288 diff --git a/drivers/staging/fsl-mc/include/dpbp.h b/drivers/staging/fsl-mc/include/dpbp.h
10289 index e14e85a5..e9e04cce 100644
10290 --- a/drivers/staging/fsl-mc/include/dpbp.h
10291 +++ b/drivers/staging/fsl-mc/include/dpbp.h
10292 @@ -1,4 +1,5 @@
10293 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
10294 +/*
10295 + * Copyright 2013-2016 Freescale Semiconductor Inc.
10296 *
10297 * Redistribution and use in source and binary forms, with or without
10298 * modification, are permitted provided that the following conditions are met:
10299 @@ -32,7 +33,8 @@
10300 #ifndef __FSL_DPBP_H
10301 #define __FSL_DPBP_H
10302
10303 -/* Data Path Buffer Pool API
10304 +/*
10305 + * Data Path Buffer Pool API
10306 * Contains initialization APIs and runtime control APIs for DPBP
10307 */
10308
10309 @@ -44,25 +46,8 @@ int dpbp_open(struct fsl_mc_io *mc_io,
10310 u16 *token);
10311
10312 int dpbp_close(struct fsl_mc_io *mc_io,
10313 - u32 cmd_flags,
10314 - u16 token);
10315 -
10316 -/**
10317 - * struct dpbp_cfg - Structure representing DPBP configuration
10318 - * @options: place holder
10319 - */
10320 -struct dpbp_cfg {
10321 - u32 options;
10322 -};
10323 -
10324 -int dpbp_create(struct fsl_mc_io *mc_io,
10325 - u32 cmd_flags,
10326 - const struct dpbp_cfg *cfg,
10327 - u16 *token);
10328 -
10329 -int dpbp_destroy(struct fsl_mc_io *mc_io,
10330 - u32 cmd_flags,
10331 - u16 token);
10332 + u32 cmd_flags,
10333 + u16 token);
10334
10335 int dpbp_enable(struct fsl_mc_io *mc_io,
10336 u32 cmd_flags,
10337 @@ -81,140 +66,25 @@ int dpbp_reset(struct fsl_mc_io *mc_io,
10338 u32 cmd_flags,
10339 u16 token);
10340
10341 -/**
10342 - * struct dpbp_irq_cfg - IRQ configuration
10343 - * @addr: Address that must be written to signal a message-based interrupt
10344 - * @val: Value to write into irq_addr address
10345 - * @irq_num: A user defined number associated with this IRQ
10346 - */
10347 -struct dpbp_irq_cfg {
10348 - u64 addr;
10349 - u32 val;
10350 - int irq_num;
10351 -};
10352 -
10353 -int dpbp_set_irq(struct fsl_mc_io *mc_io,
10354 - u32 cmd_flags,
10355 - u16 token,
10356 - u8 irq_index,
10357 - struct dpbp_irq_cfg *irq_cfg);
10358 -
10359 -int dpbp_get_irq(struct fsl_mc_io *mc_io,
10360 - u32 cmd_flags,
10361 - u16 token,
10362 - u8 irq_index,
10363 - int *type,
10364 - struct dpbp_irq_cfg *irq_cfg);
10365 -
10366 -int dpbp_set_irq_enable(struct fsl_mc_io *mc_io,
10367 - u32 cmd_flags,
10368 - u16 token,
10369 - u8 irq_index,
10370 - u8 en);
10371 -
10372 -int dpbp_get_irq_enable(struct fsl_mc_io *mc_io,
10373 - u32 cmd_flags,
10374 - u16 token,
10375 - u8 irq_index,
10376 - u8 *en);
10377 -
10378 -int dpbp_set_irq_mask(struct fsl_mc_io *mc_io,
10379 - u32 cmd_flags,
10380 - u16 token,
10381 - u8 irq_index,
10382 - u32 mask);
10383 -
10384 -int dpbp_get_irq_mask(struct fsl_mc_io *mc_io,
10385 - u32 cmd_flags,
10386 - u16 token,
10387 - u8 irq_index,
10388 - u32 *mask);
10389 -
10390 -int dpbp_get_irq_status(struct fsl_mc_io *mc_io,
10391 - u32 cmd_flags,
10392 - u16 token,
10393 - u8 irq_index,
10394 - u32 *status);
10395 -
10396 -int dpbp_clear_irq_status(struct fsl_mc_io *mc_io,
10397 - u32 cmd_flags,
10398 - u16 token,
10399 - u8 irq_index,
10400 - u32 status);
10401 -
10402 /**
10403 * struct dpbp_attr - Structure representing DPBP attributes
10404 * @id: DPBP object ID
10405 - * @version: DPBP version
10406 * @bpid: Hardware buffer pool ID; should be used as an argument in
10407 * acquire/release operations on buffers
10408 */
10409 struct dpbp_attr {
10410 int id;
10411 - /**
10412 - * struct version - Structure representing DPBP version
10413 - * @major: DPBP major version
10414 - * @minor: DPBP minor version
10415 - */
10416 - struct {
10417 - u16 major;
10418 - u16 minor;
10419 - } version;
10420 u16 bpid;
10421 };
10422
10423 -int dpbp_get_attributes(struct fsl_mc_io *mc_io,
10424 - u32 cmd_flags,
10425 - u16 token,
10426 - struct dpbp_attr *attr);
10427 -
10428 -/**
10429 - * DPBP notifications options
10430 - */
10431 -
10432 -/**
10433 - * BPSCN write will attempt to allocate into a cache (coherent write)
10434 - */
10435 -#define DPBP_NOTIF_OPT_COHERENT_WRITE 0x00000001
10436 -
10437 -/**
10438 - * struct dpbp_notification_cfg - Structure representing DPBP notifications
10439 - * towards software
10440 - * @depletion_entry: below this threshold the pool is "depleted";
10441 - * set it to '0' to disable it
10442 - * @depletion_exit: greater than or equal to this threshold the pool exit its
10443 - * "depleted" state
10444 - * @surplus_entry: above this threshold the pool is in "surplus" state;
10445 - * set it to '0' to disable it
10446 - * @surplus_exit: less than or equal to this threshold the pool exit its
10447 - * "surplus" state
10448 - * @message_iova: MUST be given if either 'depletion_entry' or 'surplus_entry'
10449 - * is not '0' (enable); I/O virtual address (must be in DMA-able memory),
10450 - * must be 16B aligned.
10451 - * @message_ctx: The context that will be part of the BPSCN message and will
10452 - * be written to 'message_iova'
10453 - * @options: Mask of available options; use 'DPBP_NOTIF_OPT_<X>' values
10454 - */
10455 -struct dpbp_notification_cfg {
10456 - u32 depletion_entry;
10457 - u32 depletion_exit;
10458 - u32 surplus_entry;
10459 - u32 surplus_exit;
10460 - u64 message_iova;
10461 - u64 message_ctx;
10462 - u16 options;
10463 -};
10464 -
10465 -int dpbp_set_notifications(struct fsl_mc_io *mc_io,
10466 - u32 cmd_flags,
10467 - u16 token,
10468 - struct dpbp_notification_cfg *cfg);
10469 -
10470 -int dpbp_get_notifications(struct fsl_mc_io *mc_io,
10471 - u32 cmd_flags,
10472 - u16 token,
10473 - struct dpbp_notification_cfg *cfg);
10474 +int dpbp_get_attributes(struct fsl_mc_io *mc_io,
10475 + u32 cmd_flags,
10476 + u16 token,
10477 + struct dpbp_attr *attr);
10478
10479 -/** @} */
10480 +int dpbp_get_api_version(struct fsl_mc_io *mc_io,
10481 + u32 cmd_flags,
10482 + u16 *major_ver,
10483 + u16 *minor_ver);
10484
10485 #endif /* __FSL_DPBP_H */
10486 diff --git a/drivers/staging/fsl-mc/include/dpcon.h b/drivers/staging/fsl-mc/include/dpcon.h
10487 new file mode 100644
10488 index 00000000..efa23906
10489 --- /dev/null
10490 +++ b/drivers/staging/fsl-mc/include/dpcon.h
10491 @@ -0,0 +1,115 @@
10492 +/* Copyright 2013-2016 Freescale Semiconductor Inc.
10493 + *
10494 + * Redistribution and use in source and binary forms, with or without
10495 + * modification, are permitted provided that the following conditions are met:
10496 + * * Redistributions of source code must retain the above copyright
10497 + * notice, this list of conditions and the following disclaimer.
10498 + * * Redistributions in binary form must reproduce the above copyright
10499 + * notice, this list of conditions and the following disclaimer in the
10500 + * documentation and/or other materials provided with the distribution.
10501 + * * Neither the name of the above-listed copyright holders nor the
10502 + * names of any contributors may be used to endorse or promote products
10503 + * derived from this software without specific prior written permission.
10504 + *
10505 + *
10506 + * ALTERNATIVELY, this software may be distributed under the terms of the
10507 + * GNU General Public License ("GPL") as published by the Free Software
10508 + * Foundation, either version 2 of that License or (at your option) any
10509 + * later version.
10510 + *
10511 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
10512 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10513 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10514 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
10515 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
10516 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
10517 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
10518 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
10519 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
10520 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
10521 + * POSSIBILITY OF SUCH DAMAGE.
10522 + */
10523 +#ifndef __FSL_DPCON_H
10524 +#define __FSL_DPCON_H
10525 +
10526 +/* Data Path Concentrator API
10527 + * Contains initialization APIs and runtime control APIs for DPCON
10528 + */
10529 +
10530 +struct fsl_mc_io;
10531 +
10532 +/** General DPCON macros */
10533 +
10534 +/**
10535 + * Use it to disable notifications; see dpcon_set_notification()
10536 + */
10537 +#define DPCON_INVALID_DPIO_ID (int)(-1)
10538 +
10539 +int dpcon_open(struct fsl_mc_io *mc_io,
10540 + u32 cmd_flags,
10541 + int dpcon_id,
10542 + u16 *token);
10543 +
10544 +int dpcon_close(struct fsl_mc_io *mc_io,
10545 + u32 cmd_flags,
10546 + u16 token);
10547 +
10548 +int dpcon_enable(struct fsl_mc_io *mc_io,
10549 + u32 cmd_flags,
10550 + u16 token);
10551 +
10552 +int dpcon_disable(struct fsl_mc_io *mc_io,
10553 + u32 cmd_flags,
10554 + u16 token);
10555 +
10556 +int dpcon_is_enabled(struct fsl_mc_io *mc_io,
10557 + u32 cmd_flags,
10558 + u16 token,
10559 + int *en);
10560 +
10561 +int dpcon_reset(struct fsl_mc_io *mc_io,
10562 + u32 cmd_flags,
10563 + u16 token);
10564 +
10565 +/**
10566 + * struct dpcon_attr - Structure representing DPCON attributes
10567 + * @id: DPCON object ID
10568 + * @qbman_ch_id: Channel ID to be used by dequeue operation
10569 + * @num_priorities: Number of priorities for the DPCON channel (1-8)
10570 + */
10571 +struct dpcon_attr {
10572 + int id;
10573 + u16 qbman_ch_id;
10574 + u8 num_priorities;
10575 +};
10576 +
10577 +int dpcon_get_attributes(struct fsl_mc_io *mc_io,
10578 + u32 cmd_flags,
10579 + u16 token,
10580 + struct dpcon_attr *attr);
10581 +
10582 +/**
10583 + * struct dpcon_notification_cfg - Structure representing notification params
10584 + * @dpio_id: DPIO object ID; must be configured with a notification channel;
10585 + * to disable notifications set it to 'DPCON_INVALID_DPIO_ID';
10586 + * @priority: Priority selection within the DPIO channel; valid values
10587 + * are 0-7, depending on the number of priorities in that channel
10588 + * @user_ctx: User context value provided with each CDAN message
10589 + */
10590 +struct dpcon_notification_cfg {
10591 + int dpio_id;
10592 + u8 priority;
10593 + u64 user_ctx;
10594 +};
10595 +
10596 +int dpcon_set_notification(struct fsl_mc_io *mc_io,
10597 + u32 cmd_flags,
10598 + u16 token,
10599 + struct dpcon_notification_cfg *cfg);
10600 +
10601 +int dpcon_get_api_version(struct fsl_mc_io *mc_io,
10602 + u32 cmd_flags,
10603 + u16 *major_ver,
10604 + u16 *minor_ver);
10605 +
10606 +#endif /* __FSL_DPCON_H */
10607 diff --git a/drivers/staging/fsl-mc/include/dpmng.h b/drivers/staging/fsl-mc/include/dpmng.h
10608 index e5cfd017..170c07dd 100644
10609 --- a/drivers/staging/fsl-mc/include/dpmng.h
10610 +++ b/drivers/staging/fsl-mc/include/dpmng.h
10611 @@ -1,4 +1,5 @@
10612 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
10613 +/*
10614 + * Copyright 2013-2016 Freescale Semiconductor Inc.
10615 *
10616 * Redistribution and use in source and binary forms, with or without
10617 * modification, are permitted provided that the following conditions are met:
10618 @@ -32,7 +33,8 @@
10619 #ifndef __FSL_DPMNG_H
10620 #define __FSL_DPMNG_H
10621
10622 -/* Management Complex General API
10623 +/*
10624 + * Management Complex General API
10625 * Contains general API for the Management Complex firmware
10626 */
10627
10628 @@ -58,12 +60,8 @@ struct mc_version {
10629 u32 revision;
10630 };
10631
10632 -int mc_get_version(struct fsl_mc_io *mc_io,
10633 - u32 cmd_flags,
10634 - struct mc_version *mc_ver_info);
10635 -
10636 -int dpmng_get_container_id(struct fsl_mc_io *mc_io,
10637 - u32 cmd_flags,
10638 - int *container_id);
10639 +int mc_get_version(struct fsl_mc_io *mc_io,
10640 + u32 cmd_flags,
10641 + struct mc_version *mc_ver_info);
10642
10643 #endif /* __FSL_DPMNG_H */
10644 diff --git a/drivers/staging/fsl-mc/include/dpopr.h b/drivers/staging/fsl-mc/include/dpopr.h
10645 new file mode 100644
10646 index 00000000..e1110af2
10647 --- /dev/null
10648 +++ b/drivers/staging/fsl-mc/include/dpopr.h
10649 @@ -0,0 +1,110 @@
10650 +/*
10651 + * Copyright 2017 NXP
10652 + *
10653 + * Redistribution and use in source and binary forms, with or without
10654 + * modification, are permitted provided that the following conditions are met:
10655 + * * Redistributions of source code must retain the above copyright
10656 + * notice, this list of conditions and the following disclaimer.
10657 + * * Redistributions in binary form must reproduce the above copyright
10658 + * notice, this list of conditions and the following disclaimer in the
10659 + * documentation and/or other materials provided with the distribution.
10660 + * * Neither the name of the above-listed copyright holders nor the
10661 + * names of any contributors may be used to endorse or promote products
10662 + * derived from this software without specific prior written permission.
10663 + *
10664 + *
10665 + * ALTERNATIVELY, this software may be distributed under the terms of the
10666 + * GNU General Public License ("GPL") as published by the Free Software
10667 + * Foundation, either version 2 of that License or (at your option) any
10668 + * later version.
10669 + *
10670 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
10671 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10672 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10673 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
10674 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
10675 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
10676 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
10677 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
10678 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
10679 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
10680 + * POSSIBILITY OF SUCH DAMAGE.
10681 + */
10682 +#ifndef __FSL_DPOPR_H_
10683 +#define __FSL_DPOPR_H_
10684 +
10685 +/* Data Path Order Restoration API
10686 + * Contains initialization APIs and runtime APIs for the Order Restoration
10687 + */
10688 +
10689 +/** Order Restoration properties */
10690 +
10691 +/**
10692 + * Create a new Order Point Record option
10693 + */
10694 +#define OPR_OPT_CREATE 0x1
10695 +/**
10696 + * Retire an existing Order Point Record option
10697 + */
10698 +#define OPR_OPT_RETIRE 0x2
10699 +
10700 +/**
10701 + * struct opr_cfg - Structure representing OPR configuration
10702 + * @oprrws: Order point record (OPR) restoration window size (0 to 5)
10703 + * 0 - Window size is 32 frames.
10704 + * 1 - Window size is 64 frames.
10705 + * 2 - Window size is 128 frames.
10706 + * 3 - Window size is 256 frames.
10707 + * 4 - Window size is 512 frames.
10708 + * 5 - Window size is 1024 frames.
10709 + * @oa: OPR auto advance NESN window size (0 disabled, 1 enabled)
10710 + * @olws: OPR acceptable late arrival window size (0 to 3)
10711 + * 0 - Disabled. Late arrivals are always rejected.
10712 + * 1 - Window size is 32 frames.
10713 + * 2 - Window size is the same as the OPR restoration
10714 + * window size configured in the OPRRWS field.
10715 + * 3 - Window size is 8192 frames. Late arrivals are
10716 + * always accepted.
10717 + * @oeane: Order restoration list (ORL) resource exhaustion
10718 + * advance NESN enable (0 disabled, 1 enabled)
10719 + * @oloe: OPR loose ordering enable (0 disabled, 1 enabled)
10720 + */
10721 +struct opr_cfg {
10722 + u8 oprrws;
10723 + u8 oa;
10724 + u8 olws;
10725 + u8 oeane;
10726 + u8 oloe;
10727 +};
10728 +
10729 +/**
10730 + * struct opr_qry - Structure representing OPR configuration
10731 + * @enable: Enabled state
10732 + * @rip: Retirement In Progress
10733 + * @ndsn: Next dispensed sequence number
10734 + * @nesn: Next expected sequence number
10735 + * @ea_hseq: Early arrival head sequence number
10736 + * @hseq_nlis: HSEQ not last in sequence
10737 + * @ea_tseq: Early arrival tail sequence number
10738 + * @tseq_nlis: TSEQ not last in sequence
10739 + * @ea_tptr: Early arrival tail pointer
10740 + * @ea_hptr: Early arrival head pointer
10741 + * @opr_id: Order Point Record ID
10742 + * @opr_vid: Order Point Record Virtual ID
10743 + */
10744 +struct opr_qry {
10745 + char enable;
10746 + char rip;
10747 + u16 ndsn;
10748 + u16 nesn;
10749 + u16 ea_hseq;
10750 + char hseq_nlis;
10751 + u16 ea_tseq;
10752 + char tseq_nlis;
10753 + u16 ea_tptr;
10754 + u16 ea_hptr;
10755 + u16 opr_id;
10756 + u16 opr_vid;
10757 +};
10758 +
10759 +#endif /* __FSL_DPOPR_H_ */
10760 diff --git a/drivers/staging/fsl-mc/include/dprc.h b/drivers/staging/fsl-mc/include/dprc.h
10761 index 593b2bbe..8dc411ec 100644
10762 --- a/drivers/staging/fsl-mc/include/dprc.h
10763 +++ b/drivers/staging/fsl-mc/include/dprc.h
10764 @@ -1,4 +1,5 @@
10765 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
10766 +/*
10767 + * Copyright 2013-2016 Freescale Semiconductor Inc.
10768 *
10769 * Redistribution and use in source and binary forms, with or without
10770 * modification, are permitted provided that the following conditions are met:
10771 @@ -34,26 +35,13 @@
10772
10773 #include "mc-cmd.h"
10774
10775 -/* Data Path Resource Container API
10776 +/*
10777 + * Data Path Resource Container API
10778 * Contains DPRC API for managing and querying DPAA resources
10779 */
10780
10781 struct fsl_mc_io;
10782
10783 -/**
10784 - * Set this value as the icid value in dprc_cfg structure when creating a
10785 - * container, in case the ICID is not selected by the user and should be
10786 - * allocated by the DPRC from the pool of ICIDs.
10787 - */
10788 -#define DPRC_GET_ICID_FROM_POOL (u16)(~(0))
10789 -
10790 -/**
10791 - * Set this value as the portal_id value in dprc_cfg structure when creating a
10792 - * container, in case the portal ID is not specifically selected by the
10793 - * user and should be allocated by the DPRC from the pool of portal ids.
10794 - */
10795 -#define DPRC_GET_PORTAL_ID_FROM_POOL (int)(~(0))
10796 -
10797 int dprc_open(struct fsl_mc_io *mc_io,
10798 u32 cmd_flags,
10799 int container_id,
10800 @@ -63,75 +51,6 @@ int dprc_close(struct fsl_mc_io *mc_io,
10801 u32 cmd_flags,
10802 u16 token);
10803
10804 -/**
10805 - * Container general options
10806 - *
10807 - * These options may be selected at container creation by the container creator
10808 - * and can be retrieved using dprc_get_attributes()
10809 - */
10810 -
10811 -/* Spawn Policy Option allowed - Indicates that the new container is allowed
10812 - * to spawn and have its own child containers.
10813 - */
10814 -#define DPRC_CFG_OPT_SPAWN_ALLOWED 0x00000001
10815 -
10816 -/* General Container allocation policy - Indicates that the new container is
10817 - * allowed to allocate requested resources from its parent container; if not
10818 - * set, the container is only allowed to use resources in its own pools; Note
10819 - * that this is a container's global policy, but the parent container may
10820 - * override it and set specific quota per resource type.
10821 - */
10822 -#define DPRC_CFG_OPT_ALLOC_ALLOWED 0x00000002
10823 -
10824 -/* Object initialization allowed - software context associated with this
10825 - * container is allowed to invoke object initialization operations.
10826 - */
10827 -#define DPRC_CFG_OPT_OBJ_CREATE_ALLOWED 0x00000004
10828 -
10829 -/* Topology change allowed - software context associated with this
10830 - * container is allowed to invoke topology operations, such as attach/detach
10831 - * of network objects.
10832 - */
10833 -#define DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED 0x00000008
10834 -
10835 -/* AIOP - Indicates that container belongs to AIOP. */
10836 -#define DPRC_CFG_OPT_AIOP 0x00000020
10837 -
10838 -/* IRQ Config - Indicates that the container allowed to configure its IRQs. */
10839 -#define DPRC_CFG_OPT_IRQ_CFG_ALLOWED 0x00000040
10840 -
10841 -/**
10842 - * struct dprc_cfg - Container configuration options
10843 - * @icid: Container's ICID; if set to 'DPRC_GET_ICID_FROM_POOL', a free
10844 - * ICID value is allocated by the DPRC
10845 - * @portal_id: Portal ID; if set to 'DPRC_GET_PORTAL_ID_FROM_POOL', a free
10846 - * portal ID is allocated by the DPRC
10847 - * @options: Combination of 'DPRC_CFG_OPT_<X>' options
10848 - * @label: Object's label
10849 - */
10850 -struct dprc_cfg {
10851 - u16 icid;
10852 - int portal_id;
10853 - u64 options;
10854 - char label[16];
10855 -};
10856 -
10857 -int dprc_create_container(struct fsl_mc_io *mc_io,
10858 - u32 cmd_flags,
10859 - u16 token,
10860 - struct dprc_cfg *cfg,
10861 - int *child_container_id,
10862 - u64 *child_portal_offset);
10863 -
10864 -int dprc_destroy_container(struct fsl_mc_io *mc_io,
10865 - u32 cmd_flags,
10866 - u16 token,
10867 - int child_container_id);
10868 -
10869 -int dprc_reset_container(struct fsl_mc_io *mc_io,
10870 - u32 cmd_flags,
10871 - u16 token,
10872 - int child_container_id);
10873
10874 /* IRQ */
10875
10876 @@ -139,7 +58,7 @@ int dprc_reset_container(struct fsl_mc_io *mc_io,
10877 #define DPRC_IRQ_INDEX 0
10878
10879 /* Number of dprc's IRQs */
10880 -#define DPRC_NUM_OF_IRQS 1
10881 +#define DPRC_NUM_OF_IRQS 1
10882
10883 /* DPRC IRQ events */
10884
10885 @@ -151,12 +70,14 @@ int dprc_reset_container(struct fsl_mc_io *mc_io,
10886 #define DPRC_IRQ_EVENT_RES_ADDED 0x00000004
10887 /* IRQ event - Indicates that resources removed from the container */
10888 #define DPRC_IRQ_EVENT_RES_REMOVED 0x00000008
10889 -/* IRQ event - Indicates that one of the descendant containers that opened by
10890 +/*
10891 + * IRQ event - Indicates that one of the descendant containers that opened by
10892 * this container is destroyed
10893 */
10894 #define DPRC_IRQ_EVENT_CONTAINER_DESTROYED 0x00000010
10895
10896 -/* IRQ event - Indicates that on one of the container's opened object is
10897 +/*
10898 + * IRQ event - Indicates that on one of the container's opened object is
10899 * destroyed
10900 */
10901 #define DPRC_IRQ_EVENT_OBJ_DESTROYED 0x00000020
10902 @@ -171,59 +92,59 @@ int dprc_reset_container(struct fsl_mc_io *mc_io,
10903 * @irq_num: A user defined number associated with this IRQ
10904 */
10905 struct dprc_irq_cfg {
10906 - phys_addr_t paddr;
10907 - u32 val;
10908 - int irq_num;
10909 + phys_addr_t paddr;
10910 + u32 val;
10911 + int irq_num;
10912 };
10913
10914 -int dprc_set_irq(struct fsl_mc_io *mc_io,
10915 - u32 cmd_flags,
10916 - u16 token,
10917 - u8 irq_index,
10918 - struct dprc_irq_cfg *irq_cfg);
10919 -
10920 -int dprc_get_irq(struct fsl_mc_io *mc_io,
10921 - u32 cmd_flags,
10922 - u16 token,
10923 - u8 irq_index,
10924 - int *type,
10925 - struct dprc_irq_cfg *irq_cfg);
10926 -
10927 -int dprc_set_irq_enable(struct fsl_mc_io *mc_io,
10928 - u32 cmd_flags,
10929 - u16 token,
10930 - u8 irq_index,
10931 - u8 en);
10932 -
10933 -int dprc_get_irq_enable(struct fsl_mc_io *mc_io,
10934 - u32 cmd_flags,
10935 - u16 token,
10936 - u8 irq_index,
10937 - u8 *en);
10938 -
10939 -int dprc_set_irq_mask(struct fsl_mc_io *mc_io,
10940 - u32 cmd_flags,
10941 - u16 token,
10942 - u8 irq_index,
10943 - u32 mask);
10944 -
10945 -int dprc_get_irq_mask(struct fsl_mc_io *mc_io,
10946 - u32 cmd_flags,
10947 - u16 token,
10948 - u8 irq_index,
10949 - u32 *mask);
10950 -
10951 -int dprc_get_irq_status(struct fsl_mc_io *mc_io,
10952 - u32 cmd_flags,
10953 - u16 token,
10954 - u8 irq_index,
10955 - u32 *status);
10956 -
10957 -int dprc_clear_irq_status(struct fsl_mc_io *mc_io,
10958 - u32 cmd_flags,
10959 - u16 token,
10960 - u8 irq_index,
10961 - u32 status);
10962 +int dprc_set_irq(struct fsl_mc_io *mc_io,
10963 + u32 cmd_flags,
10964 + u16 token,
10965 + u8 irq_index,
10966 + struct dprc_irq_cfg *irq_cfg);
10967 +
10968 +int dprc_get_irq(struct fsl_mc_io *mc_io,
10969 + u32 cmd_flags,
10970 + u16 token,
10971 + u8 irq_index,
10972 + int *type,
10973 + struct dprc_irq_cfg *irq_cfg);
10974 +
10975 +int dprc_set_irq_enable(struct fsl_mc_io *mc_io,
10976 + u32 cmd_flags,
10977 + u16 token,
10978 + u8 irq_index,
10979 + u8 en);
10980 +
10981 +int dprc_get_irq_enable(struct fsl_mc_io *mc_io,
10982 + u32 cmd_flags,
10983 + u16 token,
10984 + u8 irq_index,
10985 + u8 *en);
10986 +
10987 +int dprc_set_irq_mask(struct fsl_mc_io *mc_io,
10988 + u32 cmd_flags,
10989 + u16 token,
10990 + u8 irq_index,
10991 + u32 mask);
10992 +
10993 +int dprc_get_irq_mask(struct fsl_mc_io *mc_io,
10994 + u32 cmd_flags,
10995 + u16 token,
10996 + u8 irq_index,
10997 + u32 *mask);
10998 +
10999 +int dprc_get_irq_status(struct fsl_mc_io *mc_io,
11000 + u32 cmd_flags,
11001 + u16 token,
11002 + u8 irq_index,
11003 + u32 *status);
11004 +
11005 +int dprc_clear_irq_status(struct fsl_mc_io *mc_io,
11006 + u32 cmd_flags,
11007 + u16 token,
11008 + u8 irq_index,
11009 + u32 status);
11010
11011 /**
11012 * struct dprc_attributes - Container attributes
11013 @@ -231,114 +152,23 @@ int dprc_clear_irq_status(struct fsl_mc_io *mc_io,
11014 * @icid: Container's ICID
11015 * @portal_id: Container's portal ID
11016 * @options: Container's options as set at container's creation
11017 - * @version: DPRC version
11018 */
11019 struct dprc_attributes {
11020 int container_id;
11021 u16 icid;
11022 int portal_id;
11023 u64 options;
11024 - /**
11025 - * struct version - DPRC version
11026 - * @major: DPRC major version
11027 - * @minor: DPRC minor version
11028 - */
11029 - struct {
11030 - u16 major;
11031 - u16 minor;
11032 - } version;
11033 -};
11034 -
11035 -int dprc_get_attributes(struct fsl_mc_io *mc_io,
11036 - u32 cmd_flags,
11037 - u16 token,
11038 - struct dprc_attributes *attributes);
11039 -
11040 -int dprc_set_res_quota(struct fsl_mc_io *mc_io,
11041 - u32 cmd_flags,
11042 - u16 token,
11043 - int child_container_id,
11044 - char *type,
11045 - u16 quota);
11046 -
11047 -int dprc_get_res_quota(struct fsl_mc_io *mc_io,
11048 - u32 cmd_flags,
11049 - u16 token,
11050 - int child_container_id,
11051 - char *type,
11052 - u16 *quota);
11053 -
11054 -/* Resource request options */
11055 -
11056 -/* Explicit resource ID request - The requested objects/resources
11057 - * are explicit and sequential (in case of resources).
11058 - * The base ID is given at res_req at base_align field
11059 - */
11060 -#define DPRC_RES_REQ_OPT_EXPLICIT 0x00000001
11061 -
11062 -/* Aligned resources request - Relevant only for resources
11063 - * request (and not objects). Indicates that resources base ID should be
11064 - * sequential and aligned to the value given at dprc_res_req base_align field
11065 - */
11066 -#define DPRC_RES_REQ_OPT_ALIGNED 0x00000002
11067 -
11068 -/* Plugged Flag - Relevant only for object assignment request.
11069 - * Indicates that after all objects assigned. An interrupt will be invoked at
11070 - * the relevant GPP. The assigned object will be marked as plugged.
11071 - * plugged objects can't be assigned from their container
11072 - */
11073 -#define DPRC_RES_REQ_OPT_PLUGGED 0x00000004
11074 -
11075 -/**
11076 - * struct dprc_res_req - Resource request descriptor, to be used in assignment
11077 - * or un-assignment of resources and objects.
11078 - * @type: Resource/object type: Represent as a NULL terminated string.
11079 - * This string may received by using dprc_get_pool() to get resource
11080 - * type and dprc_get_obj() to get object type;
11081 - * Note: it is not possible to assign/un-assign DPRC objects
11082 - * @num: Number of resources
11083 - * @options: Request options: combination of DPRC_RES_REQ_OPT_ options
11084 - * @id_base_align: In case of explicit assignment (DPRC_RES_REQ_OPT_EXPLICIT
11085 - * is set at option), this field represents the required base ID
11086 - * for resource allocation; In case of aligned assignment
11087 - * (DPRC_RES_REQ_OPT_ALIGNED is set at option), this field
11088 - * indicates the required alignment for the resource ID(s) -
11089 - * use 0 if there is no alignment or explicit ID requirements
11090 - */
11091 -struct dprc_res_req {
11092 - char type[16];
11093 - u32 num;
11094 - u32 options;
11095 - int id_base_align;
11096 };
11097
11098 -int dprc_assign(struct fsl_mc_io *mc_io,
11099 - u32 cmd_flags,
11100 - u16 token,
11101 - int container_id,
11102 - struct dprc_res_req *res_req);
11103 -
11104 -int dprc_unassign(struct fsl_mc_io *mc_io,
11105 - u32 cmd_flags,
11106 - u16 token,
11107 - int child_container_id,
11108 - struct dprc_res_req *res_req);
11109 -
11110 -int dprc_get_pool_count(struct fsl_mc_io *mc_io,
11111 - u32 cmd_flags,
11112 - u16 token,
11113 - int *pool_count);
11114 -
11115 -int dprc_get_pool(struct fsl_mc_io *mc_io,
11116 - u32 cmd_flags,
11117 - u16 token,
11118 - int pool_index,
11119 - char *type);
11120 +int dprc_get_attributes(struct fsl_mc_io *mc_io,
11121 + u32 cmd_flags,
11122 + u16 token,
11123 + struct dprc_attributes *attributes);
11124
11125 int dprc_get_obj_count(struct fsl_mc_io *mc_io,
11126 - u32 cmd_flags,
11127 - u16 token,
11128 - int *obj_count);
11129 + u32 cmd_flags,
11130 + u16 token,
11131 + int *obj_count);
11132
11133 /* Objects Attributes Flags */
11134
11135 @@ -353,7 +183,7 @@ int dprc_get_obj_count(struct fsl_mc_io *mc_io,
11136 * masters;
11137 * user is responsible for proper memory handling through IOMMU configuration.
11138 */
11139 -#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001
11140 +#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001
11141
11142 /**
11143 * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj()
11144 @@ -381,41 +211,41 @@ struct dprc_obj_desc {
11145 u16 flags;
11146 };
11147
11148 -int dprc_get_obj(struct fsl_mc_io *mc_io,
11149 - u32 cmd_flags,
11150 - u16 token,
11151 - int obj_index,
11152 - struct dprc_obj_desc *obj_desc);
11153 -
11154 -int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
11155 - u32 cmd_flags,
11156 - u16 token,
11157 - char *obj_type,
11158 - int obj_id,
11159 - struct dprc_obj_desc *obj_desc);
11160 -
11161 -int dprc_set_obj_irq(struct fsl_mc_io *mc_io,
11162 - u32 cmd_flags,
11163 - u16 token,
11164 - char *obj_type,
11165 - int obj_id,
11166 - u8 irq_index,
11167 - struct dprc_irq_cfg *irq_cfg);
11168 -
11169 -int dprc_get_obj_irq(struct fsl_mc_io *mc_io,
11170 - u32 cmd_flags,
11171 - u16 token,
11172 - char *obj_type,
11173 - int obj_id,
11174 - u8 irq_index,
11175 - int *type,
11176 - struct dprc_irq_cfg *irq_cfg);
11177 -
11178 -int dprc_get_res_count(struct fsl_mc_io *mc_io,
11179 - u32 cmd_flags,
11180 - u16 token,
11181 - char *type,
11182 - int *res_count);
11183 +int dprc_get_obj(struct fsl_mc_io *mc_io,
11184 + u32 cmd_flags,
11185 + u16 token,
11186 + int obj_index,
11187 + struct dprc_obj_desc *obj_desc);
11188 +
11189 +int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
11190 + u32 cmd_flags,
11191 + u16 token,
11192 + char *obj_type,
11193 + int obj_id,
11194 + struct dprc_obj_desc *obj_desc);
11195 +
11196 +int dprc_set_obj_irq(struct fsl_mc_io *mc_io,
11197 + u32 cmd_flags,
11198 + u16 token,
11199 + char *obj_type,
11200 + int obj_id,
11201 + u8 irq_index,
11202 + struct dprc_irq_cfg *irq_cfg);
11203 +
11204 +int dprc_get_obj_irq(struct fsl_mc_io *mc_io,
11205 + u32 cmd_flags,
11206 + u16 token,
11207 + char *obj_type,
11208 + int obj_id,
11209 + u8 irq_index,
11210 + int *type,
11211 + struct dprc_irq_cfg *irq_cfg);
11212 +
11213 +int dprc_get_res_count(struct fsl_mc_io *mc_io,
11214 + u32 cmd_flags,
11215 + u16 token,
11216 + char *type,
11217 + int *res_count);
11218
11219 /**
11220 * enum dprc_iter_status - Iteration status
11221 @@ -429,27 +259,6 @@ enum dprc_iter_status {
11222 DPRC_ITER_STATUS_LAST = 2
11223 };
11224
11225 -/**
11226 - * struct dprc_res_ids_range_desc - Resource ID range descriptor
11227 - * @base_id: Base resource ID of this range
11228 - * @last_id: Last resource ID of this range
11229 - * @iter_status: Iteration status - should be set to DPRC_ITER_STATUS_FIRST at
11230 - * first iteration; while the returned marker is DPRC_ITER_STATUS_MORE,
11231 - * additional iterations are needed, until the returned marker is
11232 - * DPRC_ITER_STATUS_LAST
11233 - */
11234 -struct dprc_res_ids_range_desc {
11235 - int base_id;
11236 - int last_id;
11237 - enum dprc_iter_status iter_status;
11238 -};
11239 -
11240 -int dprc_get_res_ids(struct fsl_mc_io *mc_io,
11241 - u32 cmd_flags,
11242 - u16 token,
11243 - char *type,
11244 - struct dprc_res_ids_range_desc *range_desc);
11245 -
11246 /* Region flags */
11247 /* Cacheable - Indicates that region should be mapped as cacheable */
11248 #define DPRC_REGION_CACHEABLE 0x00000001
11249 @@ -481,64 +290,27 @@ struct dprc_region_desc {
11250 enum dprc_region_type type;
11251 };
11252
11253 -int dprc_get_obj_region(struct fsl_mc_io *mc_io,
11254 - u32 cmd_flags,
11255 - u16 token,
11256 - char *obj_type,
11257 - int obj_id,
11258 - u8 region_index,
11259 - struct dprc_region_desc *region_desc);
11260 -
11261 -int dprc_set_obj_label(struct fsl_mc_io *mc_io,
11262 - u32 cmd_flags,
11263 - u16 token,
11264 - char *obj_type,
11265 - int obj_id,
11266 - char *label);
11267 +int dprc_get_obj_region(struct fsl_mc_io *mc_io,
11268 + u32 cmd_flags,
11269 + u16 token,
11270 + char *obj_type,
11271 + int obj_id,
11272 + u8 region_index,
11273 + struct dprc_region_desc *region_desc);
11274
11275 -/**
11276 - * struct dprc_endpoint - Endpoint description for link connect/disconnect
11277 - * operations
11278 - * @type: Endpoint object type: NULL terminated string
11279 - * @id: Endpoint object ID
11280 - * @if_id: Interface ID; should be set for endpoints with multiple
11281 - * interfaces ("dpsw", "dpdmux"); for others, always set to 0
11282 - */
11283 -struct dprc_endpoint {
11284 - char type[16];
11285 - int id;
11286 - int if_id;
11287 -};
11288 +int dprc_get_api_version(struct fsl_mc_io *mc_io,
11289 + u32 cmd_flags,
11290 + u16 *major_ver,
11291 + u16 *minor_ver);
11292
11293 -/**
11294 - * struct dprc_connection_cfg - Connection configuration.
11295 - * Used for virtual connections only
11296 - * @committed_rate: Committed rate (Mbits/s)
11297 - * @max_rate: Maximum rate (Mbits/s)
11298 - */
11299 -struct dprc_connection_cfg {
11300 - u32 committed_rate;
11301 - u32 max_rate;
11302 -};
11303 +int dprc_get_container_id(struct fsl_mc_io *mc_io,
11304 + u32 cmd_flags,
11305 + int *container_id);
11306
11307 -int dprc_connect(struct fsl_mc_io *mc_io,
11308 - u32 cmd_flags,
11309 - u16 token,
11310 - const struct dprc_endpoint *endpoint1,
11311 - const struct dprc_endpoint *endpoint2,
11312 - const struct dprc_connection_cfg *cfg);
11313 -
11314 -int dprc_disconnect(struct fsl_mc_io *mc_io,
11315 - u32 cmd_flags,
11316 - u16 token,
11317 - const struct dprc_endpoint *endpoint);
11318 -
11319 -int dprc_get_connection(struct fsl_mc_io *mc_io,
11320 - u32 cmd_flags,
11321 - u16 token,
11322 - const struct dprc_endpoint *endpoint1,
11323 - struct dprc_endpoint *endpoint2,
11324 - int *state);
11325 +int dprc_reset_container(struct fsl_mc_io *mc_io,
11326 + u32 cmd_flags,
11327 + u16 token,
11328 + int child_container_id);
11329
11330 #endif /* _FSL_DPRC_H */
11331
11332 diff --git a/drivers/staging/fsl-mc/include/mc-bus.h b/drivers/staging/fsl-mc/include/mc-bus.h
11333 index 170684a5..4d1f2d3e 100644
11334 --- a/drivers/staging/fsl-mc/include/mc-bus.h
11335 +++ b/drivers/staging/fsl-mc/include/mc-bus.h
11336 @@ -1,7 +1,7 @@
11337 /*
11338 * Freescale Management Complex (MC) bus declarations
11339 *
11340 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
11341 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
11342 * Author: German Rivera <German.Rivera@freescale.com>
11343 *
11344 * This file is licensed under the terms of the GNU General Public
11345 @@ -42,8 +42,8 @@ struct msi_domain_info;
11346 */
11347 struct fsl_mc_resource_pool {
11348 enum fsl_mc_pool_type type;
11349 - int16_t max_count;
11350 - int16_t free_count;
11351 + int max_count;
11352 + int free_count;
11353 struct mutex mutex; /* serializes access to free_list */
11354 struct list_head free_list;
11355 struct fsl_mc_bus *mc_bus;
11356 @@ -73,6 +73,7 @@ struct fsl_mc_bus {
11357 int dprc_scan_container(struct fsl_mc_device *mc_bus_dev);
11358
11359 int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev,
11360 + const char *driver_override,
11361 unsigned int *total_irq_count);
11362
11363 int __init dprc_driver_init(void);
11364 diff --git a/drivers/staging/fsl-mc/include/mc-cmd.h b/drivers/staging/fsl-mc/include/mc-cmd.h
11365 index 5decb989..2e08aa31 100644
11366 --- a/drivers/staging/fsl-mc/include/mc-cmd.h
11367 +++ b/drivers/staging/fsl-mc/include/mc-cmd.h
11368 @@ -1,4 +1,5 @@
11369 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
11370 +/*
11371 + * Copyright 2013-2016 Freescale Semiconductor Inc.
11372 *
11373 * Redistribution and use in source and binary forms, with or without
11374 * modification, are permitted provided that the following conditions are met:
11375 @@ -48,6 +49,15 @@ struct mc_command {
11376 u64 params[MC_CMD_NUM_OF_PARAMS];
11377 };
11378
11379 +struct mc_rsp_create {
11380 + __le32 object_id;
11381 +};
11382 +
11383 +struct mc_rsp_api_ver {
11384 + __le16 major_ver;
11385 + __le16 minor_ver;
11386 +};
11387 +
11388 enum mc_cmd_status {
11389 MC_CMD_STATUS_OK = 0x0, /* Completed successfully */
11390 MC_CMD_STATUS_READY = 0x1, /* Ready to be processed */
11391 @@ -72,11 +82,6 @@ enum mc_cmd_status {
11392 /* Command completion flag */
11393 #define MC_CMD_FLAG_INTR_DIS 0x01
11394
11395 -#define MC_CMD_HDR_CMDID_MASK 0xFFF0
11396 -#define MC_CMD_HDR_CMDID_SHIFT 4
11397 -#define MC_CMD_HDR_TOKEN_MASK 0xFFC0
11398 -#define MC_CMD_HDR_TOKEN_SHIFT 6
11399 -
11400 static inline u64 mc_encode_cmd_header(u16 cmd_id,
11401 u32 cmd_flags,
11402 u16 token)
11403 @@ -84,10 +89,8 @@ static inline u64 mc_encode_cmd_header(u16 cmd_id,
11404 u64 header = 0;
11405 struct mc_cmd_header *hdr = (struct mc_cmd_header *)&header;
11406
11407 - hdr->cmd_id = cpu_to_le16((cmd_id << MC_CMD_HDR_CMDID_SHIFT) &
11408 - MC_CMD_HDR_CMDID_MASK);
11409 - hdr->token = cpu_to_le16((token << MC_CMD_HDR_TOKEN_SHIFT) &
11410 - MC_CMD_HDR_TOKEN_MASK);
11411 + hdr->cmd_id = cpu_to_le16(cmd_id);
11412 + hdr->token = cpu_to_le16(token);
11413 hdr->status = MC_CMD_STATUS_READY;
11414 if (cmd_flags & MC_CMD_FLAG_PRI)
11415 hdr->flags_hw = MC_CMD_FLAG_PRI;
11416 @@ -102,7 +105,26 @@ static inline u16 mc_cmd_hdr_read_token(struct mc_command *cmd)
11417 struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header;
11418 u16 token = le16_to_cpu(hdr->token);
11419
11420 - return (token & MC_CMD_HDR_TOKEN_MASK) >> MC_CMD_HDR_TOKEN_SHIFT;
11421 + return token;
11422 +}
11423 +
11424 +static inline u32 mc_cmd_read_object_id(struct mc_command *cmd)
11425 +{
11426 + struct mc_rsp_create *rsp_params;
11427 +
11428 + rsp_params = (struct mc_rsp_create *)cmd->params;
11429 + return le32_to_cpu(rsp_params->object_id);
11430 +}
11431 +
11432 +static inline void mc_cmd_read_api_version(struct mc_command *cmd,
11433 + u16 *major_ver,
11434 + u16 *minor_ver)
11435 +{
11436 + struct mc_rsp_api_ver *rsp_params;
11437 +
11438 + rsp_params = (struct mc_rsp_api_ver *)cmd->params;
11439 + *major_ver = le16_to_cpu(rsp_params->major_ver);
11440 + *minor_ver = le16_to_cpu(rsp_params->minor_ver);
11441 }
11442
11443 #endif /* __FSL_MC_CMD_H */
11444 diff --git a/drivers/staging/fsl-mc/include/mc-sys.h b/drivers/staging/fsl-mc/include/mc-sys.h
11445 index 89ad0cf5..dca7f908 100644
11446 --- a/drivers/staging/fsl-mc/include/mc-sys.h
11447 +++ b/drivers/staging/fsl-mc/include/mc-sys.h
11448 @@ -1,4 +1,5 @@
11449 -/* Copyright 2013-2014 Freescale Semiconductor Inc.
11450 +/*
11451 + * Copyright 2013-2016 Freescale Semiconductor Inc.
11452 *
11453 * Interface of the I/O services to send MC commands to the MC hardware
11454 *
11455 diff --git a/drivers/staging/fsl-mc/include/mc.h b/drivers/staging/fsl-mc/include/mc.h
11456 index f6e720e8..c23b78a4 100644
11457 --- a/drivers/staging/fsl-mc/include/mc.h
11458 +++ b/drivers/staging/fsl-mc/include/mc.h
11459 @@ -1,7 +1,7 @@
11460 /*
11461 * Freescale Management Complex (MC) bus public interface
11462 *
11463 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
11464 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
11465 * Author: German Rivera <German.Rivera@freescale.com>
11466 *
11467 * This file is licensed under the terms of the GNU General Public
11468 @@ -81,7 +81,7 @@ enum fsl_mc_pool_type {
11469 */
11470 struct fsl_mc_resource {
11471 enum fsl_mc_pool_type type;
11472 - int32_t id;
11473 + s32 id;
11474 void *data;
11475 struct fsl_mc_resource_pool *parent_pool;
11476 struct list_head node;
11477 @@ -122,6 +122,7 @@ struct fsl_mc_device_irq {
11478 * @regions: pointer to array of MMIO region entries
11479 * @irqs: pointer to array of pointers to interrupts allocated to this device
11480 * @resource: generic resource associated with this MC object device, if any.
11481 + * @driver_override: Driver name to force a match
11482 *
11483 * Generic device object for MC object devices that are "attached" to a
11484 * MC bus.
11485 @@ -154,6 +155,7 @@ struct fsl_mc_device {
11486 struct resource *regions;
11487 struct fsl_mc_device_irq **irqs;
11488 struct fsl_mc_resource *resource;
11489 + const char *driver_override;
11490 };
11491
11492 #define to_fsl_mc_device(_dev) \
11493 @@ -175,6 +177,8 @@ struct fsl_mc_device {
11494 #define fsl_mc_driver_register(drv) \
11495 __fsl_mc_driver_register(drv, THIS_MODULE)
11496
11497 +void fsl_mc_device_remove(struct fsl_mc_device *mc_dev);
11498 +
11499 int __must_check __fsl_mc_driver_register(struct fsl_mc_driver *fsl_mc_driver,
11500 struct module *owner);
11501
11502 @@ -198,4 +202,13 @@ int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev);
11503
11504 void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev);
11505
11506 +void fsl_mc_dma_configure(struct fsl_mc_device *mc_dev,
11507 + struct device_node *fsl_mc_platform_node, int coherent);
11508 +
11509 +#ifdef CONFIG_FSL_MC_BUS
11510 +struct iommu_group *fsl_mc_device_group(struct device *dev);
11511 +#else
11512 +#define fsl_mc_device_group(__dev) NULL
11513 +#endif
11514 +
11515 #endif /* _FSL_MC_H_ */
11516 --
11517 2.14.1
11518
Staging tree of dedeckeh