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[openwrt/staging/dedeckeh.git] / target / linux / lantiq / patches-4.9 / 0028-NET-lantiq-various-etop-fixes.patch
1 From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 9 Sep 2014 22:45:34 +0200
4 Subject: [PATCH 28/36] NET: lantiq: various etop fixes
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++-----------
9 1 file changed, 389 insertions(+), 166 deletions(-)
10
11 --- a/drivers/net/ethernet/lantiq_etop.c
12 +++ b/drivers/net/ethernet/lantiq_etop.c
13 @@ -11,7 +11,7 @@
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 *
17 - * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
18 + * Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
19 */
20
21 #include <linux/kernel.h>
22 @@ -30,11 +30,16 @@
23 #include <linux/mm.h>
24 #include <linux/platform_device.h>
25 #include <linux/ethtool.h>
26 +#include <linux/if_vlan.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/io.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/module.h>
32 +#include <linux/clk.h>
33 +#include <linux/of_net.h>
34 +#include <linux/of_irq.h>
35 +#include <linux/of_platform.h>
36
37 #include <asm/checksum.h>
38
39 @@ -42,7 +47,7 @@
40 #include <xway_dma.h>
41 #include <lantiq_platform.h>
42
43 -#define LTQ_ETOP_MDIO 0x11804
44 +#define LTQ_ETOP_MDIO_ACC 0x11804
45 #define MDIO_REQUEST 0x80000000
46 #define MDIO_READ 0x40000000
47 #define MDIO_ADDR_MASK 0x1f
48 @@ -51,44 +56,91 @@
49 #define MDIO_REG_OFFSET 0x10
50 #define MDIO_VAL_MASK 0xffff
51
52 -#define PPE32_CGEN 0x800
53 -#define LQ_PPE32_ENET_MAC_CFG 0x1840
54 +#define LTQ_ETOP_MDIO_CFG 0x11800
55 +#define MDIO_CFG_MASK 0x6
56 +
57 +#define LTQ_ETOP_CFG 0x11808
58 +#define LTQ_ETOP_IGPLEN 0x11820
59 +#define LTQ_ETOP_MAC_CFG 0x11840
60
61 #define LTQ_ETOP_ENETS0 0x11850
62 #define LTQ_ETOP_MAC_DA0 0x1186C
63 #define LTQ_ETOP_MAC_DA1 0x11870
64 -#define LTQ_ETOP_CFG 0x16020
65 -#define LTQ_ETOP_IGPLEN 0x16080
66 +
67 +#define MAC_CFG_MASK 0xfff
68 +#define MAC_CFG_CGEN (1 << 11)
69 +#define MAC_CFG_DUPLEX (1 << 2)
70 +#define MAC_CFG_SPEED (1 << 1)
71 +#define MAC_CFG_LINK (1 << 0)
72
73 #define MAX_DMA_CHAN 0x8
74 #define MAX_DMA_CRC_LEN 0x4
75 #define MAX_DMA_DATA_LEN 0x600
76
77 #define ETOP_FTCU BIT(28)
78 -#define ETOP_MII_MASK 0xf
79 -#define ETOP_MII_NORMAL 0xd
80 -#define ETOP_MII_REVERSE 0xe
81 #define ETOP_PLEN_UNDER 0x40
82 -#define ETOP_CGEN 0x800
83 +#define ETOP_CFG_MII0 0x01
84
85 -/* use 2 static channels for TX/RX */
86 -#define LTQ_ETOP_TX_CHANNEL 1
87 -#define LTQ_ETOP_RX_CHANNEL 6
88 -#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
89 -#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
90 +#define ETOP_CFG_MASK 0xfff
91 +#define ETOP_CFG_FEN0 (1 << 8)
92 +#define ETOP_CFG_SEN0 (1 << 6)
93 +#define ETOP_CFG_OFF1 (1 << 3)
94 +#define ETOP_CFG_REMII0 (1 << 1)
95 +#define ETOP_CFG_OFF0 (1 << 0)
96 +
97 +#define LTQ_GBIT_MDIO_CTL 0xCC
98 +#define LTQ_GBIT_MDIO_DATA 0xd0
99 +#define LTQ_GBIT_GCTL0 0x68
100 +#define LTQ_GBIT_PMAC_HD_CTL 0x8c
101 +#define LTQ_GBIT_P0_CTL 0x4
102 +#define LTQ_GBIT_PMAC_RX_IPG 0xa8
103 +#define LTQ_GBIT_RGMII_CTL 0x78
104 +
105 +#define PMAC_HD_CTL_AS (1 << 19)
106 +#define PMAC_HD_CTL_RXSH (1 << 22)
107 +
108 +/* Switch Enable (0=disable, 1=enable) */
109 +#define GCTL0_SE 0x80000000
110 +/* Disable MDIO auto polling (0=disable, 1=enable) */
111 +#define PX_CTL_DMDIO 0x00400000
112 +
113 +/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
114 +#define MDC_CLOCK_MASK 0xff000000
115 +#define MDC_CLOCK_OFFSET 24
116 +
117 +/* register information for the gbit's MDIO bus */
118 +#define MDIO_XR9_REQUEST 0x00008000
119 +#define MDIO_XR9_READ 0x00000800
120 +#define MDIO_XR9_WRITE 0x00000400
121 +#define MDIO_XR9_REG_MASK 0x1f
122 +#define MDIO_XR9_ADDR_MASK 0x1f
123 +#define MDIO_XR9_RD_MASK 0xffff
124 +#define MDIO_XR9_REG_OFFSET 0
125 +#define MDIO_XR9_ADDR_OFFSET 5
126 +#define MDIO_XR9_WR_OFFSET 16
127
128 +#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \
129 + (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
130 +
131 +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
132 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
133 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
134 #define ltq_etop_w32_mask(x, y, z) \
135 ltq_w32_mask(x, y, ltq_etop_membase + (z))
136
137 -#define DRV_VERSION "1.0"
138 +#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x))
139 +#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y))
140 +#define ltq_gbit_w32_mask(x, y, z) \
141 + ltq_w32_mask(x, y, ltq_gbit_membase + (z))
142 +
143 +#define DRV_VERSION "1.2"
144
145 static void __iomem *ltq_etop_membase;
146 +static void __iomem *ltq_gbit_membase;
147
148 struct ltq_etop_chan {
149 - int idx;
150 int tx_free;
151 + int irq;
152 struct net_device *netdev;
153 struct napi_struct napi;
154 struct ltq_dma_channel dma;
155 @@ -98,21 +150,34 @@ struct ltq_etop_chan {
156 struct ltq_etop_priv {
157 struct net_device *netdev;
158 struct platform_device *pdev;
159 - struct ltq_eth_data *pldata;
160 struct resource *res;
161
162 struct mii_bus *mii_bus;
163
164 - struct ltq_etop_chan ch[MAX_DMA_CHAN];
165 - int tx_free[MAX_DMA_CHAN >> 1];
166 + struct ltq_etop_chan txch;
167 + struct ltq_etop_chan rxch;
168 +
169 + int tx_irq;
170 + int rx_irq;
171 +
172 + unsigned char mac[6];
173 + int mii_mode;
174
175 spinlock_t lock;
176 +
177 + struct clk *clk_ppe;
178 + struct clk *clk_switch;
179 + struct clk *clk_ephy;
180 + struct clk *clk_ephycgu;
181 };
182
183 +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
184 + int phy_reg, u16 phy_data);
185 +
186 static int
187 ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
188 {
189 - ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
190 + ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
191 if (!ch->skb[ch->dma.desc])
192 return -ENOMEM;
193 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
194 @@ -147,8 +212,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan
195 spin_unlock_irqrestore(&priv->lock, flags);
196
197 skb_put(skb, len);
198 + skb->dev = ch->netdev;
199 skb->protocol = eth_type_trans(skb, ch->netdev);
200 netif_receive_skb(skb);
201 + ch->netdev->stats.rx_packets++;
202 + ch->netdev->stats.rx_bytes += len;
203 }
204
205 static int
206 @@ -156,8 +224,10 @@ ltq_etop_poll_rx(struct napi_struct *nap
207 {
208 struct ltq_etop_chan *ch = container_of(napi,
209 struct ltq_etop_chan, napi);
210 + struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
211 int rx = 0;
212 int complete = 0;
213 + unsigned long flags;
214
215 while ((rx < budget) && !complete) {
216 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
217 @@ -171,7 +241,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
218 }
219 if (complete || !rx) {
220 napi_complete(&ch->napi);
221 + spin_lock_irqsave(&priv->lock, flags);
222 ltq_dma_ack_irq(&ch->dma);
223 + spin_unlock_irqrestore(&priv->lock, flags);
224 }
225 return rx;
226 }
227 @@ -183,12 +255,14 @@ ltq_etop_poll_tx(struct napi_struct *nap
228 container_of(napi, struct ltq_etop_chan, napi);
229 struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
230 struct netdev_queue *txq =
231 - netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
232 + netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
233 unsigned long flags;
234
235 spin_lock_irqsave(&priv->lock, flags);
236 while ((ch->dma.desc_base[ch->tx_free].ctl &
237 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
238 + ch->netdev->stats.tx_packets++;
239 + ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
240 dev_kfree_skb_any(ch->skb[ch->tx_free]);
241 ch->skb[ch->tx_free] = NULL;
242 memset(&ch->dma.desc_base[ch->tx_free], 0,
243 @@ -201,7 +275,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
244 if (netif_tx_queue_stopped(txq))
245 netif_tx_start_queue(txq);
246 napi_complete(&ch->napi);
247 + spin_lock_irqsave(&priv->lock, flags);
248 ltq_dma_ack_irq(&ch->dma);
249 + spin_unlock_irqrestore(&priv->lock, flags);
250 return 1;
251 }
252
253 @@ -209,9 +285,10 @@ static irqreturn_t
254 ltq_etop_dma_irq(int irq, void *_priv)
255 {
256 struct ltq_etop_priv *priv = _priv;
257 - int ch = irq - LTQ_DMA_CH0_INT;
258 -
259 - napi_schedule(&priv->ch[ch].napi);
260 + if (irq == priv->txch.dma.irq)
261 + napi_schedule(&priv->txch.napi);
262 + else
263 + napi_schedule(&priv->rxch.napi);
264 return IRQ_HANDLED;
265 }
266
267 @@ -223,7 +300,7 @@ ltq_etop_free_channel(struct net_device
268 ltq_dma_free(&ch->dma);
269 if (ch->dma.irq)
270 free_irq(ch->dma.irq, priv);
271 - if (IS_RX(ch->idx)) {
272 + if (ch == &priv->txch) {
273 int desc;
274 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
275 dev_kfree_skb_any(ch->skb[ch->dma.desc]);
276 @@ -234,65 +311,133 @@ static void
277 ltq_etop_hw_exit(struct net_device *dev)
278 {
279 struct ltq_etop_priv *priv = netdev_priv(dev);
280 - int i;
281
282 - ltq_pmu_disable(PMU_PPE);
283 - for (i = 0; i < MAX_DMA_CHAN; i++)
284 - if (IS_TX(i) || IS_RX(i))
285 - ltq_etop_free_channel(dev, &priv->ch[i]);
286 + clk_disable(priv->clk_ppe);
287 +
288 + if (of_machine_is_compatible("lantiq,ar9"))
289 + clk_disable(priv->clk_switch);
290 +
291 + if (of_machine_is_compatible("lantiq,ase")) {
292 + clk_disable(priv->clk_ephy);
293 + clk_disable(priv->clk_ephycgu);
294 + }
295 +
296 + ltq_etop_free_channel(dev, &priv->txch);
297 + ltq_etop_free_channel(dev, &priv->rxch);
298 +}
299 +
300 +static void
301 +ltq_etop_gbit_init(struct net_device *dev)
302 +{
303 + struct ltq_etop_priv *priv = netdev_priv(dev);
304 +
305 + clk_enable(priv->clk_switch);
306 +
307 + /* enable gbit port0 on the SoC */
308 + ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);
309 +
310 + ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
311 + /* disable MDIO auto polling mode */
312 + ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
313 + /* set 1522 packet size */
314 + ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
315 + /* disable pmac & dmac headers */
316 + ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
317 + LTQ_GBIT_PMAC_HD_CTL);
318 + /* Due to traffic halt when burst length 8,
319 + replace default IPG value with 0x3B */
320 + ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
321 + /* set mdc clock to 2.5 MHz */
322 + ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
323 + LTQ_GBIT_RGMII_CTL);
324 }
325
326 static int
327 ltq_etop_hw_init(struct net_device *dev)
328 {
329 struct ltq_etop_priv *priv = netdev_priv(dev);
330 - int i;
331 + int mii_mode = priv->mii_mode;
332
333 - ltq_pmu_enable(PMU_PPE);
334 + clk_enable(priv->clk_ppe);
335
336 - switch (priv->pldata->mii_mode) {
337 + if (of_machine_is_compatible("lantiq,ar9")) {
338 + ltq_etop_gbit_init(dev);
339 + /* force the etops link to the gbit to MII */
340 + mii_mode = PHY_INTERFACE_MODE_MII;
341 + }
342 + ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
343 + ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
344 + MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
345 +
346 + switch (mii_mode) {
347 case PHY_INTERFACE_MODE_RMII:
348 - ltq_etop_w32_mask(ETOP_MII_MASK,
349 - ETOP_MII_REVERSE, LTQ_ETOP_CFG);
350 + ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
351 + ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
352 break;
353
354 case PHY_INTERFACE_MODE_MII:
355 - ltq_etop_w32_mask(ETOP_MII_MASK,
356 - ETOP_MII_NORMAL, LTQ_ETOP_CFG);
357 + ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
358 + ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
359 break;
360
361 default:
362 + if (of_machine_is_compatible("lantiq,ase")) {
363 + clk_enable(priv->clk_ephy);
364 + /* disable external MII */
365 + ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
366 + /* enable clock for internal PHY */
367 + clk_enable(priv->clk_ephycgu);
368 + /* we need to write this magic to the internal phy to
369 + make it work */
370 + ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
371 + pr_info("Selected EPHY mode\n");
372 + break;
373 + }
374 netdev_err(dev, "unknown mii mode %d\n",
375 - priv->pldata->mii_mode);
376 + mii_mode);
377 return -ENOTSUPP;
378 }
379
380 - /* enable crc generation */
381 - ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
382 + return 0;
383 +}
384 +
385 +static int
386 +ltq_etop_dma_init(struct net_device *dev)
387 +{
388 + struct ltq_etop_priv *priv = netdev_priv(dev);
389 + int tx = priv->tx_irq - LTQ_DMA_ETOP;
390 + int rx = priv->rx_irq - LTQ_DMA_ETOP;
391 + int err;
392
393 ltq_dma_init_port(DMA_PORT_ETOP);
394
395 - for (i = 0; i < MAX_DMA_CHAN; i++) {
396 - int irq = LTQ_DMA_CH0_INT + i;
397 - struct ltq_etop_chan *ch = &priv->ch[i];
398 -
399 - ch->idx = ch->dma.nr = i;
400 -
401 - if (IS_TX(i)) {
402 - ltq_dma_alloc_tx(&ch->dma);
403 - request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
404 - } else if (IS_RX(i)) {
405 - ltq_dma_alloc_rx(&ch->dma);
406 - for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
407 - ch->dma.desc++)
408 - if (ltq_etop_alloc_skb(ch))
409 - return -ENOMEM;
410 - ch->dma.desc = 0;
411 - request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
412 + priv->txch.dma.nr = tx;
413 + ltq_dma_alloc_tx(&priv->txch.dma);
414 + err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv);
415 + if (err) {
416 + netdev_err(dev, "failed to allocate tx irq\n");
417 + goto err_out;
418 + }
419 + priv->txch.dma.irq = priv->tx_irq;
420 +
421 + priv->rxch.dma.nr = rx;
422 + ltq_dma_alloc_rx(&priv->rxch.dma);
423 + for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
424 + priv->rxch.dma.desc++) {
425 + if (ltq_etop_alloc_skb(&priv->rxch)) {
426 + netdev_err(dev, "failed to allocate skbs\n");
427 + err = -ENOMEM;
428 + goto err_out;
429 }
430 - ch->dma.irq = irq;
431 }
432 - return 0;
433 + priv->rxch.dma.desc = 0;
434 + err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv);
435 + if (err)
436 + netdev_err(dev, "failed to allocate rx irq\n");
437 + else
438 + priv->rxch.dma.irq = priv->rx_irq;
439 +err_out:
440 + return err;
441 }
442
443 static void
444 @@ -306,7 +451,10 @@ ltq_etop_get_drvinfo(struct net_device *
445 static int
446 ltq_etop_nway_reset(struct net_device *dev)
447 {
448 - return phy_start_aneg(dev->phydev);
449 + if (dev->phydev)
450 + return phy_start_aneg(dev->phydev);
451 + else
452 + return 0;
453 }
454
455 static const struct ethtool_ops ltq_etop_ethtool_ops = {
456 @@ -317,6 +465,39 @@ static const struct ethtool_ops ltq_etop
457 };
458
459 static int
460 +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
461 + int phy_reg, u16 phy_data)
462 +{
463 + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
464 + (phy_data << MDIO_XR9_WR_OFFSET) |
465 + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
466 + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
467 +
468 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
469 + ;
470 + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
471 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
472 + ;
473 + return 0;
474 +}
475 +
476 +static int
477 +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
478 +{
479 + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
480 + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
481 + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
482 +
483 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
484 + ;
485 + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
486 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
487 + ;
488 + val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
489 + return val;
490 +}
491 +
492 +static int
493 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
494 {
495 u32 val = MDIO_REQUEST |
496 @@ -324,9 +505,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
497 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
498 phy_data;
499
500 - while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
501 + while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
502 ;
503 - ltq_etop_w32(val, LTQ_ETOP_MDIO);
504 + ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
505 return 0;
506 }
507
508 @@ -337,12 +518,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
509 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
510 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
511
512 - while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
513 + while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
514 ;
515 - ltq_etop_w32(val, LTQ_ETOP_MDIO);
516 - while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
517 + ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
518 + while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
519 ;
520 - val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
521 + val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
522 return val;
523 }
524
525 @@ -357,8 +538,18 @@ ltq_etop_mdio_probe(struct net_device *d
526 {
527 struct ltq_etop_priv *priv = netdev_priv(dev);
528 struct phy_device *phydev;
529 + u32 phy_supported = (SUPPORTED_10baseT_Half
530 + | SUPPORTED_10baseT_Full
531 + | SUPPORTED_100baseT_Half
532 + | SUPPORTED_100baseT_Full
533 + | SUPPORTED_Autoneg
534 + | SUPPORTED_MII
535 + | SUPPORTED_TP);
536
537 - phydev = phy_find_first(priv->mii_bus);
538 + if (of_machine_is_compatible("lantiq,ase"))
539 + phydev = mdiobus_get_phy(priv->mii_bus, 8);
540 + else
541 + phydev = mdiobus_get_phy(priv->mii_bus, 0);
542
543 if (!phydev) {
544 netdev_err(dev, "no PHY found\n");
545 @@ -366,21 +557,18 @@ ltq_etop_mdio_probe(struct net_device *d
546 }
547
548 phydev = phy_connect(dev, phydev_name(phydev),
549 - &ltq_etop_mdio_link, priv->pldata->mii_mode);
550 + &ltq_etop_mdio_link, priv->mii_mode);
551
552 if (IS_ERR(phydev)) {
553 netdev_err(dev, "Could not attach to PHY\n");
554 return PTR_ERR(phydev);
555 }
556
557 - phydev->supported &= (SUPPORTED_10baseT_Half
558 - | SUPPORTED_10baseT_Full
559 - | SUPPORTED_100baseT_Half
560 - | SUPPORTED_100baseT_Full
561 - | SUPPORTED_Autoneg
562 - | SUPPORTED_MII
563 - | SUPPORTED_TP);
564 + if (of_machine_is_compatible("lantiq,ar9"))
565 + phy_supported |= SUPPORTED_1000baseT_Half
566 + | SUPPORTED_1000baseT_Full;
567
568 + phydev->supported &= phy_supported;
569 phydev->advertising = phydev->supported;
570 phy_attached_info(phydev);
571
572 @@ -401,8 +589,13 @@ ltq_etop_mdio_init(struct net_device *de
573 }
574
575 priv->mii_bus->priv = dev;
576 - priv->mii_bus->read = ltq_etop_mdio_rd;
577 - priv->mii_bus->write = ltq_etop_mdio_wr;
578 + if (of_machine_is_compatible("lantiq,ar9")) {
579 + priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
580 + priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
581 + } else {
582 + priv->mii_bus->read = ltq_etop_mdio_rd;
583 + priv->mii_bus->write = ltq_etop_mdio_wr;
584 + }
585 priv->mii_bus->name = "ltq_mii";
586 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
587 priv->pdev->name, priv->pdev->id);
588 @@ -439,17 +632,19 @@ static int
589 ltq_etop_open(struct net_device *dev)
590 {
591 struct ltq_etop_priv *priv = netdev_priv(dev);
592 - int i;
593 + unsigned long flags;
594
595 - for (i = 0; i < MAX_DMA_CHAN; i++) {
596 - struct ltq_etop_chan *ch = &priv->ch[i];
597 + napi_enable(&priv->txch.napi);
598 + napi_enable(&priv->rxch.napi);
599 +
600 + spin_lock_irqsave(&priv->lock, flags);
601 + ltq_dma_open(&priv->txch.dma);
602 + ltq_dma_open(&priv->rxch.dma);
603 + spin_unlock_irqrestore(&priv->lock, flags);
604 +
605 + if (dev->phydev)
606 + phy_start(dev->phydev);
607
608 - if (!IS_TX(i) && (!IS_RX(i)))
609 - continue;
610 - ltq_dma_open(&ch->dma);
611 - napi_enable(&ch->napi);
612 - }
613 - phy_start(dev->phydev);
614 netif_tx_start_all_queues(dev);
615 return 0;
616 }
617 @@ -458,18 +653,19 @@ static int
618 ltq_etop_stop(struct net_device *dev)
619 {
620 struct ltq_etop_priv *priv = netdev_priv(dev);
621 - int i;
622 + unsigned long flags;
623
624 netif_tx_stop_all_queues(dev);
625 - phy_stop(dev->phydev);
626 - for (i = 0; i < MAX_DMA_CHAN; i++) {
627 - struct ltq_etop_chan *ch = &priv->ch[i];
628 -
629 - if (!IS_RX(i) && !IS_TX(i))
630 - continue;
631 - napi_disable(&ch->napi);
632 - ltq_dma_close(&ch->dma);
633 - }
634 + if (dev->phydev)
635 + phy_stop(dev->phydev);
636 + napi_disable(&priv->txch.napi);
637 + napi_disable(&priv->rxch.napi);
638 +
639 + spin_lock_irqsave(&priv->lock, flags);
640 + ltq_dma_close(&priv->txch.dma);
641 + ltq_dma_close(&priv->rxch.dma);
642 + spin_unlock_irqrestore(&priv->lock, flags);
643 +
644 return 0;
645 }
646
647 @@ -479,16 +675,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
648 int queue = skb_get_queue_mapping(skb);
649 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
650 struct ltq_etop_priv *priv = netdev_priv(dev);
651 - struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
652 - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
653 - int len;
654 + struct ltq_dma_desc *desc =
655 + &priv->txch.dma.desc_base[priv->txch.dma.desc];
656 unsigned long flags;
657 u32 byte_offset;
658 + int len;
659
660 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
661
662 - if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
663 - dev_kfree_skb_any(skb);
664 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
665 + priv->txch.skb[priv->txch.dma.desc]) {
666 netdev_err(dev, "tx ring full\n");
667 netif_tx_stop_queue(txq);
668 return NETDEV_TX_BUSY;
669 @@ -496,7 +692,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
670
671 /* dma needs to start on a 16 byte aligned address */
672 byte_offset = CPHYSADDR(skb->data) % 16;
673 - ch->skb[ch->dma.desc] = skb;
674 + priv->txch.skb[priv->txch.dma.desc] = skb;
675
676 netif_trans_update(dev);
677
678 @@ -506,11 +702,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
679 wmb();
680 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
681 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
682 - ch->dma.desc++;
683 - ch->dma.desc %= LTQ_DESC_NUM;
684 + priv->txch.dma.desc++;
685 + priv->txch.dma.desc %= LTQ_DESC_NUM;
686 spin_unlock_irqrestore(&priv->lock, flags);
687
688 - if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
689 + if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
690 netif_tx_stop_queue(txq);
691
692 return NETDEV_TX_OK;
693 @@ -525,8 +721,10 @@ ltq_etop_change_mtu(struct net_device *d
694 struct ltq_etop_priv *priv = netdev_priv(dev);
695 unsigned long flags;
696
697 + int max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
698 +
699 spin_lock_irqsave(&priv->lock, flags);
700 - ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu,
701 + ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max,
702 LTQ_ETOP_IGPLEN);
703 spin_unlock_irqrestore(&priv->lock, flags);
704 }
705 @@ -595,6 +793,9 @@ ltq_etop_init(struct net_device *dev)
706 if (err)
707 goto err_hw;
708 ltq_etop_change_mtu(dev, 1500);
709 + err = ltq_etop_dma_init(dev);
710 + if (err)
711 + goto err_hw;
712
713 memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
714 if (!is_valid_ether_addr(mac.sa_data)) {
715 @@ -612,9 +813,10 @@ ltq_etop_init(struct net_device *dev)
716 dev->addr_assign_type = NET_ADDR_RANDOM;
717
718 ltq_etop_set_multicast_list(dev);
719 - err = ltq_etop_mdio_init(dev);
720 - if (err)
721 - goto err_netdev;
722 + if (!ltq_etop_mdio_init(dev))
723 + dev->ethtool_ops = &ltq_etop_ethtool_ops;
724 + else
725 + pr_warn("etop: mdio probe failed\n");;
726 return 0;
727
728 err_netdev:
729 @@ -634,6 +836,9 @@ ltq_etop_tx_timeout(struct net_device *d
730 err = ltq_etop_hw_init(dev);
731 if (err)
732 goto err_hw;
733 + err = ltq_etop_dma_init(dev);
734 + if (err)
735 + goto err_hw;
736 netif_trans_update(dev);
737 netif_wake_queue(dev);
738 return;
739 @@ -657,14 +862,19 @@ static const struct net_device_ops ltq_e
740 .ndo_tx_timeout = ltq_etop_tx_timeout,
741 };
742
743 -static int __init
744 -ltq_etop_probe(struct platform_device *pdev)
745 +static int ltq_etop_probe(struct platform_device *pdev)
746 {
747 struct net_device *dev;
748 struct ltq_etop_priv *priv;
749 - struct resource *res;
750 + struct resource *res, *gbit_res, irqres[2];
751 + const u8 *mac;
752 int err;
753 - int i;
754 +
755 + err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
756 + if (err != 2) {
757 + dev_err(&pdev->dev, "failed to get etop irqs\n");
758 + return -EINVAL;
759 + }
760
761 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
762 if (!res) {
763 @@ -690,31 +900,62 @@ ltq_etop_probe(struct platform_device *p
764 goto err_out;
765 }
766
767 - dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
768 - if (!dev) {
769 - err = -ENOMEM;
770 - goto err_out;
771 + if (of_machine_is_compatible("lantiq,ar9")) {
772 + gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
773 + if (!gbit_res) {
774 + dev_err(&pdev->dev, "failed to get gbit resource\n");
775 + err = -ENOENT;
776 + goto err_out;
777 + }
778 + ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
779 + gbit_res->start, resource_size(gbit_res));
780 + if (!ltq_gbit_membase) {
781 + dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
782 + pdev->id);
783 + err = -ENOMEM;
784 + goto err_out;
785 + }
786 }
787 +
788 + dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
789 strcpy(dev->name, "eth%d");
790 dev->netdev_ops = &ltq_eth_netdev_ops;
791 - dev->ethtool_ops = &ltq_etop_ethtool_ops;
792 priv = netdev_priv(dev);
793 priv->res = res;
794 priv->pdev = pdev;
795 - priv->pldata = dev_get_platdata(&pdev->dev);
796 priv->netdev = dev;
797 + priv->tx_irq = irqres[0].start;
798 + priv->rx_irq = irqres[1].start;
799 + priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
800 +
801 + mac = of_get_mac_address(pdev->dev.of_node);
802 + if (mac)
803 + memcpy(priv->mac, mac, ETH_ALEN);
804 +
805 + priv->clk_ppe = clk_get(&pdev->dev, NULL);
806 + if (IS_ERR(priv->clk_ppe))
807 + return PTR_ERR(priv->clk_ppe);
808 + if (of_machine_is_compatible("lantiq,ar9")) {
809 + priv->clk_switch = clk_get(&pdev->dev, "switch");
810 + if (IS_ERR(priv->clk_switch))
811 + return PTR_ERR(priv->clk_switch);
812 + }
813 + if (of_machine_is_compatible("lantiq,ase")) {
814 + priv->clk_ephy = clk_get(&pdev->dev, "ephy");
815 + if (IS_ERR(priv->clk_ephy))
816 + return PTR_ERR(priv->clk_ephy);
817 + priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
818 + if (IS_ERR(priv->clk_ephycgu))
819 + return PTR_ERR(priv->clk_ephycgu);
820 + }
821 +
822 spin_lock_init(&priv->lock);
823 SET_NETDEV_DEV(dev, &pdev->dev);
824
825 - for (i = 0; i < MAX_DMA_CHAN; i++) {
826 - if (IS_TX(i))
827 - netif_napi_add(dev, &priv->ch[i].napi,
828 - ltq_etop_poll_tx, 8);
829 - else if (IS_RX(i))
830 - netif_napi_add(dev, &priv->ch[i].napi,
831 - ltq_etop_poll_rx, 32);
832 - priv->ch[i].netdev = dev;
833 - }
834 + netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
835 + netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
836 + priv->txch.netdev = dev;
837 + priv->rxch.netdev = dev;
838
839 err = register_netdev(dev);
840 if (err)
841 @@ -743,31 +984,22 @@ ltq_etop_remove(struct platform_device *
842 return 0;
843 }
844
845 +static const struct of_device_id ltq_etop_match[] = {
846 + { .compatible = "lantiq,etop-xway" },
847 + {},
848 +};
849 +MODULE_DEVICE_TABLE(of, ltq_etop_match);
850 +
851 static struct platform_driver ltq_mii_driver = {
852 + .probe = ltq_etop_probe,
853 .remove = ltq_etop_remove,
854 .driver = {
855 .name = "ltq_etop",
856 + .of_match_table = ltq_etop_match,
857 },
858 };
859
860 -int __init
861 -init_ltq_etop(void)
862 -{
863 - int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
864 -
865 - if (ret)
866 - pr_err("ltq_etop: Error registering platform driver!");
867 - return ret;
868 -}
869 -
870 -static void __exit
871 -exit_ltq_etop(void)
872 -{
873 - platform_driver_unregister(&ltq_mii_driver);
874 -}
875 -
876 -module_init(init_ltq_etop);
877 -module_exit(exit_ltq_etop);
878 +module_platform_driver(ltq_mii_driver);
879
880 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
881 MODULE_DESCRIPTION("Lantiq SoC ETOP");
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