3aec8568236f3f9e88d8cd73450b9f241fc5a213
[openwrt/staging/dedeckeh.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8064-vr2600v.dts
1 #include "qcom-ipq8064-v2.0.dtsi"
2
3 #include <dt-bindings/input/input.h>
4
5 / {
6 model = "TP-Link Archer VR2600v";
7 compatible = "tplink,vr2600v", "qcom,ipq8064";
8
9 memory@0 {
10 reg = <0x42000000 0x1e000000>;
11 device_type = "memory";
12 };
13
14 aliases {
15 mdio-gpio0 = &mdio0;
16
17 led-boot = &power;
18 led-failsafe = &general;
19 led-running = &power;
20 led-upgrade = &general;
21 };
22
23 keys {
24 compatible = "gpio-keys";
25 pinctrl-0 = <&button_pins>;
26 pinctrl-names = "default";
27
28 wifi {
29 label = "wifi";
30 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
31 linux,code = <KEY_RFKILL>;
32 debounce-interval = <60>;
33 wakeup-source;
34 };
35
36 reset {
37 label = "reset";
38 gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
39 linux,code = <KEY_RESTART>;
40 debounce-interval = <60>;
41 wakeup-source;
42 };
43
44 wps {
45 label = "wps";
46 gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
47 linux,code = <KEY_WPS_BUTTON>;
48 debounce-interval = <60>;
49 wakeup-source;
50 };
51
52 dect {
53 label = "dect";
54 gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
55 linux,code = <KEY_PHONE>;
56 debounce-interval = <60>;
57 wakeup-source;
58 };
59
60 ledswitch {
61 label = "ledswitch";
62 gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
63 linux,code = <KEY_LIGHTS_TOGGLE>;
64 debounce-interval = <60>;
65 wakeup-source;
66 };
67 };
68
69 leds {
70 compatible = "gpio-leds";
71 pinctrl-0 = <&led_pins>;
72 pinctrl-names = "default";
73
74 dsl {
75 label = "white:dsl";
76 gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
77 };
78
79 usb {
80 label = "white:usb";
81 gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
82 };
83
84 lan {
85 label = "white:lan";
86 gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
87 };
88
89 wlan2g {
90 label = "white:wlan2g";
91 gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
92 };
93
94 wlan5g {
95 label = "white:wlan5g";
96 gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>;
97 };
98
99 power: power {
100 label = "white:power";
101 gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
102 default-state = "keep";
103 };
104
105 phone {
106 label = "white:phone";
107 gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
108 };
109
110 wan {
111 label = "white:wan";
112 gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
113 };
114
115 general: general {
116 label = "white:general";
117 gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
118 };
119 };
120 };
121
122 &qcom_pinmux {
123 led_pins: led_pins {
124 mux {
125 pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17",
126 "gpio26", "gpio53", "gpio56", "gpio66";
127 function = "gpio";
128 drive-strength = <2>;
129 bias-pull-up;
130 };
131 };
132
133 button_pins: button_pins {
134 mux {
135 pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68";
136 function = "gpio";
137 drive-strength = <2>;
138 bias-pull-up;
139 };
140 };
141
142 spi_pins: spi_pins {
143 mux {
144 pins = "gpio18", "gpio19", "gpio21";
145 function = "gsbi5";
146 bias-pull-down;
147 };
148
149 data {
150 pins = "gpio18", "gpio19";
151 drive-strength = <10>;
152 };
153
154 cs {
155 pins = "gpio20";
156 drive-strength = <10>;
157 bias-pull-up;
158 };
159
160 clk {
161 pins = "gpio21";
162 drive-strength = <12>;
163 };
164 };
165 };
166
167 &gsbi5 {
168 qcom,mode = <GSBI_PROT_SPI>;
169 status = "okay";
170
171 spi4: spi@1a280000 {
172 status = "okay";
173
174 pinctrl-0 = <&spi_pins>;
175 pinctrl-names = "default";
176
177 cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
178
179 W25Q128@0 {
180 compatible = "jedec,spi-nor";
181 #address-cells = <1>;
182 #size-cells = <1>;
183 spi-max-frequency = <50000000>;
184 reg = <0>;
185
186 SBL1@0 {
187 label = "SBL1";
188 reg = <0x0 0x20000>;
189 read-only;
190 };
191
192 MIBIB@20000 {
193 label = "MIBIB";
194 reg = <0x20000 0x20000>;
195 read-only;
196 };
197
198 SBL2@40000 {
199 label = "SBL2";
200 reg = <0x40000 0x40000>;
201 read-only;
202 };
203
204 SBL3@80000 {
205 label = "SBL3";
206 reg = <0x80000 0x80000>;
207 read-only;
208 };
209
210 DDRCONFIG@100000 {
211 label = "DDRCONFIG";
212 reg = <0x100000 0x10000>;
213 read-only;
214 };
215
216 SSD@110000 {
217 label = "SSD";
218 reg = <0x110000 0x10000>;
219 read-only;
220 };
221
222 TZ@120000 {
223 label = "TZ";
224 reg = <0x120000 0x80000>;
225 read-only;
226 };
227
228 RPM@1a0000 {
229 label = "RPM";
230 reg = <0x1a0000 0x80000>;
231 read-only;
232 };
233
234 APPSBL@220000 {
235 label = "APPSBL";
236 reg = <0x220000 0x80000>;
237 read-only;
238 };
239
240 APPSBLENV@2a0000 {
241 label = "APPSBLENV";
242 reg = <0x2a0000 0x40000>;
243 read-only;
244 };
245
246 OLDART@2e0000 {
247 label = "OLDART";
248 reg = <0x2e0000 0x40000>;
249 read-only;
250 };
251
252 kernel@320000 {
253 label = "kernel";
254 reg = <0x320000 0x300000>;
255 };
256
257 rootfs@620000 {
258 label = "rootfs";
259 reg = <0x620000 0x960000>;
260 };
261
262 defaultmac: default-mac@0xfaf100 {
263 label = "default-mac";
264 reg = <0xfaf100 0x00200>;
265 read-only;
266 };
267
268 ART@fc0000 {
269 label = "ART";
270 reg = <0xfc0000 0x40000>;
271 read-only;
272
273 compatible = "nvmem-cells";
274 #address-cells = <1>;
275 #size-cells = <1>;
276
277 precal_ART_1000: precal@1000 {
278 reg = <0x1000 0x2f20>;
279 };
280
281 precal_ART_5000: precal@5000 {
282 reg = <0x5000 0x2f20>;
283 };
284 };
285 };
286 };
287 };
288
289 &usb3_0 {
290 status = "okay";
291 };
292
293 &usb3_1 {
294 status = "okay";
295 };
296
297 &pcie0 {
298 status = "okay";
299
300 bridge@0,0 {
301 reg = <0x00000000 0 0 0 0>;
302 #address-cells = <3>;
303 #size-cells = <2>;
304 ranges;
305
306 wifi@1,0 {
307 compatible = "pci168c,0040";
308 reg = <0x00010000 0 0 0 0>;
309
310 nvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_1000>;
311 nvmem-cell-names = "mac-address", "pre-calibration";
312 mac-address-increment = <(-1)>;
313 };
314 };
315 };
316
317 &pcie1 {
318 status = "okay";
319 max-link-speed = <1>;
320
321 bridge@0,0 {
322 reg = <0x00000000 0 0 0 0>;
323 #address-cells = <3>;
324 #size-cells = <2>;
325 ranges;
326
327 wifi@1,0 {
328 compatible = "pci168c,0040";
329 reg = <0x00010000 0 0 0 0>;
330
331 nvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_5000>;
332 nvmem-cell-names = "mac-address", "pre-calibration";
333 };
334 };
335 };
336
337 &mdio0 {
338 status = "okay";
339
340 pinctrl-0 = <&mdio0_pins>;
341 pinctrl-names = "default";
342
343 phy0: ethernet-phy@0 {
344 reg = <0>;
345 qca,ar8327-initvals = <
346 0x00004 0x7600000 /* PAD0_MODE */
347 0x00008 0x1000000 /* PAD5_MODE */
348 0x0000c 0x80 /* PAD6_MODE */
349 0x000e4 0x6a545 /* MAC_POWER_SEL */
350 0x000e0 0xc74164de /* SGMII_CTRL */
351 0x0007c 0x4e /* PORT0_STATUS */
352 0x00094 0x4e /* PORT6_STATUS */
353 >;
354 };
355
356 phy4: ethernet-phy@4 {
357 reg = <4>;
358 };
359 };
360
361 &gmac1 {
362 status = "okay";
363 phy-mode = "rgmii";
364 qcom,id = <1>;
365
366 pinctrl-0 = <&rgmii2_pins>;
367 pinctrl-names = "default";
368
369 nvmem-cells = <&macaddr_defaultmac_0>;
370 nvmem-cell-names = "mac-address";
371 mac-address-increment = <1>;
372
373 fixed-link {
374 speed = <1000>;
375 full-duplex;
376 };
377 };
378
379 &gmac2 {
380 status = "okay";
381 phy-mode = "sgmii";
382 qcom,id = <2>;
383
384 nvmem-cells = <&macaddr_defaultmac_0>;
385 nvmem-cell-names = "mac-address";
386
387 fixed-link {
388 speed = <1000>;
389 full-duplex;
390 };
391 };
392
393 &adm_dma {
394 status = "okay";
395 };
396
397 &defaultmac {
398 compatible = "nvmem-cells";
399 #address-cells = <1>;
400 #size-cells = <1>;
401
402 macaddr_defaultmac_0: macaddr@0 {
403 reg = <0x0 0x6>;
404 };
405 };