target/linux/generic/pending-5.15/733-01-net-ethernet-mtk_eth_soc-reset-PCS-state.patch

   1 From b66105968b8c37c26a75b9da9281cbc1c8f73594 Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Sun, 22 Jan 2023 23:58:36 +0000
   4 Subject: [PATCH] net: ethernet: mtk_eth_soc: reset PCS state
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Reset PCS state when changing interface mode.
  10
  11 Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  12 Tested-by: Bjørn Mork <bjorn@mork.no>
  13 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  14 ---
  15  drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++++
  16  drivers/net/ethernet/mediatek/mtk_sgmii.c   | 4 ++++
  17  2 files changed, 8 insertions(+)
  18
  19 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  20 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  21 @@ -530,6 +530,10 @@
  22  #define SGMII_SEND_AN_ERROR_EN         BIT(11)
  23  #define SGMII_IF_MODE_MASK             GENMASK(5, 1)
  24
  25 +/* Register to reset SGMII design */
  26 +#define SGMII_RESERVED_0       0x34
  27 +#define SGMII_SW_RESET         BIT(0)
  28 +
  29  /* Register to set SGMII speed, ANA RG_ Control Signals III*/
  30  #define SGMSYS_ANA_RG_CS3      0x2028
  31  #define RG_PHY_SPEED_MASK      (BIT(2) | BIT(3))
  32 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
  33 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
  34 @@ -90,6 +90,10 @@ static int mtk_pcs_config(struct phylink
  35                 regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
  36                                    SGMII_PHYA_PWD, SGMII_PHYA_PWD);
  37
  38 +               /* Reset SGMII PCS state */
  39 +               regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
  40 +                                  SGMII_SW_RESET, SGMII_SW_RESET);
  41 +
  42                 mpcs->interface = interface;
  43         }
  44