target/linux/generic/pending-5.15/724-net-mtk_sgmii-implement-mtk_pcs_ops.patch

   1 From cbfed00575d15eafd85efd9619b7ecc0836a4aa7 Mon Sep 17 00:00:00 2001
   2 From: Alexander Couzens <lynxis@fe80.eu>
   3 Date: Sat, 13 Aug 2022 14:42:12 +0200
   4 Subject: [PATCH 04/10] net: mtk_sgmii: implement mtk_pcs_ops
   5
   6 Implement mtk_pcs_ops for the SGMII pcs to read the current state
   7 of the hardware.
   8
   9 Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
  10 [added DUPLEX_FULL]
  11 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  12 ---
  13  drivers/net/ethernet/mediatek/mtk_sgmii.c | 15 +++++++++++++++
  14  1 file changed, 15 insertions(+)
  15
  16 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
  17 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
  18 @@ -143,10 +143,28 @@ static void mtk_pcs_link_up(struct phyli
  19         regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
  20  }
  21
  22 +static void mtk_pcs_get_state(struct phylink_pcs *pcs, struct phylink_link_state *state)
  23 +{
  24 +       struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
  25 +       unsigned int val;
  26 +
  27 +       regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
  28 +       state->an_complete = !!(val & SGMII_AN_COMPLETE);
  29 +       state->link = !!(val & SGMII_LINK_STATYS);
  30 +       if (!state->link)
  31 +               return;
  32 +
  33 +       regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
  34 +       state->speed = val & RG_PHY_SPEED_3_125G ? SPEED_2500 : SPEED_1000;
  35 +       state->duplex = DUPLEX_FULL;
  36 +       state->pause = 0;
  37 +}
  38 +
  39  static const struct phylink_pcs_ops mtk_pcs_ops = {
  40         .pcs_config = mtk_pcs_config,
  41         .pcs_an_restart = mtk_pcs_restart_an,
  42         .pcs_link_up = mtk_pcs_link_up,
  43 +       .pcs_get_state = mtk_pcs_get_state,
  44  };
  45
  46  int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)