target/linux/generic/backport-5.15/806-v6.0-0001-nvmem-microchip-otpc-add-support.patch

   1 From 98830350d3fc824c1ff5c338140fe20f041a5916 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Wed, 6 Jul 2022 11:06:22 +0100
   4 Subject: [PATCH] nvmem: microchip-otpc: add support
   5
   6 Add support for Microchip OTP controller available on SAMA7G5. The OTPC
   7 controls the access to a non-volatile memory. The memory behind OTPC is
   8 organized into packets, packets are composed by a fixed length header
   9 (4 bytes long) and a variable length payload (payload length is available
  10 in the header). When software request the data at an offset in memory
  11 the OTPC will return (via header + data registers) the whole packet that
  12 has a word at that offset. For the OTP memory layout like below:
  13
  14 offset  OTP Memory layout
  15
  16          .           .
  17          .    ...    .
  18          .           .
  19 0x0E     +-----------+  <--- packet X
  20          | header  X |
  21 0x12     +-----------+
  22          | payload X |
  23 0x16     |           |
  24          |           |
  25 0x1A     |           |
  26          +-----------+
  27          .           .
  28          .    ...    .
  29          .           .
  30
  31 if user requests data at address 0x16 the data started at 0x0E will be
  32 returned by controller. User will be able to fetch the whole packet
  33 starting at 0x0E (or parts of the packet) via proper registers. The same
  34 packet will be returned if software request the data at offset 0x0E or
  35 0x12 or 0x1A.
  36
  37 The OTP will be populated by Microchip with at least 2 packets first one
  38 being boot configuration packet and the 2nd one being temperature
  39 calibration packet. The packet order will be preserved b/w different chip
  40 revisions but the packet sizes may change.
  41
  42 For the above reasons and to keep the same software able to work on all
  43 chip variants the read function of the driver is working with a packet
  44 id instead of an offset in OTP memory.
  45
  46 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  47 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
  48 Link: https://lore.kernel.org/r/20220706100627.6534-3-srinivas.kandagatla@linaro.org
  49 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  50 ---
  51  MAINTAINERS                    |   8 +
  52  drivers/nvmem/Kconfig          |   7 +
  53  drivers/nvmem/Makefile         |   2 +
  54  drivers/nvmem/microchip-otpc.c | 288 +++++++++++++++++++++++++++++++++
  55  4 files changed, 305 insertions(+)
  56  create mode 100644 drivers/nvmem/microchip-otpc.c
  57
  58 --- a/MAINTAINERS
  59 +++ b/MAINTAINERS
  60 @@ -12362,6 +12362,14 @@ S:     Supported
  61  F:     Documentation/devicetree/bindings/mtd/atmel-nand.txt
  62  F:     drivers/mtd/nand/raw/atmel/*
  63
  64 +MICROCHIP OTPC DRIVER
  65 +M:     Claudiu Beznea <claudiu.beznea@microchip.com>
  66 +L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  67 +S:     Supported
  68 +F:     Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml
  69 +F:     drivers/nvmem/microchip-otpc.c
  70 +F:     dt-bindings/nvmem/microchip,sama7g5-otpc.h
  71 +
  72  MICROCHIP PWM DRIVER
  73  M:     Claudiu Beznea <claudiu.beznea@microchip.com>
  74  L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
  75 --- a/drivers/nvmem/Kconfig
  76 +++ b/drivers/nvmem/Kconfig
  77 @@ -107,6 +107,13 @@ config MTK_EFUSE
  78           This driver can also be built as a module. If so, the module
  79           will be called efuse-mtk.
  80
  81 +config MICROCHIP_OTPC
  82 +       tristate "Microchip OTPC support"
  83 +       depends on ARCH_AT91 || COMPILE_TEST
  84 +       help
  85 +         This driver enable the OTP controller available on Microchip SAMA7G5
  86 +         SoCs. It controlls the access to the OTP memory connected to it.
  87 +
  88  config NVMEM_NINTENDO_OTP
  89         tristate "Nintendo Wii and Wii U OTP Support"
  90         depends on WII || COMPILE_TEST
  91 --- a/drivers/nvmem/Makefile
  92 +++ b/drivers/nvmem/Makefile
  93 @@ -67,3 +67,5 @@ obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP)     += nvm
  94  nvmem_sunplus_ocotp-y          := sunplus-ocotp.o
  95  obj-$(CONFIG_NVMEM_APPLE_EFUSES)       += nvmem-apple-efuses.o
  96  nvmem-apple-efuses-y           := apple-efuses.o
  97 +obj-$(CONFIG_MICROCHIP_OTPC)   += nvmem-microchip-otpc.o
  98 +nvmem-microchip-otpc-y         := microchip-otpc.o
  99 --- /dev/null
 100 +++ b/drivers/nvmem/microchip-otpc.c
 101 @@ -0,0 +1,288 @@
 102 +// SPDX-License-Identifier: GPL-2.0
 103 +/*
 104 + * OTP Memory controller
 105 + *
 106 + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
 107 + *
 108 + * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
 109 + */
 110 +
 111 +#include <linux/bitfield.h>
 112 +#include <linux/iopoll.h>
 113 +#include <linux/module.h>
 114 +#include <linux/nvmem-provider.h>
 115 +#include <linux/of.h>
 116 +#include <linux/platform_device.h>
 117 +
 118 +#define MCHP_OTPC_CR                   (0x0)
 119 +#define MCHP_OTPC_CR_READ              BIT(6)
 120 +#define MCHP_OTPC_MR                   (0x4)
 121 +#define MCHP_OTPC_MR_ADDR              GENMASK(31, 16)
 122 +#define MCHP_OTPC_AR                   (0x8)
 123 +#define MCHP_OTPC_SR                   (0xc)
 124 +#define MCHP_OTPC_SR_READ              BIT(6)
 125 +#define MCHP_OTPC_HR                   (0x20)
 126 +#define MCHP_OTPC_HR_SIZE              GENMASK(15, 8)
 127 +#define MCHP_OTPC_DR                   (0x24)
 128 +
 129 +#define MCHP_OTPC_NAME                 "mchp-otpc"
 130 +#define MCHP_OTPC_SIZE                 (11 * 1024)
 131 +
 132 +/**
 133 + * struct mchp_otpc - OTPC private data structure
 134 + * @base: base address
 135 + * @dev: struct device pointer
 136 + * @packets: list of packets in OTP memory
 137 + * @npackets: number of packets in OTP memory
 138 + */
 139 +struct mchp_otpc {
 140 +       void __iomem *base;
 141 +       struct device *dev;
 142 +       struct list_head packets;
 143 +       u32 npackets;
 144 +};
 145 +
 146 +/**
 147 + * struct mchp_otpc_packet - OTPC packet data structure
 148 + * @list: list head
 149 + * @id: packet ID
 150 + * @offset: packet offset (in words) in OTP memory
 151 + */
 152 +struct mchp_otpc_packet {
 153 +       struct list_head list;
 154 +       u32 id;
 155 +       u32 offset;
 156 +};
 157 +
 158 +static struct mchp_otpc_packet *mchp_otpc_id_to_packet(struct mchp_otpc *otpc,
 159 +                                                      u32 id)
 160 +{
 161 +       struct mchp_otpc_packet *packet;
 162 +
 163 +       if (id >= otpc->npackets)
 164 +               return NULL;
 165 +
 166 +       list_for_each_entry(packet, &otpc->packets, list) {
 167 +               if (packet->id == id)
 168 +                       return packet;
 169 +       }
 170 +
 171 +       return NULL;
 172 +}
 173 +
 174 +static int mchp_otpc_prepare_read(struct mchp_otpc *otpc,
 175 +                                 unsigned int offset)
 176 +{
 177 +       u32 tmp;
 178 +
 179 +       /* Set address. */
 180 +       tmp = readl_relaxed(otpc->base + MCHP_OTPC_MR);
 181 +       tmp &= ~MCHP_OTPC_MR_ADDR;
 182 +       tmp |= FIELD_PREP(MCHP_OTPC_MR_ADDR, offset);
 183 +       writel_relaxed(tmp, otpc->base + MCHP_OTPC_MR);
 184 +
 185 +       /* Set read. */
 186 +       tmp = readl_relaxed(otpc->base + MCHP_OTPC_CR);
 187 +       tmp |= MCHP_OTPC_CR_READ;
 188 +       writel_relaxed(tmp, otpc->base + MCHP_OTPC_CR);
 189 +
 190 +       /* Wait for packet to be transferred into temporary buffers. */
 191 +       return read_poll_timeout(readl_relaxed, tmp, !(tmp & MCHP_OTPC_SR_READ),
 192 +                                10000, 2000, false, otpc->base + MCHP_OTPC_SR);
 193 +}
 194 +
 195 +/*
 196 + * OTPC memory is organized into packets. Each packets contains a header and
 197 + * a payload. Header is 4 bytes long and contains the size of the payload.
 198 + * Payload size varies. The memory footprint is something as follows:
 199 + *
 200 + * Memory offset  Memory footprint     Packet ID
 201 + * -------------  ----------------     ---------
 202 + *
 203 + * 0x0            +------------+   <-- packet 0
 204 + *                | header  0  |
 205 + * 0x4            +------------+
 206 + *                | payload 0  |
 207 + *                .            .
 208 + *                .    ...     .
 209 + *                .            .
 210 + * offset1        +------------+   <-- packet 1
 211 + *                | header  1  |
 212 + * offset1 + 0x4  +------------+
 213 + *                | payload 1  |
 214 + *                .            .
 215 + *                .    ...     .
 216 + *                .            .
 217 + * offset2        +------------+   <-- packet 2
 218 + *                .            .
 219 + *                .    ...     .
 220 + *                .            .
 221 + * offsetN        +------------+   <-- packet N
 222 + *                | header  N  |
 223 + * offsetN + 0x4  +------------+
 224 + *                | payload N  |
 225 + *                .            .
 226 + *                .    ...     .
 227 + *                .            .
 228 + *                +------------+
 229 + *
 230 + * where offset1, offset2, offsetN depends on the size of payload 0, payload 1,
 231 + * payload N-1.
 232 + *
 233 + * The access to memory is done on a per packet basis: the control registers
 234 + * need to be updated with an offset address (within a packet range) and the
 235 + * data registers will be update by controller with information contained by
 236 + * that packet. E.g. if control registers are updated with any address within
 237 + * the range [offset1, offset2) the data registers are updated by controller
 238 + * with packet 1. Header data is accessible though MCHP_OTPC_HR register.
 239 + * Payload data is accessible though MCHP_OTPC_DR and MCHP_OTPC_AR registers.
 240 + * There is no direct mapping b/w the offset requested by software and the
 241 + * offset returned by hardware.
 242 + *
 243 + * For this, the read function will return the first requested bytes in the
 244 + * packet. The user will have to be aware of the memory footprint before doing
 245 + * the read request.
 246 + */
 247 +static int mchp_otpc_read(void *priv, unsigned int off, void *val,
 248 +                         size_t bytes)
 249 +{
 250 +       struct mchp_otpc *otpc = priv;
 251 +       struct mchp_otpc_packet *packet;
 252 +       u32 *buf = val;
 253 +       u32 offset;
 254 +       size_t len = 0;
 255 +       int ret, payload_size;
 256 +
 257 +       /*
 258 +        * We reach this point with off being multiple of stride = 4 to
 259 +        * be able to cross the subsystem. Inside the driver we use continuous
 260 +        * unsigned integer numbers for packet id, thus devide off by 4
 261 +        * before passing it to mchp_otpc_id_to_packet().
 262 +        */
 263 +       packet = mchp_otpc_id_to_packet(otpc, off / 4);
 264 +       if (!packet)
 265 +               return -EINVAL;
 266 +       offset = packet->offset;
 267 +
 268 +       while (len < bytes) {
 269 +               ret = mchp_otpc_prepare_read(otpc, offset);
 270 +               if (ret)
 271 +                       return ret;
 272 +
 273 +               /* Read and save header content. */
 274 +               *buf++ = readl_relaxed(otpc->base + MCHP_OTPC_HR);
 275 +               len += sizeof(*buf);
 276 +               offset++;
 277 +               if (len >= bytes)
 278 +                       break;
 279 +
 280 +               /* Read and save payload content. */
 281 +               payload_size = FIELD_GET(MCHP_OTPC_HR_SIZE, *(buf - 1));
 282 +               writel_relaxed(0UL, otpc->base + MCHP_OTPC_AR);
 283 +               do {
 284 +                       *buf++ = readl_relaxed(otpc->base + MCHP_OTPC_DR);
 285 +                       len += sizeof(*buf);
 286 +                       offset++;
 287 +                       payload_size--;
 288 +               } while (payload_size >= 0 && len < bytes);
 289 +       }
 290 +
 291 +       return 0;
 292 +}
 293 +
 294 +static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size)
 295 +{
 296 +       struct mchp_otpc_packet *packet;
 297 +       u32 word, word_pos = 0, id = 0, npackets = 0, payload_size;
 298 +       int ret;
 299 +
 300 +       INIT_LIST_HEAD(&otpc->packets);
 301 +       *size = 0;
 302 +
 303 +       while (*size < MCHP_OTPC_SIZE) {
 304 +               ret = mchp_otpc_prepare_read(otpc, word_pos);
 305 +               if (ret)
 306 +                       return ret;
 307 +
 308 +               word = readl_relaxed(otpc->base + MCHP_OTPC_HR);
 309 +               payload_size = FIELD_GET(MCHP_OTPC_HR_SIZE, word);
 310 +               if (!payload_size)
 311 +                       break;
 312 +
 313 +               packet = devm_kzalloc(otpc->dev, sizeof(*packet), GFP_KERNEL);
 314 +               if (!packet)
 315 +                       return -ENOMEM;
 316 +
 317 +               packet->id = id++;
 318 +               packet->offset = word_pos;
 319 +               INIT_LIST_HEAD(&packet->list);
 320 +               list_add_tail(&packet->list, &otpc->packets);
 321 +
 322 +               /* Count size by adding header and paload sizes. */
 323 +               *size += 4 * (payload_size + 1);
 324 +               /* Next word: this packet (header, payload) position + 1. */
 325 +               word_pos += payload_size + 2;
 326 +
 327 +               npackets++;
 328 +       }
 329 +
 330 +       otpc->npackets = npackets;
 331 +
 332 +       return 0;
 333 +}
 334 +
 335 +static struct nvmem_config mchp_nvmem_config = {
 336 +       .name = MCHP_OTPC_NAME,
 337 +       .type = NVMEM_TYPE_OTP,
 338 +       .read_only = true,
 339 +       .word_size = 4,
 340 +       .stride = 4,
 341 +       .reg_read = mchp_otpc_read,
 342 +};
 343 +
 344 +static int mchp_otpc_probe(struct platform_device *pdev)
 345 +{
 346 +       struct nvmem_device *nvmem;
 347 +       struct mchp_otpc *otpc;
 348 +       u32 size;
 349 +       int ret;
 350 +
 351 +       otpc = devm_kzalloc(&pdev->dev, sizeof(*otpc), GFP_KERNEL);
 352 +       if (!otpc)
 353 +               return -ENOMEM;
 354 +
 355 +       otpc->base = devm_platform_ioremap_resource(pdev, 0);
 356 +       if (IS_ERR(otpc->base))
 357 +               return PTR_ERR(otpc->base);
 358 +
 359 +       otpc->dev = &pdev->dev;
 360 +       ret = mchp_otpc_init_packets_list(otpc, &size);
 361 +       if (ret)
 362 +               return ret;
 363 +
 364 +       mchp_nvmem_config.dev = otpc->dev;
 365 +       mchp_nvmem_config.size = size;
 366 +       mchp_nvmem_config.priv = otpc;
 367 +       nvmem = devm_nvmem_register(&pdev->dev, &mchp_nvmem_config);
 368 +
 369 +       return PTR_ERR_OR_ZERO(nvmem);
 370 +}
 371 +
 372 +static const struct of_device_id __maybe_unused mchp_otpc_ids[] = {
 373 +       { .compatible = "microchip,sama7g5-otpc", },
 374 +       { },
 375 +};
 376 +MODULE_DEVICE_TABLE(of, mchp_otpc_ids);
 377 +
 378 +static struct platform_driver mchp_otpc_driver = {
 379 +       .probe = mchp_otpc_probe,
 380 +       .driver = {
 381 +               .name = MCHP_OTPC_NAME,
 382 +               .of_match_table = of_match_ptr(mchp_otpc_ids),
 383 +       },
 384 +};
 385 +module_platform_driver(mchp_otpc_driver);
 386 +
 387 +MODULE_AUTHOR("Claudiu Beznea <claudiu.beznea@microchip.com>");
 388 +MODULE_DESCRIPTION("Microchip SAMA7G5 OTPC driver");
 389 +MODULE_LICENSE("GPL");