target/linux/bmips/patches-5.15/100-irqchip-add-support-for-bcm6345-style-external-inter.patch

   1 From cf908990d4a8ccdb73ee4484aa8cadad379ca314 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Sun, 30 Nov 2014 14:54:27 +0100
   4 Subject: [PATCH 2/5] irqchip: add support for bcm6345-style external
   5  interrupt controller
   6
   7 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
   8 ---
   9  .../interrupt-controller/brcm,bcm6345-ext-intc.txt |   29 ++
  10  drivers/irqchip/Kconfig                            |    4 +
  11  drivers/irqchip/Makefile                           |    1 +
  12  drivers/irqchip/irq-bcm6345-ext.c                  |  287 ++++++++++++++++++++
  13  include/linux/irqchip/irq-bcm6345-ext.h            |   14 +
  14  5 files changed, 335 insertions(+)
  15  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
  16  create mode 100644 drivers/irqchip/irq-bcm6345-ext.c
  17  create mode 100644 include/linux/irqchip/irq-bcm6345-ext.h
  18
  19 --- /dev/null
  20 +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
  21 @@ -0,0 +1,29 @@
  22 +Broadcom BCM6345-style external interrupt controller
  23 +
  24 +Required properties:
  25 +
  26 +- compatible: Should be "brcm,bcm6345-ext-intc" or "brcm,bcm6318-ext-intc".
  27 +- reg: Specifies the base physical addresses and size of the registers.
  28 +- interrupt-controller: identifies the node as an interrupt controller.
  29 +- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
  30 +  source, Should be 2.
  31 +- interrupt-parent: Specifies the phandle to the parent interrupt controller
  32 +  this one is cascaded from.
  33 +- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller
  34 +  node, valid values depend on the type of parent interrupt controller.
  35 +
  36 +Optional properties:
  37 +
  38 +- brcm,field-width: Size of each field (mask, clear, sense, ...) in bits in the
  39 +  register. Defaults to 4.
  40 +
  41 +Example:
  42 +
  43 +ext_intc: interrupt-controller@10000018 {
  44 +       compatible = "brcm,bcm6345-ext-intc";
  45 +       interrupt-parent = <&periph_intc>;
  46 +       #interrupt-cells = <2>;
  47 +       reg = <0x10000018 0x4>;
  48 +       interrupt-controller;
  49 +       interrupts = <24>, <25>, <26>, <27>;
  50 +};
  51 --- a/drivers/irqchip/Kconfig
  52 +++ b/drivers/irqchip/Kconfig
  53 @@ -108,6 +108,10 @@ config I8259
  54         bool
  55         select IRQ_DOMAIN
  56
  57 +config BCM6345_EXT_IRQ
  58 +       bool "BCM6345 External IRQ Controller"
  59 +       select IRQ_DOMAIN
  60 +
  61  config BCM6345_L1_IRQ
  62         bool
  63         select GENERIC_IRQ_CHIP
  64 --- a/drivers/irqchip/Makefile
  65 +++ b/drivers/irqchip/Makefile
  66 @@ -62,6 +62,7 @@ obj-$(CONFIG_XTENSA_MX)                       += irq-xtensa-
  67  obj-$(CONFIG_XILINX_INTC)              += irq-xilinx-intc.o
  68  obj-$(CONFIG_IRQ_CROSSBAR)             += irq-crossbar.o
  69  obj-$(CONFIG_SOC_VF610)                        += irq-vf610-mscm-ir.o
  70 +obj-$(CONFIG_BCM6345_EXT_IRQ)          += irq-bcm6345-ext.o
  71  obj-$(CONFIG_BCM6345_L1_IRQ)           += irq-bcm6345-l1.o
  72  obj-$(CONFIG_BCM7038_L1_IRQ)           += irq-bcm7038-l1.o
  73  obj-$(CONFIG_BCM7120_L2_IRQ)           += irq-bcm7120-l2.o
  74 --- /dev/null
  75 +++ b/drivers/irqchip/irq-bcm6345-ext.c
  76 @@ -0,0 +1,280 @@
  77 +/*
  78 + * This file is subject to the terms and conditions of the GNU General Public
  79 + * License.  See the file "COPYING" in the main directory of this archive
  80 + * for more details.
  81 + *
  82 + * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
  83 + */
  84 +
  85 +#include <linux/ioport.h>
  86 +#include <linux/irq.h>
  87 +#include <linux/irqchip.h>
  88 +#include <linux/irqchip/chained_irq.h>
  89 +#include <linux/irqchip/irq-bcm6345-ext.h>
  90 +#include <linux/kernel.h>
  91 +#include <linux/of.h>
  92 +#include <linux/of_irq.h>
  93 +#include <linux/of_address.h>
  94 +#include <linux/slab.h>
  95 +#include <linux/spinlock.h>
  96 +
  97 +#define MAX_IRQS               4
  98 +
  99 +#define EXTIRQ_CFG_SENSE       0
 100 +#define EXTIRQ_CFG_STAT                1
 101 +#define EXTIRQ_CFG_CLEAR       2
 102 +#define EXTIRQ_CFG_MASK                3
 103 +#define EXTIRQ_CFG_BOTHEDGE    4
 104 +#define EXTIRQ_CFG_LEVELSENSE  5
 105 +
 106 +struct intc_data {
 107 +       struct irq_chip chip;
 108 +       struct irq_domain *domain;
 109 +       raw_spinlock_t lock;
 110 +
 111 +       int parent_irq[MAX_IRQS];
 112 +       void __iomem *reg;
 113 +       int shift;
 114 +       unsigned int toggle_clear_on_ack:1;
 115 +};
 116 +
 117 +static void bcm6345_ext_intc_irq_handle(struct irq_desc *desc)
 118 +{
 119 +       struct intc_data *data = irq_desc_get_handler_data(desc);
 120 +       struct irq_chip *chip = irq_desc_get_chip(desc);
 121 +       unsigned int irq = irq_desc_get_irq(desc);
 122 +       unsigned int idx;
 123 +
 124 +       chained_irq_enter(chip, desc);
 125 +
 126 +       for (idx = 0; idx < MAX_IRQS; idx++) {
 127 +               if (data->parent_irq[idx] != irq)
 128 +                       continue;
 129 +
 130 +               generic_handle_irq(irq_find_mapping(data->domain, idx));
 131 +       }
 132 +
 133 +       chained_irq_exit(chip, desc);
 134 +}
 135 +
 136 +static void bcm6345_ext_intc_irq_ack(struct irq_data *data)
 137 +{
 138 +       struct intc_data *priv = data->domain->host_data;
 139 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 140 +       u32 reg;
 141 +
 142 +       raw_spin_lock(&priv->lock);
 143 +       reg = __raw_readl(priv->reg);
 144 +       __raw_writel(reg | (1 << (hwirq + EXTIRQ_CFG_CLEAR * priv->shift)),
 145 +                    priv->reg);
 146 +       if (priv->toggle_clear_on_ack)
 147 +               __raw_writel(reg, priv->reg);
 148 +       raw_spin_unlock(&priv->lock);
 149 +}
 150 +
 151 +static void bcm6345_ext_intc_irq_mask(struct irq_data *data)
 152 +{
 153 +       struct intc_data *priv = data->domain->host_data;
 154 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 155 +       u32 reg;
 156 +
 157 +       raw_spin_lock(&priv->lock);
 158 +       reg = __raw_readl(priv->reg);
 159 +       reg &= ~(1 << (hwirq + EXTIRQ_CFG_MASK * priv->shift));
 160 +       __raw_writel(reg, priv->reg);
 161 +       raw_spin_unlock(&priv->lock);
 162 +}
 163 +
 164 +static void bcm6345_ext_intc_irq_unmask(struct irq_data *data)
 165 +{
 166 +       struct intc_data *priv = data->domain->host_data;
 167 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 168 +       u32 reg;
 169 +
 170 +       raw_spin_lock(&priv->lock);
 171 +       reg = __raw_readl(priv->reg);
 172 +       reg |= 1 << (hwirq + EXTIRQ_CFG_MASK * priv->shift);
 173 +       __raw_writel(reg, priv->reg);
 174 +       raw_spin_unlock(&priv->lock);
 175 +}
 176 +
 177 +static int bcm6345_ext_intc_set_type(struct irq_data *data,
 178 +                                    unsigned int flow_type)
 179 +{
 180 +       struct intc_data *priv = data->domain->host_data;
 181 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 182 +       bool levelsense = 0, sense = 0, bothedge = 0;
 183 +       u32 reg;
 184 +
 185 +       flow_type &= IRQ_TYPE_SENSE_MASK;
 186 +
 187 +       if (flow_type == IRQ_TYPE_NONE)
 188 +               flow_type = IRQ_TYPE_LEVEL_LOW;
 189 +
 190 +       switch (flow_type) {
 191 +       case IRQ_TYPE_EDGE_BOTH:
 192 +               bothedge = 1;
 193 +               break;
 194 +
 195 +       case IRQ_TYPE_EDGE_RISING:
 196 +               sense = 1;
 197 +               break;
 198 +
 199 +       case IRQ_TYPE_EDGE_FALLING:
 200 +               break;
 201 +
 202 +       case IRQ_TYPE_LEVEL_HIGH:
 203 +               levelsense = 1;
 204 +               sense = 1;
 205 +               break;
 206 +
 207 +       case IRQ_TYPE_LEVEL_LOW:
 208 +               levelsense = 1;
 209 +               break;
 210 +
 211 +       default:
 212 +               pr_err("bogus flow type combination given!\n");
 213 +               return -EINVAL;
 214 +       }
 215 +
 216 +       raw_spin_lock(&priv->lock);
 217 +       reg = __raw_readl(priv->reg);
 218 +
 219 +       if (levelsense)
 220 +               reg |= 1 << (hwirq + EXTIRQ_CFG_LEVELSENSE * priv->shift);
 221 +       else
 222 +               reg &= ~(1 << (hwirq + EXTIRQ_CFG_LEVELSENSE * priv->shift));
 223 +       if (sense)
 224 +               reg |= 1 << (hwirq + EXTIRQ_CFG_SENSE * priv->shift);
 225 +       else
 226 +               reg &= ~(1 << (hwirq + EXTIRQ_CFG_SENSE * priv->shift));
 227 +       if (bothedge)
 228 +               reg |= 1 << (hwirq + EXTIRQ_CFG_BOTHEDGE * priv->shift);
 229 +       else
 230 +               reg &= ~(1 << (hwirq + EXTIRQ_CFG_BOTHEDGE * priv->shift));
 231 +
 232 +       __raw_writel(reg, priv->reg);
 233 +       raw_spin_unlock(&priv->lock);
 234 +
 235 +       irqd_set_trigger_type(data, flow_type);
 236 +       if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 237 +               irq_set_handler_locked(data, handle_level_irq);
 238 +       else
 239 +               irq_set_handler_locked(data, handle_edge_irq);
 240 +
 241 +       return 0;
 242 +}
 243 +
 244 +static int bcm6345_ext_intc_map(struct irq_domain *d, unsigned int irq,
 245 +                               irq_hw_number_t hw)
 246 +{
 247 +       struct intc_data *priv = d->host_data;
 248 +
 249 +       irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
 250 +
 251 +       return 0;
 252 +}
 253 +
 254 +static const struct irq_domain_ops bcm6345_ext_domain_ops = {
 255 +       .xlate = irq_domain_xlate_twocell,
 256 +       .map = bcm6345_ext_intc_map,
 257 +};
 258 +
 259 +static int __init __bcm6345_ext_intc_init(struct device_node *node,
 260 +                                         int num_irqs, int *irqs,
 261 +                                         void __iomem *reg, int shift,
 262 +                                         bool toggle_clear_on_ack)
 263 +{
 264 +       struct intc_data *data;
 265 +       unsigned int i;
 266 +
 267 +       data = kzalloc(sizeof(*data), GFP_KERNEL);
 268 +       if (!data)
 269 +               return -ENOMEM;
 270 +
 271 +       raw_spin_lock_init(&data->lock);
 272 +
 273 +       for (i = 0; i < num_irqs; i++) {
 274 +               data->parent_irq[i] = irqs[i];
 275 +
 276 +               irq_set_handler_data(irqs[i], data);
 277 +               irq_set_chained_handler(irqs[i], bcm6345_ext_intc_irq_handle);
 278 +       }
 279 +
 280 +       data->reg = reg;
 281 +       data->shift = shift;
 282 +       data->toggle_clear_on_ack = toggle_clear_on_ack;
 283 +
 284 +       data->chip.name = "bcm6345-ext-intc";
 285 +       data->chip.irq_ack = bcm6345_ext_intc_irq_ack;
 286 +       data->chip.irq_mask = bcm6345_ext_intc_irq_mask;
 287 +       data->chip.irq_unmask = bcm6345_ext_intc_irq_unmask;
 288 +       data->chip.irq_set_type = bcm6345_ext_intc_set_type;
 289 +
 290 +       data->domain = irq_domain_add_linear(node, num_irqs,
 291 +                                            &bcm6345_ext_domain_ops, data);
 292 +       if (!data->domain) {
 293 +               kfree(data);
 294 +               return -ENOMEM;
 295 +       }
 296 +
 297 +       return 0;
 298 +}
 299 +
 300 +void __init bcm6345_ext_intc_init(int num_irqs, int *irqs, void __iomem *reg,
 301 +                                 int shift)
 302 +{
 303 +       __bcm6345_ext_intc_init(NULL, num_irqs, irqs, reg, shift, false);
 304 +}
 305 +
 306 +#ifdef CONFIG_OF
 307 +static int __init bcm6345_ext_intc_of_init(struct device_node *node,
 308 +                                          struct device_node *parent)
 309 +{
 310 +       int num_irqs, ret = -EINVAL;
 311 +       unsigned i;
 312 +       void __iomem *base;
 313 +       int irqs[MAX_IRQS] = { 0 };
 314 +       u32 shift;
 315 +       bool toggle_clear_on_ack = false;
 316 +
 317 +       num_irqs = of_irq_count(node);
 318 +
 319 +       if (!num_irqs || num_irqs > MAX_IRQS)
 320 +               return -EINVAL;
 321 +
 322 +       if (of_property_read_u32(node, "brcm,field-width", &shift))
 323 +               shift = 4;
 324 +
 325 +       /* on BCM6318 setting CLEAR seems to continuously mask interrupts */
 326 +       if (of_device_is_compatible(node, "brcm,bcm6318-ext-intc"))
 327 +               toggle_clear_on_ack = true;
 328 +
 329 +       for (i = 0; i < num_irqs; i++) {
 330 +               irqs[i] = irq_of_parse_and_map(node, i);
 331 +               if (!irqs[i])
 332 +                       return -ENOMEM;
 333 +       }
 334 +
 335 +       base = of_iomap(node, 0);
 336 +       if (!base)
 337 +               return -ENXIO;
 338 +
 339 +       ret = __bcm6345_ext_intc_init(node, num_irqs, irqs, base, shift,
 340 +                                     toggle_clear_on_ack);
 341 +       if (!ret)
 342 +               return 0;
 343 +
 344 +       iounmap(base);
 345 +
 346 +       for (i = 0; i < num_irqs; i++)
 347 +               irq_dispose_mapping(irqs[i]);
 348 +
 349 +       return ret;
 350 +}
 351 +
 352 +IRQCHIP_DECLARE(bcm6318_ext_intc, "brcm,bcm6318-ext-intc",
 353 +               bcm6345_ext_intc_of_init);
 354 +IRQCHIP_DECLARE(bcm6345_ext_intc, "brcm,bcm6345-ext-intc",
 355 +               bcm6345_ext_intc_of_init);
 356 +#endif
 357 --- /dev/null
 358 +++ b/include/linux/irqchip/irq-bcm6345-ext.h
 359 @@ -0,0 +1,14 @@
 360 +/*
 361 + * This file is subject to the terms and conditions of the GNU General Public
 362 + * License.  See the file "COPYING" in the main directory of this archive
 363 + * for more details.
 364 + *
 365 + * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
 366 + */
 367 +
 368 +#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H
 369 +#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H
 370 +
 371 +void bcm6345_ext_intc_init(int n_irqs, int *irqs, void __iomem *reg, int shift);
 372 +
 373 +#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H */