target/linux/bmips/files/drivers/pci/controller/pci-bcm6348.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * BCM6348 PCI Controller Driver
   4  *
   5  * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
   6  * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
   7  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/kernel.h>
  14 #include <linux/memblock.h>
  15 #include <linux/mm.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_pci.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/pci.h>
  22 #include <linux/reset.h>
  23 #include <linux/types.h>
  24 #include <linux/vmalloc.h>
  25
  26 #include "../pci.h"
  27
  28 #define CARDBUS_DUMMY_ID                0x6348
  29 #define CARDBUS_PCI_IDSEL               0x8
  30 #define FAKE_CB_BRIDGE_SLOT             0x1e
  31
  32 #define BCMPCI_REG_TIMERS               0x40
  33 #define REG_TIMER_TRDY_SHIFT            0
  34 #define REG_TIMER_TRDY_MASK             (0xff << REG_TIMER_TRDY_SHIFT)
  35 #define REG_TIMER_RETRY_SHIFT           8
  36 #define REG_TIMER_RETRY_MASK            (0xff << REG_TIMER_RETRY_SHIFT)
  37
  38 #define MPI_SP0_RANGE_REG               0x100
  39 #define MPI_SP0_REMAP_REG               0x104
  40 #define MPI_SP0_REMAP_ENABLE_MASK       (1 << 0)
  41 #define MPI_SP1_RANGE_REG               0x10C
  42 #define MPI_SP1_REMAP_REG               0x110
  43 #define MPI_SP1_REMAP_ENABLE_MASK       (1 << 0)
  44
  45 #define MPI_L2PCFG_REG                  0x11c
  46 #define MPI_L2PCFG_CFG_TYPE_SHIFT       0
  47 #define MPI_L2PCFG_CFG_TYPE_MASK        (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
  48 #define MPI_L2PCFG_REG_SHIFT            2
  49 #define MPI_L2PCFG_REG_MASK             (0x3f << MPI_L2PCFG_REG_SHIFT)
  50 #define MPI_L2PCFG_FUNC_SHIFT           8
  51 #define MPI_L2PCFG_FUNC_MASK            (0x7 << MPI_L2PCFG_FUNC_SHIFT)
  52 #define MPI_L2PCFG_DEVNUM_SHIFT         11
  53 #define MPI_L2PCFG_DEVNUM_MASK          (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
  54 #define MPI_L2PCFG_CFG_USEREG_MASK      (1 << 30)
  55 #define MPI_L2PCFG_CFG_SEL_MASK         (1 << 31)
  56
  57 #define MPI_L2PMEMRANGE1_REG            0x120
  58 #define MPI_L2PMEMBASE1_REG             0x124
  59 #define MPI_L2PMEMREMAP1_REG            0x128
  60 #define MPI_L2PMEMRANGE2_REG            0x12C
  61 #define MPI_L2PMEMBASE2_REG             0x130
  62 #define MPI_L2PMEMREMAP2_REG            0x134
  63 #define MPI_L2PIORANGE_REG              0x138
  64 #define MPI_L2PIOBASE_REG               0x13C
  65 #define MPI_L2PIOREMAP_REG              0x140
  66 #define MPI_L2P_BASE_MASK               (0xffff8000)
  67 #define MPI_L2PREMAP_ENABLED_MASK       (1 << 0)
  68 #define MPI_L2PREMAP_IS_CARDBUS_MASK    (1 << 2)
  69
  70 #define MPI_PCIMODESEL_REG              0x144
  71 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
  72 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
  73 #define MPI_PCIMODESEL_EXT_ARB_MASK     (1 << 2)
  74 #define MPI_PCIMODESEL_PREFETCH_SHIFT   4
  75 #define MPI_PCIMODESEL_PREFETCH_MASK    (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
  76
  77 #define MPI_LOCBUSCTL_REG               0x14c
  78 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK  (1 << 0)
  79 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK   (1 << 1)
  80
  81 #define MPI_LOCINT_REG                  0x150
  82 #define MPI_LOCINT_MASK(x)              (1 << (x + 16))
  83 #define MPI_LOCINT_STAT(x)              (1 << (x))
  84 #define MPI_LOCINT_DIR_FAILED           6
  85 #define MPI_LOCINT_EXT_PCI_INT          7
  86 #define MPI_LOCINT_SERR                 8
  87 #define MPI_LOCINT_CSERR                9
  88
  89 #define MPI_PCICFGCTL_REG               0x178
  90 #define MPI_PCICFGCTL_CFGADDR_SHIFT     2
  91 #define MPI_PCICFGCTL_CFGADDR_MASK      (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
  92 #define MPI_PCICFGCTL_WRITEEN_MASK      (1 << 7)
  93
  94 #define MPI_PCICFGDATA_REG              0x17c
  95
  96 #define PCMCIA_OFFSET                   0x54
  97
  98 #define PCMCIA_C1_REG                   0x0
  99 #define PCMCIA_C1_CD1_MASK              (1 << 0)
 100 #define PCMCIA_C1_CD2_MASK              (1 << 1)
 101 #define PCMCIA_C1_VS1_MASK              (1 << 2)
 102 #define PCMCIA_C1_VS2_MASK              (1 << 3)
 103 #define PCMCIA_C1_VS1OE_MASK            (1 << 6)
 104 #define PCMCIA_C1_VS2OE_MASK            (1 << 7)
 105 #define PCMCIA_C1_CBIDSEL_SHIFT         (8)
 106 #define PCMCIA_C1_CBIDSEL_MASK          (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
 107 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK   (1 << 13)
 108 #define PCMCIA_C1_EN_PCMCIA_MASK        (1 << 14)
 109 #define PCMCIA_C1_EN_CARDBUS_MASK       (1 << 15)
 110 #define PCMCIA_C1_RESET_MASK            (1 << 18)
 111
 112 #ifdef CONFIG_CARDBUS
 113 struct bcm6348_cb {
 114         u16 pci_command;
 115         u8 cb_latency;
 116         u8 subordinate_busn;
 117         u8 cardbus_busn;
 118         u8 pci_busn;
 119         int bus_assigned;
 120         u16 bridge_control;
 121
 122         u32 mem_base0;
 123         u32 mem_limit0;
 124         u32 mem_base1;
 125         u32 mem_limit1;
 126
 127         u32 io_base0;
 128         u32 io_limit0;
 129         u32 io_base1;
 130         u32 io_limit1;
 131 };
 132 #endif /* CONFIG_CARDBUS */
 133
 134 struct bcm6348_pci {
 135         void __iomem *pci;
 136         void __iomem *pcmcia;
 137         void __iomem *io;
 138         int irq;
 139         struct reset_control *reset;
 140         bool remap;
 141 #ifdef CONFIG_CARDBUS
 142         struct bcm6348_cb cb;
 143         int cb_bus;
 144 #endif /* CONFIG_CARDBUS */
 145 };
 146
 147 static struct bcm6348_pci bcm6348_pci;
 148
 149 extern int bmips_pci_irq;
 150
 151 static u32 bcm6348_int_cfg_readl(u32 reg)
 152 {
 153         struct bcm6348_pci *priv = &bcm6348_pci;
 154         u32 tmp;
 155
 156         tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
 157         tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
 158         __raw_writel(tmp, priv->pci + MPI_PCICFGCTL_REG);
 159         iob();
 160         return __raw_readl(priv->pci + MPI_PCICFGDATA_REG);
 161 }
 162
 163 static void bcm6348_int_cfg_writel(u32 val, u32 reg)
 164 {
 165         struct bcm6348_pci *priv = &bcm6348_pci;
 166         u32 tmp;
 167
 168         tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
 169         tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
 170         __raw_writel(tmp, priv->pci + MPI_PCICFGCTL_REG);
 171         __raw_writel(val, priv->pci + MPI_PCICFGDATA_REG);
 172 }
 173
 174 /*
 175  * swizzle 32bits data to return only the needed part
 176  */
 177 static int postprocess_read(u32 data, int where, unsigned int size)
 178 {
 179         u32 ret = 0;
 180
 181         switch (size) {
 182         case 1:
 183                 ret = (data >> ((where & 3) << 3)) & 0xff;
 184                 break;
 185         case 2:
 186                 ret = (data >> ((where & 3) << 3)) & 0xffff;
 187                 break;
 188         case 4:
 189                 ret = data;
 190                 break;
 191         }
 192
 193         return ret;
 194 }
 195
 196 static int preprocess_write(u32 orig_data, u32 val, int where,
 197                             unsigned int size)
 198 {
 199         u32 ret = 0;
 200
 201         switch (size) {
 202         case 1:
 203                 ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
 204                         (val << ((where & 3) << 3));
 205                 break;
 206         case 2:
 207                 ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
 208                         (val << ((where & 3) << 3));
 209                 break;
 210         case 4:
 211                 ret = val;
 212                 break;
 213         }
 214
 215         return ret;
 216 }
 217
 218 static int bcm6348_setup_cfg_access(int type, unsigned int busn,
 219                                     unsigned int devfn, int where)
 220 {
 221         struct bcm6348_pci *priv = &bcm6348_pci;
 222         unsigned int slot, func, reg;
 223         u32 val;
 224
 225         slot = PCI_SLOT(devfn);
 226         func = PCI_FUNC(devfn);
 227         reg = where >> 2;
 228
 229         /* sanity check */
 230         if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
 231                 return 1;
 232
 233         if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
 234                 return 1;
 235
 236         if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
 237                 return 1;
 238
 239         /* ok, setup config access */
 240         val = (reg << MPI_L2PCFG_REG_SHIFT);
 241         val |= (func << MPI_L2PCFG_FUNC_SHIFT);
 242         val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
 243         val |= MPI_L2PCFG_CFG_USEREG_MASK;
 244         val |= MPI_L2PCFG_CFG_SEL_MASK;
 245         /* type 0 cycle for local bus, type 1 cycle for anything else */
 246         if (type != 0) {
 247                 /* FIXME: how to specify bus ??? */
 248                 val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
 249         }
 250         __raw_writel(val, priv->pci + MPI_L2PCFG_REG);
 251
 252         return 0;
 253 }
 254
 255
 256 static int bcm6348_do_cfg_read(int type, unsigned int busn,
 257                                unsigned int devfn, int where, int size,
 258                                u32 *val)
 259 {
 260         struct bcm6348_pci *priv = &bcm6348_pci;
 261         u32 data;
 262
 263         /* two phase cycle, first we write address, then read data at
 264          * another location, caller already has a spinlock so no need
 265          * to add one here */
 266         if (bcm6348_setup_cfg_access(type, busn, devfn, where))
 267                 return PCIBIOS_DEVICE_NOT_FOUND;
 268         iob();
 269         data = le32_to_cpu(__raw_readl(priv->io));
 270         /* restore IO space normal behaviour */
 271         __raw_writel(0, priv->pci + MPI_L2PCFG_REG);
 272
 273         *val = postprocess_read(data, where, size);
 274
 275         return PCIBIOS_SUCCESSFUL;
 276 }
 277
 278 static int bcm6348_do_cfg_write(int type, unsigned int busn,
 279                                 unsigned int devfn, int where, int size,
 280                                 u32 val)
 281 {
 282         struct bcm6348_pci *priv = &bcm6348_pci;
 283         u32 data;
 284
 285         /* two phase cycle, first we write address, then write data to
 286          * another location, caller already has a spinlock so no need
 287          * to add one here */
 288         if (bcm6348_setup_cfg_access(type, busn, devfn, where))
 289                 return PCIBIOS_DEVICE_NOT_FOUND;
 290         iob();
 291
 292         data = le32_to_cpu(__raw_readl(priv->io));
 293         data = preprocess_write(data, val, where, size);
 294
 295         __raw_writel(cpu_to_le32(data), priv->io);
 296         wmb();
 297         /* no way to know the access is done, we have to wait */
 298         udelay(500);
 299         /* restore IO space normal behaviour */
 300         __raw_writel(0, priv->pci + MPI_L2PCFG_REG);
 301
 302         return PCIBIOS_SUCCESSFUL;
 303 }
 304
 305 static int bcm6348_pci_read(struct pci_bus *bus, unsigned int devfn,
 306                              int where, int size, u32 *val)
 307 {
 308         int type;
 309
 310         type = bus->parent ? 1 : 0;
 311
 312         if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
 313                 return PCIBIOS_DEVICE_NOT_FOUND;
 314
 315         return bcm6348_do_cfg_read(type, bus->number, devfn,
 316                                    where, size, val);
 317 }
 318
 319 static int bcm6348_pci_write(struct pci_bus *bus, unsigned int devfn,
 320                               int where, int size, u32 val)
 321 {
 322         int type;
 323
 324         type = bus->parent ? 1 : 0;
 325
 326         if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
 327                 return PCIBIOS_DEVICE_NOT_FOUND;
 328
 329         return bcm6348_do_cfg_write(type, bus->number, devfn,
 330                                     where, size, val);
 331 }
 332
 333 static struct pci_ops bcm6348_pci_ops = {
 334         .read = bcm6348_pci_read,
 335         .write = bcm6348_pci_write,
 336 };
 337
 338 static struct resource bcm6348_pci_io_resource = {
 339         .name = "BCM6348 PCI IO space",
 340         .flags = IORESOURCE_IO,
 341 };
 342 static struct resource bcm6348_pci_mem_resource;
 343 static struct resource bcm6348_pci_busn_resource;
 344
 345 static struct pci_controller bcm6348_pci_controller = {
 346         .pci_ops = &bcm6348_pci_ops,
 347         .io_resource = &bcm6348_pci_io_resource,
 348         .mem_resource = &bcm6348_pci_mem_resource,
 349 };
 350
 351 #ifdef CONFIG_CARDBUS
 352 static int bcm6348_cb_bridge_read(int where, int size, u32 *val)
 353 {
 354         struct bcm6348_cb *cb = &bcm6348_pci.cb;
 355         unsigned int reg;
 356         u32 data;
 357
 358         data = 0;
 359         reg = where >> 2;
 360         switch (reg) {
 361         case (PCI_VENDOR_ID >> 2):
 362         case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):
 363                 /* create dummy vendor/device id from our cpu id */
 364                 data = (CARDBUS_DUMMY_ID << 16) | PCI_VENDOR_ID_BROADCOM;
 365                 break;
 366
 367         case (PCI_COMMAND >> 2):
 368                 data = (PCI_STATUS_DEVSEL_SLOW << 16);
 369                 data |= cb->pci_command;
 370                 break;
 371
 372         case (PCI_CLASS_REVISION >> 2):
 373                 data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
 374                 break;
 375
 376         case (PCI_CACHE_LINE_SIZE >> 2):
 377                 data = (PCI_HEADER_TYPE_CARDBUS << 16);
 378                 break;
 379
 380         case (PCI_INTERRUPT_LINE >> 2):
 381                 /* bridge control */
 382                 data = (cb->bridge_control << 16);
 383                 /* pin:intA line:0xff */
 384                 data |= (0x1 << 8) | 0xff;
 385                 break;
 386
 387         case (PCI_CB_PRIMARY_BUS >> 2):
 388                 data = (cb->cb_latency << 24);
 389                 data |= (cb->subordinate_busn << 16);
 390                 data |= (cb->cardbus_busn << 8);
 391                 data |= cb->pci_busn;
 392                 break;
 393
 394         case (PCI_CB_MEMORY_BASE_0 >> 2):
 395                 data = cb->mem_base0;
 396                 break;
 397
 398         case (PCI_CB_MEMORY_LIMIT_0 >> 2):
 399                 data = cb->mem_limit0;
 400                 break;
 401
 402         case (PCI_CB_MEMORY_BASE_1 >> 2):
 403                 data = cb->mem_base1;
 404                 break;
 405
 406         case (PCI_CB_MEMORY_LIMIT_1 >> 2):
 407                 data = cb->mem_limit1;
 408                 break;
 409
 410         case (PCI_CB_IO_BASE_0 >> 2):
 411                 /* | 1 for 32bits io support */
 412                 data = cb->io_base0 | 0x1;
 413                 break;
 414
 415         case (PCI_CB_IO_LIMIT_0 >> 2):
 416                 data = cb->io_limit0;
 417                 break;
 418
 419         case (PCI_CB_IO_BASE_1 >> 2):
 420                 /* | 1 for 32bits io support */
 421                 data = cb->io_base1 | 0x1;
 422                 break;
 423
 424         case (PCI_CB_IO_LIMIT_1 >> 2):
 425                 data = cb->io_limit1;
 426                 break;
 427         }
 428
 429         *val = postprocess_read(data, where, size);
 430         return PCIBIOS_SUCCESSFUL;
 431 }
 432
 433 /*
 434  * emulate configuration write access on a cardbus bridge
 435  */
 436 static int bcm6348_cb_bridge_write(int where, int size, u32 val)
 437 {
 438         struct bcm6348_cb *cb = &bcm6348_pci.cb;
 439         unsigned int reg;
 440         u32 data, tmp;
 441         int ret;
 442
 443         ret = bcm6348_cb_bridge_read((where & ~0x3), 4, &data);
 444         if (ret != PCIBIOS_SUCCESSFUL)
 445                 return ret;
 446
 447         data = preprocess_write(data, val, where, size);
 448
 449         reg = where >> 2;
 450         switch (reg) {
 451         case (PCI_COMMAND >> 2):
 452                 cb->pci_command = (data & 0xffff);
 453                 break;
 454
 455         case (PCI_CB_PRIMARY_BUS >> 2):
 456                 cb->cb_latency = (data >> 24) & 0xff;
 457                 cb->subordinate_busn = (data >> 16) & 0xff;
 458                 cb->cardbus_busn = (data >> 8) & 0xff;
 459                 cb->pci_busn = data & 0xff;
 460                 if (cb->cardbus_busn)
 461                         cb->bus_assigned = 1;
 462                 break;
 463
 464         case (PCI_INTERRUPT_LINE >> 2):
 465                 tmp = (data >> 16) & 0xffff;
 466                 /* Disable memory prefetch support */
 467                 tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
 468                 tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
 469                 cb->bridge_control = tmp;
 470                 break;
 471
 472         case (PCI_CB_MEMORY_BASE_0 >> 2):
 473                 cb->mem_base0 = data;
 474                 break;
 475
 476         case (PCI_CB_MEMORY_LIMIT_0 >> 2):
 477                 cb->mem_limit0 = data;
 478                 break;
 479
 480         case (PCI_CB_MEMORY_BASE_1 >> 2):
 481                 cb->mem_base1 = data;
 482                 break;
 483
 484         case (PCI_CB_MEMORY_LIMIT_1 >> 2):
 485                 cb->mem_limit1 = data;
 486                 break;
 487
 488         case (PCI_CB_IO_BASE_0 >> 2):
 489                 cb->io_base0 = data;
 490                 break;
 491
 492         case (PCI_CB_IO_LIMIT_0 >> 2):
 493                 cb->io_limit0 = data;
 494                 break;
 495
 496         case (PCI_CB_IO_BASE_1 >> 2):
 497                 cb->io_base1 = data;
 498                 break;
 499
 500         case (PCI_CB_IO_LIMIT_1 >> 2):
 501                 cb->io_limit1 = data;
 502                 break;
 503         }
 504
 505         return PCIBIOS_SUCCESSFUL;
 506 }
 507
 508 static int bcm6348_cb_read(struct pci_bus *bus, unsigned int devfn,
 509                            int where, int size, u32 *val)
 510 {
 511         struct bcm6348_pci *priv = &bcm6348_pci;
 512         struct bcm6348_cb *cb = &priv->cb;
 513
 514         /* Snoop access to slot 0x1e on root bus, we fake a cardbus
 515          * bridge at this location */
 516         if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
 517                 priv->cb_bus = bus->number;
 518                 return bcm6348_cb_bridge_read(where, size, val);
 519         }
 520
 521         /* A configuration cycle for the device behind the cardbus
 522          * bridge is actually done as a type 0 cycle on the primary
 523          * bus. This means that only one device can be on the cardbus
 524          * bus */
 525         if (cb->bus_assigned &&
 526             bus->number == cb->cardbus_busn &&
 527             PCI_SLOT(devfn) == 0)
 528                 return bcm6348_do_cfg_read(0, 0,
 529                                            PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
 530                                            where, size, val);
 531
 532         return PCIBIOS_DEVICE_NOT_FOUND;
 533 }
 534
 535 static int bcm6348_cb_write(struct pci_bus *bus, unsigned int devfn,
 536                             int where, int size, u32 val)
 537 {
 538         struct bcm6348_pci *priv = &bcm6348_pci;
 539         struct bcm6348_cb *cb = &priv->cb;
 540
 541         if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
 542                 priv->cb_bus = bus->number;
 543                 return bcm6348_cb_bridge_write(where, size, val);
 544         }
 545
 546         if (cb->bus_assigned &&
 547             bus->number == cb->cardbus_busn &&
 548             PCI_SLOT(devfn) == 0)
 549                 return bcm6348_do_cfg_write(0, 0,
 550                                             PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
 551                                             where, size, val);
 552
 553         return PCIBIOS_DEVICE_NOT_FOUND;
 554 }
 555
 556 static struct pci_ops bcm6348_cb_ops = {
 557         .read = bcm6348_cb_read,
 558         .write = bcm6348_cb_write,
 559 };
 560
 561 /*
 562  * only one IO window, so it  cannot be shared by PCI and cardbus, use
 563  * fixup to choose and detect unhandled configuration
 564  */
 565 static void bcm6348_pci_fixup(struct pci_dev *dev)
 566 {
 567         struct bcm6348_pci *priv = &bcm6348_pci;
 568         struct bcm6348_cb *cb = &priv->cb;
 569         static int io_window = -1;
 570         int i, found, new_io_window;
 571         u32 val;
 572
 573         /* look for any io resource */
 574         found = 0;
 575         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 576                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
 577                         found = 1;
 578                         break;
 579                 }
 580         }
 581
 582         if (!found)
 583                 return;
 584
 585         /* skip our fake bus with only cardbus bridge on it */
 586         if (dev->bus->number == priv->cb_bus)
 587                 return;
 588
 589         /* find on which bus the device is */
 590         if (cb->bus_assigned &&
 591             dev->bus->number == cb->cardbus_busn &&
 592             PCI_SLOT(dev->devfn) == 0)
 593                 new_io_window = 1;
 594         else
 595                 new_io_window = 0;
 596
 597         if (new_io_window == io_window)
 598                 return;
 599
 600         if (io_window != -1) {
 601                 pr_err("bcm63xx: both PCI and cardbus devices "
 602                        "need IO, which hardware cannot do\n");
 603                 return;
 604         }
 605
 606         pr_info("bcm63xx: PCI IO window assigned to %s\n",
 607                (new_io_window == 0) ? "PCI" : "cardbus");
 608
 609         val = __raw_readl(priv->pci + MPI_L2PIOREMAP_REG);
 610         if (io_window)
 611                 val |= MPI_L2PREMAP_IS_CARDBUS_MASK;
 612         else
 613                 val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;
 614         __raw_writel(val, priv->pci + MPI_L2PIOREMAP_REG);
 615
 616         io_window = new_io_window;
 617 }
 618 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm6348_pci_fixup);
 619
 620 static struct resource bcm6348_cb_io_resource = {
 621         .name = "bcm6348 CB IO space",
 622         .flags = IORESOURCE_IO,
 623 };
 624 static struct resource bcm6348_cb_mem_resource;
 625
 626 static struct pci_controller bcm6348_cb_controller = {
 627         .pci_ops = &bcm6348_cb_ops,
 628         .io_resource = &bcm6348_cb_io_resource,
 629         .mem_resource = &bcm6348_cb_mem_resource,
 630 };
 631 #endif /* CONFIG_CARDBUS */
 632
 633 static void bcm6348_pci_setup(struct bcm6348_pci *priv)
 634 {
 635         u32 val;
 636
 637         /* Setup local bus to PCI access (PCI memory) */
 638         val = bcm6348_pci_mem_resource.start & MPI_L2P_BASE_MASK;
 639         __raw_writel(val, priv->pci + MPI_L2PMEMBASE1_REG);
 640         __raw_writel(~(resource_size(&bcm6348_pci_mem_resource) - 1),
 641                      priv->pci + MPI_L2PMEMRANGE1_REG);
 642         __raw_writel(val | MPI_L2PREMAP_ENABLED_MASK,
 643                      priv->pci + MPI_L2PMEMREMAP1_REG);
 644
 645         /* Set Cardbus IDSEL (type 0 cfg access on primary bus for
 646          * this IDSEL will be done on Cardbus instead) */
 647         val = __raw_readl(priv->pcmcia + PCMCIA_C1_REG);
 648         val &= ~PCMCIA_C1_CBIDSEL_MASK;
 649         val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
 650         __raw_writel(val, priv->pcmcia + PCMCIA_C1_REG);
 651
 652 #ifdef CONFIG_CARDBUS
 653         /* setup local bus to PCI access (Cardbus memory) */
 654         val = bcm6348_cb_mem_resource.start & MPI_L2P_BASE_MASK;
 655         __raw_writel(val, priv->pci + MPI_L2PMEMBASE2_REG);
 656         __raw_writel(~(resource_size(&bcm6348_cb_mem_resource) - 1),
 657                      priv->pci + MPI_L2PMEMRANGE2_REG);
 658         val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
 659         __raw_writel(val, priv->pci + MPI_L2PMEMREMAP2_REG);
 660 #else
 661         /* disable second access windows */
 662         __raw_writel(0, priv->pci + MPI_L2PMEMREMAP2_REG);
 663 #endif
 664
 665         /* setup local bus to PCI access (IO memory), we have only 1
 666          * IO window for both PCI and cardbus, but it cannot handle
 667          * both at the same time, assume standard PCI for now, if
 668          * cardbus card has IO zone, PCI fixup will change window to
 669          * cardbus */
 670         val = bcm6348_pci_io_resource.start & MPI_L2P_BASE_MASK;
 671         __raw_writel(val, priv->pci + MPI_L2PIOBASE_REG);
 672         __raw_writel(~(resource_size(&bcm6348_pci_io_resource) - 1),
 673                      priv->pci + MPI_L2PIORANGE_REG);
 674         __raw_writel(val | MPI_L2PREMAP_ENABLED_MASK,
 675                      priv->pci + MPI_L2PIOREMAP_REG);
 676
 677         /* Enable PCI related GPIO pins */
 678         __raw_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK,
 679                      priv->pci + MPI_LOCBUSCTL_REG);
 680
 681         /* Setup PCI to local bus access, used by PCI device to target
 682          * local RAM while bus mastering */
 683         bcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
 684         if (priv->remap)
 685                 val = MPI_SP0_REMAP_ENABLE_MASK;
 686         else
 687                 val = 0;
 688         __raw_writel(val, priv->pci + MPI_SP0_REMAP_REG);
 689
 690         bcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_4);
 691         __raw_writel(0, priv->pci + MPI_SP1_REMAP_REG);
 692
 693         /* Setup sp0 range to local RAM size */
 694         __raw_writel(~(memblock_phys_mem_size() - 1),
 695                      priv->pci + MPI_SP0_RANGE_REG);
 696         __raw_writel(0, priv->pci + MPI_SP1_RANGE_REG);
 697
 698         /* Change host bridge retry counter to infinite number of
 699          * retries, needed for some broadcom wifi cards with Silicon
 700          * Backplane bus where access to srom seems very slow */
 701         val = bcm6348_int_cfg_readl(BCMPCI_REG_TIMERS);
 702         val &= ~REG_TIMER_RETRY_MASK;
 703         bcm6348_int_cfg_writel(val, BCMPCI_REG_TIMERS);
 704
 705         /* EEnable memory decoder and bus mastering */
 706         val = bcm6348_int_cfg_readl(PCI_COMMAND);
 707         val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 708         bcm6348_int_cfg_writel(val, PCI_COMMAND);
 709
 710         /* Enable read prefetching & disable byte swapping for bus
 711          * mastering transfers */
 712         val = __raw_readl(priv->pci + MPI_PCIMODESEL_REG);
 713         val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
 714         val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
 715         val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
 716         val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
 717         __raw_writel(val, priv->pci + MPI_PCIMODESEL_REG);
 718
 719         /* Enable pci interrupt */
 720         val = __raw_readl(priv->pci + MPI_LOCINT_REG);
 721         val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
 722         __raw_writel(val, priv->pci + MPI_LOCINT_REG);
 723 }
 724
 725 static int bcm6348_pci_probe(struct platform_device *pdev)
 726 {
 727         struct device *dev = &pdev->dev;
 728         struct device_node *np = dev->of_node;
 729         struct bcm6348_pci *priv = &bcm6348_pci;
 730         struct resource *res;
 731         LIST_HEAD(resources);
 732
 733         of_pci_check_probe_only();
 734
 735         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pci");
 736         priv->pci = devm_ioremap_resource(dev, res);
 737         if (IS_ERR(priv->pci))
 738                 return PTR_ERR(priv->pci);
 739
 740         priv->pcmcia = priv->pci + PCMCIA_OFFSET;
 741
 742         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pci-io");
 743         if (!res)
 744                 return -EINVAL;
 745 #ifdef CONFIG_CARDBUS
 746         bcm6348_pci_io_resource.start = res->start;
 747         bcm6348_pci_io_resource.end = res->end - (resource_size(res) >> 1);
 748         bcm6348_cb_io_resource.start = res->start + (resource_size(res) >> 1);
 749         bcm6348_cb_io_resource.end = res->end;
 750 #else
 751         bcm6348_pci_io_resource.start = res->start;
 752         bcm6348_pci_io_resource.end = res->end;
 753 #endif
 754
 755         priv->irq = platform_get_irq(pdev, 0);
 756         if (!priv->irq)
 757                 return -ENODEV;
 758
 759         bmips_pci_irq = priv->irq;
 760
 761         priv->reset = devm_reset_control_get(dev, "pci");
 762         if (IS_ERR(priv->reset))
 763                 return PTR_ERR(priv->reset);
 764
 765         priv->remap = of_property_read_bool(np, "brcm,remap");
 766
 767         reset_control_reset(priv->reset);
 768
 769         pci_load_of_ranges(&bcm6348_pci_controller, np);
 770         if (!bcm6348_pci_mem_resource.start)
 771                 return -EINVAL;
 772
 773         of_pci_parse_bus_range(np, &bcm6348_pci_busn_resource);
 774         pci_add_resource(&resources, &bcm6348_pci_busn_resource);
 775
 776         /*
 777          * Configuration accesses are done through IO space, remap 4
 778          * first bytes to access it from CPU.
 779          *
 780          * This means that no IO access from CPU should happen while
 781          * we do a configuration cycle, but there's no way we can add
 782          * a spinlock for each io access, so this is currently kind of
 783          * broken on SMP.
 784          */
 785         priv->io = ioremap(bcm6348_pci_io_resource.start, sizeof(u32));
 786         if (!priv->io)
 787                 return -ENOMEM;
 788
 789         bcm6348_pci_setup(priv);
 790
 791         register_pci_controller(&bcm6348_pci_controller);
 792
 793 #ifdef CONFIG_CARDBUS
 794         priv->cb_bus = -1;
 795         register_pci_controller(&bcm6348_cb_controller);
 796 #endif /* CONFIG_CARDBUS */
 797
 798         /* Mark memory space used for IO mapping as reserved */
 799         request_mem_region(bcm6348_pci_io_resource.start,
 800                            resource_size(&bcm6348_pci_io_resource),
 801                            "BCM6348 PCI IO space");
 802
 803         return 0;
 804 }
 805
 806 static const struct of_device_id bcm6348_pci_of_match[] = {
 807         { .compatible = "brcm,bcm6348-pci", },
 808         { /* sentinel */ }
 809 };
 810
 811 static struct platform_driver bcm6348_pci_driver = {
 812         .probe = bcm6348_pci_probe,
 813         .driver = {
 814                 .name = "bcm6348-pci",
 815                 .of_match_table = bcm6348_pci_of_match,
 816         },
 817 };
 818
 819 int __init bcm6348_pci_init(void)
 820 {
 821         int ret = platform_driver_register(&bcm6348_pci_driver);
 822         if (ret)
 823                 pr_err("pci-bcm6348: Error registering platform driver!\n");
 824         return ret;
 825 }
 826 late_initcall_sync(bcm6348_pci_init);