b9e9af35b8e9b412bb4d0a73e6971d8ee060adaa
[openwrt/staging/dedeckeh.git] / target / linux / ar71xx / files / drivers / net / dsa / mv88e6063.c
1 /*
2 * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips
3 * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>
4 *
5 * This driver was base on: net/dsa/mv88e6060.c
6 * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips
7 * Copyright (c) 2008-2009 Marvell Semiconductor
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15 #include <linux/version.h>
16 #include <linux/list.h>
17 #include <linux/netdevice.h>
18 #include <linux/phy.h>
19 #include <net/dsa.h>
20
21 #define REG_BASE 0x10
22 #define REG_PHY(p) (REG_BASE + (p))
23 #define REG_PORT(p) (REG_BASE + 8 + (p))
24 #define REG_GLOBAL (REG_BASE + 0x0f)
25 #define NUM_PORTS 7
26
27 static int reg_read(struct dsa_switch *ds, int addr, int reg)
28 {
29 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
30 return mdiobus_read(ds->master_mii_bus, addr, reg);
31 #else
32 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
33 return mdiobus_read(bus, addr, reg);
34 #endif
35 }
36
37 #define REG_READ(addr, reg) \
38 ({ \
39 int __ret; \
40 \
41 __ret = reg_read(ds, addr, reg); \
42 if (__ret < 0) \
43 return __ret; \
44 __ret; \
45 })
46
47
48 static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
49 {
50 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
51 return mdiobus_write(ds->master_mii_bus, addr, reg, val);
52 #else
53 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
54 return mdiobus_write(bus, addr, reg, val);
55 #endif
56 }
57
58 #define REG_WRITE(addr, reg, val) \
59 ({ \
60 int __ret; \
61 \
62 __ret = reg_write(ds, addr, reg, val); \
63 if (__ret < 0) \
64 return __ret; \
65 })
66
67 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
68 static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr)
69 {
70 #else
71 static char *mv88e6063_probe(struct device *host_dev, int sw_addr)
72 {
73 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
74 #endif
75 int ret;
76
77 ret = mdiobus_read(bus, REG_PORT(0), 0x03);
78 if (ret >= 0) {
79 ret &= 0xfff0;
80 if (ret == 0x1530)
81 return "Marvell 88E6063";
82 }
83
84 return NULL;
85 }
86
87 static int mv88e6063_switch_reset(struct dsa_switch *ds)
88 {
89 int i;
90 int ret;
91
92 /*
93 * Set all ports to the disabled state.
94 */
95 for (i = 0; i < NUM_PORTS; i++) {
96 ret = REG_READ(REG_PORT(i), 0x04);
97 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
98 }
99
100 /*
101 * Wait for transmit queues to drain.
102 */
103 msleep(2);
104
105 /*
106 * Reset the switch.
107 */
108 REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
109
110 /*
111 * Wait up to one second for reset to complete.
112 */
113 for (i = 0; i < 1000; i++) {
114 ret = REG_READ(REG_GLOBAL, 0x00);
115 if ((ret & 0x8000) == 0x0000)
116 break;
117
118 msleep(1);
119 }
120 if (i == 1000)
121 return -ETIMEDOUT;
122
123 return 0;
124 }
125
126 static int mv88e6063_setup_global(struct dsa_switch *ds)
127 {
128 /*
129 * Disable discarding of frames with excessive collisions,
130 * set the maximum frame size to 1536 bytes, and mask all
131 * interrupt sources.
132 */
133 REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
134
135 /*
136 * Enable automatic address learning, set the address
137 * database size to 1024 entries, and set the default aging
138 * time to 5 minutes.
139 */
140 REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
141
142 return 0;
143 }
144
145 static int mv88e6063_setup_port(struct dsa_switch *ds, int p)
146 {
147 int addr = REG_PORT(p);
148
149 /*
150 * Do not force flow control, disable Ingress and Egress
151 * Header tagging, disable VLAN tunneling, and set the port
152 * state to Forwarding. Additionally, if this is the CPU
153 * port, enable Ingress and Egress Trailer tagging mode.
154 */
155 REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
156
157 /*
158 * Port based VLAN map: give each port its own address
159 * database, allow the CPU port to talk to each of the 'real'
160 * ports, and allow each of the 'real' ports to only talk to
161 * the CPU port.
162 */
163 REG_WRITE(addr, 0x06,
164 ((p & 0xf) << 12) |
165 (dsa_is_cpu_port(ds, p) ?
166 ds->phys_port_mask :
167 (1 << ds->dst->cpu_port)));
168
169 /*
170 * Port Association Vector: when learning source addresses
171 * of packets, add the address to the address database using
172 * a port bitmap that has only the bit for this port set and
173 * the other bits clear.
174 */
175 REG_WRITE(addr, 0x0b, 1 << p);
176
177 return 0;
178 }
179
180 static int mv88e6063_setup(struct dsa_switch *ds)
181 {
182 int i;
183 int ret;
184
185 ret = mv88e6063_switch_reset(ds);
186 if (ret < 0)
187 return ret;
188
189 /* @@@ initialise atu */
190
191 ret = mv88e6063_setup_global(ds);
192 if (ret < 0)
193 return ret;
194
195 for (i = 0; i < NUM_PORTS; i++) {
196 ret = mv88e6063_setup_port(ds, i);
197 if (ret < 0)
198 return ret;
199 }
200
201 return 0;
202 }
203
204 static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr)
205 {
206 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
207 REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
208 REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
209
210 return 0;
211 }
212
213 static int mv88e6063_port_to_phy_addr(int port)
214 {
215 if (port >= 0 && port <= NUM_PORTS)
216 return REG_PHY(port);
217 return -1;
218 }
219
220 static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum)
221 {
222 int addr;
223
224 addr = mv88e6063_port_to_phy_addr(port);
225 if (addr == -1)
226 return 0xffff;
227
228 return reg_read(ds, addr, regnum);
229 }
230
231 static int
232 mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
233 {
234 int addr;
235
236 addr = mv88e6063_port_to_phy_addr(port);
237 if (addr == -1)
238 return 0xffff;
239
240 return reg_write(ds, addr, regnum, val);
241 }
242
243 static void mv88e6063_poll_link(struct dsa_switch *ds)
244 {
245 int i;
246
247 for (i = 0; i < DSA_MAX_PORTS; i++) {
248 struct net_device *dev;
249 int uninitialized_var(port_status);
250 int link;
251 int speed;
252 int duplex;
253 int fc;
254
255 dev = ds->ports[i];
256 if (dev == NULL)
257 continue;
258
259 link = 0;
260 if (dev->flags & IFF_UP) {
261 port_status = reg_read(ds, REG_PORT(i), 0x00);
262 if (port_status < 0)
263 continue;
264
265 link = !!(port_status & 0x1000);
266 }
267
268 if (!link) {
269 if (netif_carrier_ok(dev)) {
270 printk(KERN_INFO "%s: link down\n", dev->name);
271 netif_carrier_off(dev);
272 }
273 continue;
274 }
275
276 speed = (port_status & 0x0100) ? 100 : 10;
277 duplex = (port_status & 0x0200) ? 1 : 0;
278 fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
279
280 if (!netif_carrier_ok(dev)) {
281 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
282 "flow control %sabled\n", dev->name,
283 speed, duplex ? "full" : "half",
284 fc ? "en" : "dis");
285 netif_carrier_on(dev);
286 }
287 }
288 }
289
290 static struct dsa_switch_driver mv88e6063_switch_driver = {
291 .tag_protocol = htons(ETH_P_TRAILER),
292 .probe = mv88e6063_probe,
293 .setup = mv88e6063_setup,
294 .set_addr = mv88e6063_set_addr,
295 .phy_read = mv88e6063_phy_read,
296 .phy_write = mv88e6063_phy_write,
297 .poll_link = mv88e6063_poll_link,
298 };
299
300 static int __init mv88e6063_init(void)
301 {
302 register_switch_driver(&mv88e6063_switch_driver);
303 return 0;
304 }
305 module_init(mv88e6063_init);
306
307 static void __exit mv88e6063_cleanup(void)
308 {
309 unregister_switch_driver(&mv88e6063_switch_driver);
310 }
311 module_exit(mv88e6063_cleanup);