package/kernel/mac80211/patches/rt2x00/006-v6.1-rt2x00-add-r-calibration-for-MT7620.patch

   1 From patchwork Sat Sep 17 20:27:41 2022
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   5 X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
   6 X-Patchwork-Id: 12979247
   7 X-Patchwork-Delegate: kvalo@adurom.com
   8 Return-Path: <linux-wireless-owner@kernel.org>
   9 Date: Sat, 17 Sep 2022 21:27:41 +0100
  10 From: Daniel Golle <daniel@makrotopia.org>
  11 To: linux-wireless@vger.kernel.org, Stanislaw Gruszka <stf_xl@wp.pl>,
  12         Helmut Schaa <helmut.schaa@googlemail.com>
  13 Cc: Kalle Valo <kvalo@kernel.org>,
  14         "David S. Miller" <davem@davemloft.net>,
  15         Eric Dumazet <edumazet@google.com>,
  16         Jakub Kicinski <kuba@kernel.org>,
  17         Paolo Abeni <pabeni@redhat.com>,
  18         Johannes Berg <johannes.berg@intel.com>
  19 Subject: [PATCH v3 06/16] rt2x00: add r calibration for MT7620
  20 Message-ID:
  21  <e0c34f233089bec4eb73826bc4f512166ee25934.1663445157.git.daniel@makrotopia.org>
  22 References: <cover.1663445157.git.daniel@makrotopia.org>
  23 MIME-Version: 1.0
  24 Content-Disposition: inline
  25 In-Reply-To: <cover.1663445157.git.daniel@makrotopia.org>
  26 Precedence: bulk
  27 List-ID: <linux-wireless.vger.kernel.org>
  28 X-Mailing-List: linux-wireless@vger.kernel.org
  29
  30 From: Tomislav Požega <pozega.tomislav@gmail.com>
  31
  32 Add r calibration code as found in mtk driver.
  33
  34 Signed-off-by: Tomislav Požega <pozega.tomislav@gmail.com>
  35 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  36 Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
  37 ---
  38 v2: use rt2800_wait_bbp_rf_ready()
  39
  40  drivers/net/wireless/ralink/rt2x00/rt2800.h   |   2 +
  41  .../net/wireless/ralink/rt2x00/rt2800lib.c    | 133 ++++++++++++++++++
  42  2 files changed, 135 insertions(+)
  43
  44 --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
  45 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
  46 @@ -1016,6 +1016,8 @@
  47   */
  48  #define MAC_STATUS_CFG                 0x1200
  49  #define MAC_STATUS_CFG_BBP_RF_BUSY     FIELD32(0x00000003)
  50 +#define MAC_STATUS_CFG_BBP_RF_BUSY_TX  FIELD32(0x00000001)
  51 +#define MAC_STATUS_CFG_BBP_RF_BUSY_RX  FIELD32(0x00000002)
  52
  53  /*
  54   * PWR_PIN_CFG:
  55 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  56 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  57 @@ -8501,6 +8501,138 @@ static void rt2800_rf_self_txdc_cal(stru
  58         rt2800_register_write(rt2x00dev, RF_BYPASS2, mac052c);
  59  }
  60
  61 +static int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2)
  62 +{
  63 +       int calcode = ((d2 - d1) * 1000) / 43;
  64 +
  65 +       if ((calcode % 10) >= 5)
  66 +               calcode += 10;
  67 +       calcode = (calcode / 10);
  68 +
  69 +       return calcode;
  70 +}
  71 +
  72 +static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev)
  73 +{
  74 +       u32 savemacsysctrl;
  75 +       u8 saverfb0r1, saverfb0r34, saverfb0r35;
  76 +       u8 saverfb5r4, saverfb5r17, saverfb5r18;
  77 +       u8 saverfb5r19, saverfb5r20;
  78 +       u8 savebbpr22, savebbpr47, savebbpr49;
  79 +       u8 bytevalue = 0;
  80 +       int rcalcode;
  81 +       u8 r_cal_code = 0;
  82 +       char d1 = 0, d2 = 0;
  83 +       u8 rfvalue;
  84 +       u32 MAC_RF_BYPASS0, MAC_RF_CONTROL0, MAC_PWR_PIN_CFG;
  85 +       u32 maccfg;
  86 +
  87 +       saverfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
  88 +       saverfb0r34 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 34);
  89 +       saverfb0r35 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
  90 +       saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
  91 +       saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
  92 +       saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
  93 +       saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
  94 +       saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
  95 +
  96 +       savebbpr22 = rt2800_bbp_read(rt2x00dev, 22);
  97 +       savebbpr47 = rt2800_bbp_read(rt2x00dev, 47);
  98 +       savebbpr49 = rt2800_bbp_read(rt2x00dev, 49);
  99 +
 100 +       savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 101 +       MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
 102 +       MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
 103 +       MAC_PWR_PIN_CFG = rt2800_register_read(rt2x00dev, PWR_PIN_CFG);
 104 +
 105 +       maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 106 +       maccfg &= (~0x04);
 107 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
 108 +
 109 +       if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
 110 +               rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n");
 111 +
 112 +       maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 113 +       maccfg &= (~0x04);
 114 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
 115 +
 116 +       if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
 117 +               rt2x00_warn(rt2x00dev, "Wait MAC Rx Status to MAX !!!\n");
 118 +
 119 +       rfvalue = (MAC_RF_BYPASS0 | 0x3004);
 120 +       rt2800_register_write(rt2x00dev, RF_BYPASS0, rfvalue);
 121 +       rfvalue = (MAC_RF_CONTROL0 | (~0x3002));
 122 +       rt2800_register_write(rt2x00dev, RF_CONTROL0, rfvalue);
 123 +
 124 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x27);
 125 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
 126 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0x83);
 127 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x00);
 128 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
 129 +
 130 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x00);
 131 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, 0x13);
 132 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
 133 +
 134 +       rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x1);
 135 +
 136 +       rt2800_bbp_write(rt2x00dev, 47, 0x04);
 137 +       rt2800_bbp_write(rt2x00dev, 22, 0x80);
 138 +       usleep_range(100, 200);
 139 +       bytevalue = rt2800_bbp_read(rt2x00dev, 49);
 140 +       if (bytevalue > 128)
 141 +               d1 = bytevalue - 256;
 142 +       else
 143 +               d1 = (char)bytevalue;
 144 +       rt2800_bbp_write(rt2x00dev, 22, 0x0);
 145 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01);
 146 +
 147 +       rt2800_bbp_write(rt2x00dev, 22, 0x80);
 148 +       usleep_range(100, 200);
 149 +       bytevalue = rt2800_bbp_read(rt2x00dev, 49);
 150 +       if (bytevalue > 128)
 151 +               d2 = bytevalue - 256;
 152 +       else
 153 +               d2 = (char)bytevalue;
 154 +       rt2800_bbp_write(rt2x00dev, 22, 0x0);
 155 +
 156 +       rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2);
 157 +       if (rcalcode < 0)
 158 +               r_cal_code = 256 + rcalcode;
 159 +       else
 160 +               r_cal_code = (u8)rcalcode;
 161 +
 162 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 7, r_cal_code);
 163 +
 164 +       rt2800_bbp_write(rt2x00dev, 22, 0x0);
 165 +
 166 +       bytevalue = rt2800_bbp_read(rt2x00dev, 21);
 167 +       bytevalue |= 0x1;
 168 +       rt2800_bbp_write(rt2x00dev, 21, bytevalue);
 169 +       bytevalue = rt2800_bbp_read(rt2x00dev, 21);
 170 +       bytevalue &= (~0x1);
 171 +       rt2800_bbp_write(rt2x00dev, 21, bytevalue);
 172 +
 173 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, saverfb0r1);
 174 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, saverfb0r34);
 175 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, saverfb0r35);
 176 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);
 177 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
 178 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
 179 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
 180 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
 181 +
 182 +       rt2800_bbp_write(rt2x00dev, 22, savebbpr22);
 183 +       rt2800_bbp_write(rt2x00dev, 47, savebbpr47);
 184 +       rt2800_bbp_write(rt2x00dev, 49, savebbpr49);
 185 +
 186 +       rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
 187 +       rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
 188 +
 189 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
 190 +       rt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG);
 191 +}
 192 +
 193  static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
 194                                        bool set_bw, bool is_ht40)
 195  {
 196 @@ -9108,6 +9240,7 @@ static void rt2800_init_rfcsr_6352(struc
 197         rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
 198         rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
 199
 200 +       rt2800_r_calibration(rt2x00dev);
 201         rt2800_rf_self_txdc_cal(rt2x00dev);
 202         rt2800_bw_filter_calibration(rt2x00dev, true);
 203         rt2800_bw_filter_calibration(rt2x00dev, false);