mediatek: add support for Adtran SmartRG Bonanza Peak series bonanza-peak
authorDaniel Golle <daniel@makrotopia.org>
Fri, 17 Nov 2023 02:25:09 +0000 (02:25 +0000)
committerDaniel Golle <daniel@makrotopia.org>
Fri, 17 Nov 2023 02:49:35 +0000 (02:49 +0000)
Installation via U-Boot:
0. setup TFTP server with IP 192.168.1.10/24, place initramfs image
renamed to openwrt.XXX where XXX is the internal product number.
1. setenv boot_mode openwrt ; saveenv
2. run boot1
3. run boot2
4. upload sysupgrade.bin via scp to /tmp
5. sysupgrade

TODO:
 * clean up DTS
 * get bluetooth to work
 * proper support for PHY LEDs of GPY211 and MT7531

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
target/linux/mediatek/dts/mt7986a-smartrg-SDG-8612.dts [new file with mode: 0644]
target/linux/mediatek/dts/mt7986a-smartrg-SDG-8614.dts [new file with mode: 0644]
target/linux/mediatek/dts/mt7986a-smartrg-SDG-8622.dts [new file with mode: 0644]
target/linux/mediatek/dts/mt7986a-smartrg-SDG-8632.dts [new file with mode: 0644]
target/linux/mediatek/dts/mt7986a-smartrg-bonanza-peak.dtsi [new file with mode: 0644]
target/linux/mediatek/filogic/base-files/etc/board.d/02_network
target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata
target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh
target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh
target/linux/mediatek/image/filogic.mk

diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8612.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8612.dts
new file mode 100644 (file)
index 0000000..244ba3e
--- /dev/null
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 SmartRG Inc.
+ * Author: Chad Monroe <chad.monroe@smartrg.com>
+ */
+
+#include "mt7986a-smartrg-bonanza-peak.dtsi"
+
+/ {
+       model = "SmartRG SDG-8612";
+       compatible = "smartrg,sdg-8612", "mediatek,mt7986a";
+};
+
+&gmac0 {
+       fixed-link {
+               speed = <2500>;
+               full-duplex;
+               pause;
+       };
+};
+
+&gmac1 {
+       phy-handle = <&phy6>;
+};
+
+&mdio {
+       switch: switch@0 {
+               compatible = "mediatek,mt7531";
+               reg = <31>;
+               reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@1 {
+                               reg = <1>;
+                               label = "lan3";
+                       };
+
+                       port@2 {
+                               reg = <2>;
+                               label = "lan2";
+                       };
+
+                       port@3 {
+                               reg = <3>;
+                               label = "lan1";
+                       };
+
+                       port5: port@5 {
+                               reg = <5>;
+                               label = "lan4";
+
+                               phy-mode = "2500base-x";
+                               phy-handle = <&phy5>;
+                       };
+
+                       port@6 {
+                               reg = <6>;
+                               ethernet = <&gmac0>;
+                               phy-mode = "2500base-x";
+
+                               fixed-link {
+                                       speed = <2500>;
+                                       full-duplex;
+                                       pause;
+                               };
+                       };
+               };
+       };
+};
+
+&wifi {
+       ieee80211-freq-limit = <2400000 2500000>, <5170000 5835000>;
+};
diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8614.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8614.dts
new file mode 100644 (file)
index 0000000..73f8fd5
--- /dev/null
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 SmartRG Inc.
+ * Author: Chad Monroe <chad.monroe@smartrg.com>
+ */
+
+#include "mt7986a-smartrg-bonanza-peak.dtsi"
+
+/ {
+       model = "SmartRG SDG-8614";
+       compatible = "smartrg,sdg-8614", "mediatek,mt7986a";
+
+       leds {
+               mux_sel {
+                       default-state = "off";
+               };
+       };
+
+       /* SFP1 cage (WAN) */
+       i2c_sfp1: i2c-gpio-0 {
+               compatible = "i2c-gpio";
+               sda-gpios = <&pio 62 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+               scl-gpios = <&pio 63 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+               i2c-gpio,delay-us = <2>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+       sfp1: sfp1 {
+               compatible = "sff,sfp";
+               i2c-bus = <&i2c_sfp1>;
+               los-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
+               mod-def0-gpios = <&pio 65 GPIO_ACTIVE_LOW>;
+               rate-select0-gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
+               rate-select1-gpios = <&pio 28 GPIO_ACTIVE_HIGH>;
+               tx-disable-gpios = <&pio 64 GPIO_ACTIVE_HIGH>;
+               tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
+               maximum-power-milliwatt = <3000>;
+       };
+};
+
+&gmac0 {
+       fixed-link {
+               speed = <2500>;
+               full-duplex;
+               pause;
+       };
+};
+
+&gmac1 {
+       sfp = <&sfp1>;
+       managed = "in-band-status";
+};
+
+&mdio {
+       switch: switch@0 {
+               compatible = "mediatek,mt7531";
+               reg = <31>;
+               reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@1 {
+                               reg = <1>;
+                               label = "lan3";
+                       };
+
+                       port@2 {
+                               reg = <2>;
+                               label = "lan2";
+                       };
+
+                       port@3 {
+                               reg = <3>;
+                               label = "lan1";
+                       };
+
+                       port5: port@5 {
+                               reg = <5>;
+                               label = "lan4";
+
+                               phy-mode = "2500base-x";
+                               phy-handle = <&phy5>;
+                       };
+
+                       port@6 {
+                               reg = <6>;
+                               ethernet = <&gmac0>;
+                               phy-mode = "2500base-x";
+
+                               fixed-link {
+                                       speed = <2500>;
+                                       full-duplex;
+                                       pause;
+                               };
+                       };
+               };
+       };
+};
+
+&wifi {
+       ieee80211-freq-limit = <2400000 2500000>, <5170000 5835000>;
+};
diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8622.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8622.dts
new file mode 100644 (file)
index 0000000..2c28c8f
--- /dev/null
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 SmartRG Inc.
+ * Author: Chad Monroe <chad.monroe@smartrg.com>
+ */
+
+#include "mt7986a-smartrg-bonanza-peak.dtsi"
+
+/ {
+       model = "SmartRG SDG-8622";
+       compatible = "smartrg,sdg-8622", "mediatek,mt7986a";
+};
+
+&gmac0 {
+       phy-handle = <&phy5>;
+
+       label = "lan";
+};
+
+&gmac1 {
+       phy-handle = <&phy6>;
+};
+
+&pcie {
+       status = "okay";
+};
+
+&pcie_phy {
+       status = "okay";
+};
+
+&radio0 {
+       ieee80211-freq-limit = <5170000 5330000>;
+};
+
+&wifi {
+       ieee80211-freq-limit = <2400000 2500000>, <5490000 5835000>;
+};
diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8632.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8632.dts
new file mode 100644 (file)
index 0000000..bc92f85
--- /dev/null
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 SmartRG Inc.
+ * Author: Chad Monroe <chad.monroe@smartrg.com>
+ */
+
+#include "mt7986a-smartrg-bonanza-peak.dtsi"
+
+/ {
+       model = "SmartRG SDG-8632";
+       compatible = "smartrg,sdg-8632", "mediatek,mt7986a";
+};
+
+&gmac0 {
+       phy-handle = <&phy5>;
+
+       label = "lan";
+};
+
+&gmac1 {
+       phy-handle = <&phy6>;
+};
+
+&pcie {
+       status = "okay";
+};
+
+&pcie_phy {
+       status = "okay";
+};
+
+&radio0 {
+       ieee80211-freq-limit = <5170000 5835000>;
+};
+
+&wifi {
+       ieee80211-freq-limit = <2400000 2500000>, <5945000 7125000>;
+};
diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-bonanza-peak.dtsi b/target/linux/mediatek/dts/mt7986a-smartrg-bonanza-peak.dtsi
new file mode 100644 (file)
index 0000000..0bdff3e
--- /dev/null
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 SmartRG Inc.
+ * Author: Chad Monroe <chad.monroe@smartrg.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "mt7986a.dtsi"
+
+/ {
+       aliases {
+               serial0 = &uart0;
+               ethernet0 = &gmac0;
+               ethernet1 = &gmac1;
+               led-boot = &sys_status;
+               led-failsafe = &sys_status;
+               led-running = &sys_status;
+               led-upgrade = &sys_status;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+               bootargs = "root=/dev/mmcblk0p5";
+       };
+
+       memory@40000000 {
+               device_type = "memory";
+               reg = <0 0x40000000 0 0x40000000>;
+       };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               /delete-node/ramoops@42ff0000;
+
+               bootdata_reserved: bootdata@45000000 {
+                       no-map;
+                       reg = <0x0 0x45000000 0x0 0x00001000>;
+               };
+
+               ramoops_reserved: ramoops@45001000 {
+                       no-map;
+                       compatible = "ramoops";
+                       reg = <0x0 0x45001000 0x0 0x00140000>;
+                       ftrace-size = <0x20000>;
+                       record-size = <0x20000>;
+                       console-size = <0x20000>;
+                       pmsg-size = <0x80000>;
+               };
+       };
+
+       bootdata {
+               compatible = "bootdata";
+               memory-region = <&bootdata_reserved>;
+       };
+
+       reg_1p8v: regulator-1p8v {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-1.8V";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       reg_3p3v: regulator-3p3v {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       reg_5v: regulator-5v {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-5V";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       fan: pwm-fan {
+               compatible = "pwm-fan";
+               #cooling-cells = <2>;
+               pwms = <&pwm 1 40000 0>;
+
+               /**
+                * set fan speed
+                *
+                * 0 = off
+                * 51 = 20% duty cycle (minimum supported)
+                * 61 = 24% duty cycle (2020 RPM)
+                * 77 = 30% duty cycle (3000 RPM)
+                * 102 = 40% duty cycle (3600 RPM)
+                * 255 = 100% duty cycle
+                */
+               cooling-levels = <51 61 77 102>;
+
+               interrupt-parent = <&pio>;
+               interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+               pulses-per-revolution = <2>;
+
+               status = "okay";
+       };
+
+       keys {
+               compatible = "gpio-keys";
+               pinctrl-names = "default";
+               pinctrl-0 = <&button_pins>;
+
+               reset {
+                       label = "reset";
+                       linux,code = <KEY_RESTART>;
+                       gpios = <&pio 17 GPIO_ACTIVE_LOW>;
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               mux_sel {
+                       label = "mux_sel";
+                       gpios = <&pio 23 GPIO_ACTIVE_LOW>;
+                       default-state = "on";
+               };
+
+               mux_oe {
+                       label = "mux_oe";
+                       gpios = <&pio 24 GPIO_ACTIVE_LOW>;
+                       default-state = "on";
+               };
+
+               sfp_red {
+                       label = "sfp_red";
+                       gpios = <&pio 16 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+
+               sfp_green {
+                       label = "sfp_green";
+                       gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
+                       default-state = "off";
+               };
+       };
+};
+
+&cpu_thermal {
+       cooling-maps {
+               cpu-active-high {
+                       /* active: set fan to cooling level 3 */
+                       cooling-device = <&fan 3 3>;
+                       trip = <&cpu_trip_active_high>;
+               };
+
+               cpu-active-medium {
+                       /* active: set fan to cooling level 2 */
+                       cooling-device = <&fan 2 2>;
+                       trip = <&cpu_trip_active_medium>;
+               };
+
+               cpu-active-low {
+                       /* active: set fan to cooling level 1 */
+                       cooling-device = <&fan 1 1>;
+                       trip = <&cpu_trip_active_low>;
+               };
+
+               cpu-active-silent {
+                       /* active: set fan to cooling level 0 */
+                       cooling-device = <&fan 0 0>;
+                       trip = <&cpu_trip_active_silent>;
+               };
+       };
+
+       trips {
+               cpu_trip_active_high: active-high {
+                       temperature = <110000>;
+                       hysteresis = <2000>;
+                       type = "active";
+               };
+
+               cpu_trip_active_medium: active-medium {
+                       temperature = <80000>;
+                       hysteresis = <2000>;
+                       type = "active";
+               };
+
+               cpu_trip_active_low: active-low {
+                       temperature = <60000>;
+                       hysteresis = <2000>;
+                       type = "active";
+               };
+
+               cpu_trip_active_silent: active-silent {
+                       temperature = <40000>;
+                       hysteresis = <2000>;
+                       type = "active";
+               };
+       };
+};
+
+&crypto {
+       status = "okay";
+};
+
+&eth {
+       status = "okay";
+
+       gmac0: mac@0 {
+               compatible = "mediatek,eth-mac";
+               reg = <0>;
+
+               phy-mode = "2500base-x";
+       };
+
+       gmac1: mac@1 {
+               label = "wan";
+
+               compatible = "mediatek,eth-mac";
+               reg = <1>;
+
+               phy-mode = "2500base-x";
+       };
+
+       mdio: mdio-bus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+};
+
+&mdio {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+       reset-delay-us = <1500000>;
+       reset-post-delay-us = <1000000>;
+
+       phy5: ethernet-phy@5 {
+               /* GPY211 */
+               compatible = "maxlinear,gpy211", "ethernet-phy-ieee802.3-c45";
+               reg = <5>;
+
+               mxl,led-drive-vdd;
+               mxl,led-config = <0x30 0x40 0x80 0x0>;
+       };
+
+       phy6: ethernet-phy@6 {
+               /* GPY211 */
+               compatible = "maxlinear,gpy211", "ethernet-phy-ieee802.3-c45";
+               reg = <6>;
+
+               mxl,led-drive-vdd;
+               mxl,led-config = <0x30 0x40 0x80 0x0>;
+       };
+};
+
+&crypto {
+       status = "okay";
+};
+
+&mmc0 {
+       pinctrl-names = "default", "state_uhs";
+       pinctrl-0 = <&mmc0_pins_default>;
+       pinctrl-1 = <&mmc0_pins_uhs>;
+       bus-width = <8>;
+       max-frequency = <200000000>;
+       cap-mmc-highspeed;
+       mmc-hs200-1_8v;
+       mmc-hs400-1_8v;
+       hs400-ds-delay = <0x14014>;
+       vmmc-supply = <&reg_3p3v>;
+       vqmmc-supply = <&reg_1p8v>;
+       non-removable;
+       no-sd;
+       no-sdio;
+       status = "okay";
+};
+
+&pcie {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie_pins>;
+       status = "disabled";
+
+       slot0: pcie@0,0 {
+               reg = <0x0000 0 0 0 0>;
+
+               radio0: mt7915@0,0 {
+                       reg = <0x0000 0 0 0 0>;
+               };
+       };
+};
+
+&pcie_phy {
+       status = "disabled";
+};
+
+&wifi {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&wf_2g_5g_pins>;
+};
+
+&pio {
+       mmc0_pins_default: mmc0-pins {
+               mux {
+                       function = "emmc";
+                       groups = "emmc_51";
+               };
+               conf-cmd-dat {
+                       pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+                              "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+                              "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+                       input-enable;
+                       drive-strength = <4>;
+                       mediatek,pull-up-adv = <1>;     /* pull-up 10K */
+               };
+               conf-clk {
+                       pins = "EMMC_CK";
+                       drive-strength = <6>;
+                       mediatek,pull-down-adv = <2>;   /* pull-down 50K */
+               };
+               conf-ds {
+                       pins = "EMMC_DSL";
+                       mediatek,pull-down-adv = <2>;   /* pull-down 50K */
+               };
+               conf-rst {
+                       pins = "EMMC_RSTB";
+                       drive-strength = <4>;
+                       mediatek,pull-up-adv = <1>;     /* pull-up 10K */
+               };
+       };
+
+       mmc0_pins_uhs: mmc0-uhs-pins {
+               mux {
+                       function = "emmc";
+                       groups = "emmc_51";
+               };
+               conf-cmd-dat {
+                       pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+                              "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+                              "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+                       input-enable;
+                       drive-strength = <4>;
+                       mediatek,pull-up-adv = <1>;     /* pull-up 10K */
+               };
+               conf-clk {
+                       pins = "EMMC_CK";
+                       drive-strength = <6>;
+                       mediatek,pull-down-adv = <2>;   /* pull-down 50K */
+               };
+               conf-ds {
+                       pins = "EMMC_DSL";
+                       mediatek,pull-down-adv = <2>;   /* pull-down 50K */
+               };
+               conf-rst {
+                       pins = "EMMC_RSTB";
+                       drive-strength = <4>;
+                       mediatek,pull-up-adv = <1>;     /* pull-up 10K */
+               };
+       };
+
+       pcie_pins: pcie-pins {
+               mux {
+                       function = "pcie";
+                       groups = "pcie_clk", "pcie_pereset";
+               };
+       };
+
+       button_pins: button-pins {
+               pins = "GPIO_12";
+               mediatek,pull-down-adv = <0>; /* bias-disable */
+       };
+
+       uart1_pins: uart1-pins {
+               mux {
+                       function = "uart";
+                       groups = "uart1_2_rx_tx", "uart1_2_cts_rts";
+               };
+       };
+
+       i2c0_pins: i2c0-pins {
+               mux {
+                       function = "i2c";
+                       groups = "i2c";
+               };
+       };
+
+       pwm_pins: pwm-pins {
+               mux {
+                       function = "pwm";
+                       groups = "pwm0", "pwm1_0";
+               };
+       };
+
+       wf_2g_5g_pins: wf-2g-5g-pins {
+               mux {
+                       function = "wifi";
+                       groups = "wf_2g", "wf_5g";
+               };
+               conf {
+                       pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+                              "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+                              "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+                              "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+                              "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+                              "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+                              "WF1_TOP_CLK", "WF1_TOP_DATA";
+                       drive-strength = <4>;
+               };
+       };
+};
+
+&ssusb {
+       vusb33-supply = <&reg_3p3v>;
+       vbus-supply = <&reg_5v>;
+       status = "okay";
+};
+
+&trng {
+       status = "okay";
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart1_pins>;
+       status = "okay";
+
+       /* DA14531MOD Bluetooth */
+       bluetooth {
+               compatible = "renesas,DA14531";
+               reset-gpios = <&pio 27 GPIO_ACTIVE_LOW>;
+       };
+};
+
+&usb_phy {
+       status = "okay";
+};
+
+&i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c0_pins>;
+       status = "okay";
+
+       system-leds {
+               compatible = "srg,sysled";
+               reg = <0x30>;
+
+               system_red {
+                       label = "red";
+                       reg = <1>;
+               };
+
+               sys_status: system_green {
+                       label = "green";
+                       reg = <2>;
+                       linux,default-trigger = "timer";
+               };
+
+               system_blue {
+                       label = "blue";
+                       reg = <3>;
+               };
+
+               system_white {
+                       label = "white";
+                       reg = <4>;
+               };
+       };
+};
+
+&pwm {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pwm_pins>;
+       status = "okay";
+};
+
+&watchdog {
+       interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+       status = "okay";
+};
index aad1d67ff6fde57a85c5ded70065e145d8b90e4a..e16dd9ac72d06adfc810d0b830f5f249edd627dd 100644 (file)
@@ -52,6 +52,10 @@ mediatek_setup_interfaces()
        qihoo,360t7)
                ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" wan
                ;;
+       smartrg,sdg-8622|\
+       smartrg,sdg-8632)
+               ucidef_set_interfaces_lan_wan lan wan
+               ;;
        glinet,gl-mt6000|\
        tplink,tl-xdr4288|\
        tplink,tl-xdr6088)
@@ -128,6 +132,14 @@ mediatek_setup_macs()
                wan_mac=$(macaddr_add "$lan_mac" 1)
                label_mac=$wan_mac
                ;;
+       smartrg,sdg-8612|\
+       smartrg,sdg-8614|\
+       smartrg,sdg-8622|\
+       smartrg,sdg-8632)
+               label_mac=$(mmc_get_mac_ascii mfginfo MFG_MAC)
+               wan_mac=$label_mac
+               lan_mac=$(macaddr_add "$label_mac" 1)
+               ;;
        xiaomi,mi-router-wr30u-112m-nmbm|\
        xiaomi,mi-router-wr30u-stock|\
        xiaomi,mi-router-wr30u-ubootmod|\
index 4d9833f66cfb0a8e004458e54ca53ff1647a6065..7dc57d535d2a09885e1b30749f4a42561f4138b7 100644 (file)
@@ -7,11 +7,20 @@
 board=$(board_name)
 
 case "$FIRMWARE" in
+"mediatek/mt7915_eeprom.bin")
+       case "$board" in
+       smartrg,sdg-8622)
+               caldata_extract_mmc "factory" 0xa0000 0x1000
+               ;;
+       esac
+       ;;
 "mediatek/mt7916_eeprom.bin")
        case "$board" in
        acer,predator-w6)
                caldata_extract_mmc "factory" 0xA0000 0x1000
                ;;
+       smartrg,sdg-8632)
+               caldata_extract_mmc "factory" 0xa0000 0x1000
        esac
        ;;
 "mediatek/mt7981_eeprom_mt7976_dbdc.bin")
@@ -34,6 +43,12 @@ case "$FIRMWARE" in
                ln -sf /tmp/tp_data/MT7986_EEPROM.bin \
                        /lib/firmware/$FIRMWARE
                ;;
+       smartrg,sdg-8612|\
+       smartrg,sdg-8614|\
+       smartrg,sdg-8622|\
+       smartrg,sdg-8632)
+               caldata_extract_mmc "factory" 0x0 0x1000
+               ;;
        esac
        ;;
 "mediatek/mt7986_eeprom_mt7976.bin")
index 395cc0f2dc546616e1b0e51149eff3e2b03322de..209e251029072b44855805404adf4baa124267ad 100644 (file)
@@ -85,6 +85,15 @@ case "$board" in
                [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
                [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
                ;;
+       smartrg,sdg-8612|\
+       smartrg,sdg-8614|\
+       smartrg,sdg-8622|\
+       smartrg,sdg-8632)
+               addr=$(mmc_get_mac_ascii mfginfo MFG_MAC)
+               [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
+               [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
+               [ "$PHYNBR" = "2" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress
+               ;;
        tplink,tl-xdr4288|\
        tplink,tl-xdr6086|\
        tplink,tl-xdr6088)
index d770b1364322afd0c23a17f4ae835e192acaa43d..37b5be133439c350e5609014097612d17330feba 100644 (file)
@@ -21,6 +21,23 @@ preinit_set_mac_address() {
                addr=$(get_mac_binary "/tmp/tp_data/default-mac" 0)
                ip link set dev eth1 address "$(macaddr_add $addr 1)"
                ;;
+       smartrg,sdg-8612|\
+       smartrg,sdg-8614)
+               addr=$(mmc_get_mac_ascii mfginfo MFG_MAC)
+               lan_addr=$(macaddr_add $addr 1)
+               ip link set dev wan address "$addr"
+               ip link set dev eth0 address "$lan_addr"
+               ip link set dev lan1 address "$lan_addr"
+               ip link set dev lan2 address "$lan_addr"
+               ip link set dev lan3 address "$lan_addr"
+               ip link set dev lan4 address "$lan_addr"
+               ;;
+       smartrg,sdg-8622|\
+       smartrg,sdg-8632)
+               addr=$(mmc_get_mac_ascii mfginfo MFG_MAC)
+               ip link set dev wan address "$addr"
+               ip link set dev lan address "$(macaddr_add $addr 1)"
+               ;;
        *)
                ;;
        esac
index b7b9d6599325614e6c629e8598927e54af0a70db..7833abe5af4cf5c477e850aba80bd5fe094d9540 100755 (executable)
@@ -51,7 +51,11 @@ platform_do_upgrade() {
        local board=$(board_name)
 
        case "$board" in
-       acer,predator-w6)
+       acer,predator-w6|\
+       smartrg,sdg-8612|\
+       smartrg,sdg-8614|\
+       smartrg,sdg-8622|\
+       smartrg,sdg-8632)
                CI_KERNPART="kernel"
                CI_ROOTPART="rootfs"
                emmc_do_upgrade "$1"
index 0ef3e945756895dd17bf784c0059e31943626a98..b37b2bbb21b4be27ed2abd110c3fde5be402e756 100644 (file)
@@ -105,6 +105,42 @@ define Build/cetron-header
        rm $@.tmp
 endef
 
+define Device/adtran_smartrg
+  DEVICE_VENDOR := Adtran
+  DEVICE_DTS_DIR := ../dts
+  DEVICE_PACKAGES := da14531-firmware kmod-bluetooth kmod-hwmon-pwmfan \
+                    kmod-mt7915-firmware kmod-mt7986-firmware mt7986-wo-firmware
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+
+define Device/smartrg_sdg-8612
+$(call Device/adtran_smartrg)
+  DEVICE_MODEL := SDG-8612
+  DEVICE_DTS := mt7986a-smartrg-SDG-8612
+endef
+TARGET_DEVICES += smartrg_sdg-8612
+
+define Device/smartrg_sdg-8614
+$(call Device/adtran_smartrg)
+  DEVICE_MODEL := SDG-8614
+  DEVICE_DTS := mt7986a-smartrg-SDG-8614
+endef
+TARGET_DEVICES += smartrg_sdg-8614
+
+define Device/smartrg_sdg-8622
+$(call Device/adtran_smartrg)
+  DEVICE_MODEL := SDG-8622
+  DEVICE_DTS := mt7986a-smartrg-SDG-8622
+endef
+TARGET_DEVICES += smartrg_sdg-8622
+
+define Device/smartrg_sdg-8632
+$(call Device/adtran_smartrg)
+  DEVICE_MODEL := SDG-8632
+  DEVICE_DTS := mt7986a-smartrg-SDG-8632
+endef
+TARGET_DEVICES += smartrg_sdg-8632
+
 define Device/asus_tuf-ax4200
   DEVICE_VENDOR := ASUS
   DEVICE_MODEL := TUF-AX4200