2048e22f2e5abaaa86cee9ad0bf33f05d217a026
[openwrt/staging/dangole.git] / target / linux / realtek / patches-5.15 / 704-include-linux-add-phy-hsgmii-mode.patch
1 From 9d9bf16aa8d966834ac1280f96c37d22552c33d1 Mon Sep 17 00:00:00 2001
2 From: Birger Koblitz <git@birger-koblitz.de>
3 Date: Wed, 8 Sep 2021 16:13:18 +0200
4 Subject: phy: Add PHY hsgmii mode
5
6 This adds RTL93xx-specific MAC configuration routines that allow also configuration
7 of 10GBit links for phylink. There is support for the Realtek-specific HISGMI
8 protocol.
9
10 Submitted-by: Birger Koblitz <git@birger-koblitz.de>
11 ---
12 drivers/net/phy/phylink.c | 2 ++
13 include/linux/phy.h | 3 +++
14 2 file changed, 5 insertions(+)
15
16 --- a/drivers/net/phy/phylink.c
17 +++ b/drivers/net/phy/phylink.c
18 @@ -408,6 +408,7 @@ void phylink_get_linkmodes(unsigned long
19
20 case PHY_INTERFACE_MODE_XGMII:
21 case PHY_INTERFACE_MODE_RXAUI:
22 + case PHY_INTERFACE_MODE_HSGMII:
23 case PHY_INTERFACE_MODE_XAUI:
24 case PHY_INTERFACE_MODE_10GBASER:
25 case PHY_INTERFACE_MODE_10GKR:
26 @@ -662,6 +663,7 @@ static int phylink_parse_mode(struct phy
27 fallthrough;
28 case PHY_INTERFACE_MODE_USXGMII:
29 case PHY_INTERFACE_MODE_10GKR:
30 + case PHY_INTERFACE_MODE_HSGMII:
31 case PHY_INTERFACE_MODE_10GBASER:
32 phylink_set(pl->supported, 10baseT_Half);
33 phylink_set(pl->supported, 10baseT_Full);
34 --- a/include/linux/phy.h
35 +++ b/include/linux/phy.h
36 @@ -139,6 +139,7 @@ typedef enum {
37 PHY_INTERFACE_MODE_XGMII,
38 PHY_INTERFACE_MODE_XLGMII,
39 PHY_INTERFACE_MODE_MOCA,
40 + PHY_INTERFACE_MODE_HSGMII,
41 PHY_INTERFACE_MODE_QSGMII,
42 PHY_INTERFACE_MODE_TRGMII,
43 PHY_INTERFACE_MODE_100BASEX,
44 @@ -244,6 +245,8 @@ static inline const char *phy_modes(phy_
45 return "xlgmii";
46 case PHY_INTERFACE_MODE_MOCA:
47 return "moca";
48 + case PHY_INTERFACE_MODE_HSGMII:
49 + return "hsgmii";
50 case PHY_INTERFACE_MODE_QSGMII:
51 return "qsgmii";
52 case PHY_INTERFACE_MODE_TRGMII: