target/linux/mediatek/patches-5.15/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch

   1 From d35469096915f2551ed1d26da1ab12ff500fc963 Mon Sep 17 00:00:00 2001
   2 From: Maso Huang <maso.huang@mediatek.com>
   3 Date: Thu, 17 Aug 2023 18:13:33 +0800
   4 Subject: [PATCH 1/9] ASoC: mediatek: mt7986: add common header
   5
   6 Add header files for register definition and structure.
   7
   8 Signed-off-by: Maso Huang <maso.huang@mediatek.com>
   9 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  10 Link: https://lore.kernel.org/r/20230817101338.18782-2-maso.huang@mediatek.com
  11 Signed-off-by: Mark Brown <broonie@kernel.org>
  12 ---
  13  sound/soc/mediatek/mt7986/mt7986-afe-common.h |  49 +++++
  14  sound/soc/mediatek/mt7986/mt7986-reg.h        | 196 ++++++++++++++++++
  15  2 files changed, 245 insertions(+)
  16  create mode 100644 sound/soc/mediatek/mt7986/mt7986-afe-common.h
  17  create mode 100644 sound/soc/mediatek/mt7986/mt7986-reg.h
  18
  19 --- /dev/null
  20 +++ b/sound/soc/mediatek/mt7986/mt7986-afe-common.h
  21 @@ -0,0 +1,49 @@
  22 +/* SPDX-License-Identifier: GPL-2.0 */
  23 +/*
  24 + * mt7986-afe-common.h  --  MediaTek 7986 audio driver definitions
  25 + *
  26 + * Copyright (c) 2023 MediaTek Inc.
  27 + * Authors: Vic Wu <vic.wu@mediatek.com>
  28 + *          Maso Huang <maso.huang@mediatek.com>
  29 + */
  30 +
  31 +#ifndef _MT_7986_AFE_COMMON_H_
  32 +#define _MT_7986_AFE_COMMON_H_
  33 +
  34 +#include <sound/soc.h>
  35 +#include <linux/clk.h>
  36 +#include <linux/list.h>
  37 +#include <linux/regmap.h>
  38 +#include "../common/mtk-base-afe.h"
  39 +
  40 +enum {
  41 +       MT7986_MEMIF_DL1,
  42 +       MT7986_MEMIF_VUL12,
  43 +       MT7986_MEMIF_NUM,
  44 +       MT7986_DAI_ETDM = MT7986_MEMIF_NUM,
  45 +       MT7986_DAI_NUM,
  46 +};
  47 +
  48 +enum {
  49 +       MT7986_IRQ_0,
  50 +       MT7986_IRQ_1,
  51 +       MT7986_IRQ_2,
  52 +       MT7986_IRQ_NUM,
  53 +};
  54 +
  55 +struct mt7986_afe_private {
  56 +       struct clk_bulk_data *clks;
  57 +       int num_clks;
  58 +
  59 +       int pm_runtime_bypass_reg_ctl;
  60 +
  61 +       /* dai */
  62 +       void *dai_priv[MT7986_DAI_NUM];
  63 +};
  64 +
  65 +unsigned int mt7986_afe_rate_transform(struct device *dev,
  66 +                                      unsigned int rate);
  67 +
  68 +/* dai register */
  69 +int mt7986_dai_etdm_register(struct mtk_base_afe *afe);
  70 +#endif
  71 --- /dev/null
  72 +++ b/sound/soc/mediatek/mt7986/mt7986-reg.h
  73 @@ -0,0 +1,196 @@
  74 +/* SPDX-License-Identifier: GPL-2.0 */
  75 +/*
  76 + * mt7986-reg.h  --  MediaTek 7986 audio driver reg definition
  77 + *
  78 + * Copyright (c) 2023 MediaTek Inc.
  79 + * Authors: Vic Wu <vic.wu@mediatek.com>
  80 + *          Maso Huang <maso.huang@mediatek.com>
  81 + */
  82 +
  83 +#ifndef _MT7986_REG_H_
  84 +#define _MT7986_REG_H_
  85 +
  86 +#define AUDIO_TOP_CON2                  0x0008
  87 +#define AUDIO_TOP_CON4                  0x0010
  88 +#define AUDIO_ENGEN_CON0                0x0014
  89 +#define AFE_IRQ_MCU_EN                  0x0100
  90 +#define AFE_IRQ_MCU_STATUS              0x0120
  91 +#define AFE_IRQ_MCU_CLR                 0x0128
  92 +#define AFE_IRQ0_MCU_CFG0               0x0140
  93 +#define AFE_IRQ0_MCU_CFG1               0x0144
  94 +#define AFE_IRQ1_MCU_CFG0               0x0148
  95 +#define AFE_IRQ1_MCU_CFG1               0x014c
  96 +#define AFE_IRQ2_MCU_CFG0               0x0150
  97 +#define AFE_IRQ2_MCU_CFG1               0x0154
  98 +#define ETDM_IN5_CON0                   0x13f0
  99 +#define ETDM_IN5_CON1                   0x13f4
 100 +#define ETDM_IN5_CON2                   0x13f8
 101 +#define ETDM_IN5_CON3                   0x13fc
 102 +#define ETDM_IN5_CON4                   0x1400
 103 +#define ETDM_OUT5_CON0                  0x1570
 104 +#define ETDM_OUT5_CON4                  0x1580
 105 +#define ETDM_OUT5_CON5                  0x1584
 106 +#define ETDM_4_7_COWORK_CON0            0x15e0
 107 +#define ETDM_4_7_COWORK_CON1            0x15e4
 108 +#define AFE_CONN018_1                   0x1b44
 109 +#define AFE_CONN018_4                   0x1b50
 110 +#define AFE_CONN019_1                   0x1b64
 111 +#define AFE_CONN019_4                   0x1b70
 112 +#define AFE_CONN124_1                   0x2884
 113 +#define AFE_CONN124_4                   0x2890
 114 +#define AFE_CONN125_1                   0x28a4
 115 +#define AFE_CONN125_4                   0x28b0
 116 +#define AFE_CONN_RS_0                   0x3920
 117 +#define AFE_CONN_RS_3                   0x392c
 118 +#define AFE_CONN_16BIT_0                0x3960
 119 +#define AFE_CONN_16BIT_3                0x396c
 120 +#define AFE_CONN_24BIT_0                0x3980
 121 +#define AFE_CONN_24BIT_3                0x398c
 122 +#define AFE_MEMIF_CON0                  0x3d98
 123 +#define AFE_MEMIF_RD_MON                0x3da0
 124 +#define AFE_MEMIF_WR_MON                0x3da4
 125 +#define AFE_DL0_BASE_MSB                0x3e40
 126 +#define AFE_DL0_BASE                    0x3e44
 127 +#define AFE_DL0_CUR_MSB                 0x3e48
 128 +#define AFE_DL0_CUR                     0x3e4c
 129 +#define AFE_DL0_END_MSB                 0x3e50
 130 +#define AFE_DL0_END                     0x3e54
 131 +#define AFE_DL0_RCH_MON                 0x3e58
 132 +#define AFE_DL0_LCH_MON                 0x3e5c
 133 +#define AFE_DL0_CON0                    0x3e60
 134 +#define AFE_VUL0_BASE_MSB               0x4220
 135 +#define AFE_VUL0_BASE                   0x4224
 136 +#define AFE_VUL0_CUR_MSB                0x4228
 137 +#define AFE_VUL0_CUR                    0x422c
 138 +#define AFE_VUL0_END_MSB                0x4230
 139 +#define AFE_VUL0_END                    0x4234
 140 +#define AFE_VUL0_CON0                   0x4238
 141 +
 142 +#define AFE_MAX_REGISTER AFE_VUL0_CON0
 143 +#define AFE_IRQ_STATUS_BITS             0x7
 144 +#define AFE_IRQ_CNT_SHIFT               0
 145 +#define AFE_IRQ_CNT_MASK               0xffffff
 146 +
 147 +/* AUDIO_TOP_CON2 */
 148 +#define CLK_OUT5_PDN                    BIT(14)
 149 +#define CLK_OUT5_PDN_MASK               BIT(14)
 150 +#define CLK_IN5_PDN                     BIT(7)
 151 +#define CLK_IN5_PDN_MASK                BIT(7)
 152 +
 153 +/* AUDIO_TOP_CON4 */
 154 +#define PDN_APLL_TUNER2                 BIT(12)
 155 +#define PDN_APLL_TUNER2_MASK            BIT(12)
 156 +
 157 +/* AUDIO_ENGEN_CON0 */
 158 +#define AUD_APLL2_EN                    BIT(3)
 159 +#define AUD_APLL2_EN_MASK               BIT(3)
 160 +#define AUD_26M_EN                      BIT(0)
 161 +#define AUD_26M_EN_MASK                 BIT(0)
 162 +
 163 +/* AFE_DL0_CON0 */
 164 +#define DL0_ON_SFT                      28
 165 +#define DL0_ON_MASK                     0x1
 166 +#define DL0_ON_MASK_SFT                 BIT(28)
 167 +#define DL0_MINLEN_SFT                  20
 168 +#define DL0_MINLEN_MASK                 0xf
 169 +#define DL0_MINLEN_MASK_SFT             (0xf << 20)
 170 +#define DL0_MODE_SFT                    8
 171 +#define DL0_MODE_MASK                   0x1f
 172 +#define DL0_MODE_MASK_SFT               (0x1f << 8)
 173 +#define DL0_PBUF_SIZE_SFT               5
 174 +#define DL0_PBUF_SIZE_MASK              0x3
 175 +#define DL0_PBUF_SIZE_MASK_SFT          (0x3 << 5)
 176 +#define DL0_MONO_SFT                    4
 177 +#define DL0_MONO_MASK                   0x1
 178 +#define DL0_MONO_MASK_SFT               BIT(4)
 179 +#define DL0_HALIGN_SFT                  2
 180 +#define DL0_HALIGN_MASK                 0x1
 181 +#define DL0_HALIGN_MASK_SFT             BIT(2)
 182 +#define DL0_HD_MODE_SFT                 0
 183 +#define DL0_HD_MODE_MASK                0x3
 184 +#define DL0_HD_MODE_MASK_SFT            (0x3 << 0)
 185 +
 186 +/* AFE_VUL0_CON0 */
 187 +#define VUL0_ON_SFT                     28
 188 +#define VUL0_ON_MASK                    0x1
 189 +#define VUL0_ON_MASK_SFT                BIT(28)
 190 +#define VUL0_MODE_SFT                   8
 191 +#define VUL0_MODE_MASK                  0x1f
 192 +#define VUL0_MODE_MASK_SFT              (0x1f << 8)
 193 +#define VUL0_MONO_SFT                   4
 194 +#define VUL0_MONO_MASK                  0x1
 195 +#define VUL0_MONO_MASK_SFT              BIT(4)
 196 +#define VUL0_HALIGN_SFT                 2
 197 +#define VUL0_HALIGN_MASK                0x1
 198 +#define VUL0_HALIGN_MASK_SFT            BIT(2)
 199 +#define VUL0_HD_MODE_SFT                0
 200 +#define VUL0_HD_MODE_MASK               0x3
 201 +#define VUL0_HD_MODE_MASK_SFT           (0x3 << 0)
 202 +
 203 +/* AFE_IRQ_MCU_CON */
 204 +#define IRQ_MCU_MODE_SFT                4
 205 +#define IRQ_MCU_MODE_MASK               0x1f
 206 +#define IRQ_MCU_MODE_MASK_SFT           (0x1f << 4)
 207 +#define IRQ_MCU_ON_SFT                  0
 208 +#define IRQ_MCU_ON_MASK                 0x1
 209 +#define IRQ_MCU_ON_MASK_SFT             BIT(0)
 210 +#define IRQ0_MCU_CLR_SFT                0
 211 +#define IRQ0_MCU_CLR_MASK               0x1
 212 +#define IRQ0_MCU_CLR_MASK_SFT           BIT(0)
 213 +#define IRQ1_MCU_CLR_SFT                1
 214 +#define IRQ1_MCU_CLR_MASK               0x1
 215 +#define IRQ1_MCU_CLR_MASK_SFT           BIT(1)
 216 +#define IRQ2_MCU_CLR_SFT                2
 217 +#define IRQ2_MCU_CLR_MASK               0x1
 218 +#define IRQ2_MCU_CLR_MASK_SFT           BIT(2)
 219 +
 220 +/* ETDM_IN5_CON2 */
 221 +#define IN_CLK_SRC(x)                   ((x) << 10)
 222 +#define IN_CLK_SRC_SFT                  10
 223 +#define IN_CLK_SRC_MASK                 GENMASK(12, 10)
 224 +
 225 +/* ETDM_IN5_CON3 */
 226 +#define IN_SEL_FS(x)                    ((x) << 26)
 227 +#define IN_SEL_FS_SFT                   26
 228 +#define IN_SEL_FS_MASK                  GENMASK(30, 26)
 229 +
 230 +/* ETDM_IN5_CON4 */
 231 +#define IN_RELATCH(x)                   ((x) << 20)
 232 +#define IN_RELATCH_SFT                  20
 233 +#define IN_RELATCH_MASK                 GENMASK(24, 20)
 234 +#define IN_CLK_INV                      BIT(18)
 235 +#define IN_CLK_INV_MASK                 BIT(18)
 236 +
 237 +/* ETDM_IN5_CON0 & ETDM_OUT5_CON0 */
 238 +#define RELATCH_SRC_MASK                GENMASK(30, 28)
 239 +#define ETDM_CH_NUM_MASK                GENMASK(27, 23)
 240 +#define ETDM_WRD_LEN_MASK               GENMASK(20, 16)
 241 +#define ETDM_BIT_LEN_MASK               GENMASK(15, 11)
 242 +#define ETDM_FMT_MASK                   GENMASK(8, 6)
 243 +#define ETDM_SYNC                       BIT(1)
 244 +#define ETDM_SYNC_MASK                  BIT(1)
 245 +#define ETDM_EN                         BIT(0)
 246 +#define ETDM_EN_MASK                    BIT(0)
 247 +
 248 +/* ETDM_OUT5_CON4 */
 249 +#define OUT_RELATCH(x)                  ((x) << 24)
 250 +#define OUT_RELATCH_SFT                 24
 251 +#define OUT_RELATCH_MASK                GENMASK(28, 24)
 252 +#define OUT_CLK_SRC(x)                  ((x) << 6)
 253 +#define OUT_CLK_SRC_SFT                 6
 254 +#define OUT_CLK_SRC_MASK                GENMASK(8, 6)
 255 +#define OUT_SEL_FS(x)                   (x)
 256 +#define OUT_SEL_FS_SFT                  0
 257 +#define OUT_SEL_FS_MASK                 GENMASK(4, 0)
 258 +
 259 +/* ETDM_OUT5_CON5 */
 260 +#define ETDM_CLK_DIV                    BIT(12)
 261 +#define ETDM_CLK_DIV_MASK               BIT(12)
 262 +#define OUT_CLK_INV                     BIT(9)
 263 +#define OUT_CLK_INV_MASK                BIT(9)
 264 +
 265 +/* ETDM_4_7_COWORK_CON0 */
 266 +#define OUT_SEL(x)                      ((x) << 12)
 267 +#define OUT_SEL_SFT                     12
 268 +#define OUT_SEL_MASK                    GENMASK(15, 12)
 269 +#endif