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mediatek: switch to pending XFI 10G Ethernet drivers
[openwrt/staging/dangole.git] / target / linux / mediatek / files-6.1 / arch / arm64 / boot / dts / mediatek / mt7988a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/pinctrl/mt65xx.h>
13 #include <dt-bindings/reset/mediatek,mt7988-resets.h>
14 #include <dt-bindings/thermal/thermal.h>
15
16 /* TOPRGU resets */
17 #define MT7988_TOPRGU_SGMII0_GRST 1
18 #define MT7988_TOPRGU_SGMII1_GRST 2
19 #define MT7988_TOPRGU_XFI0_GRST 12
20 #define MT7988_TOPRGU_XFI1_GRST 13
21 #define MT7988_TOPRGU_XFI_PEXTP0_GRST 14
22 #define MT7988_TOPRGU_XFI_PEXTP1_GRST 15
23 #define MT7988_TOPRGU_XFI_PLL_GRST 16
24
25 / {
26 compatible = "mediatek,mt7988";
27 interrupt-parent = <&gic>;
28 #address-cells = <2>;
29 #size-cells = <2>;
30
31 cci: cci {
32 compatible = "mediatek,mt7988-cci",
33 "mediatek,mt8183-cci";
34 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
35 <&topckgen CLK_TOP_XTAL>;
36 clock-names = "cci", "intermediate";
37 operating-points-v2 = <&cci_opp>;
38 };
39
40 cpus {
41 #address-cells = <1>;
42 #size-cells = <0>;
43 cpu0: cpu@0 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a73";
46 enable-method = "psci";
47 reg = <0x0>;
48 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
49 <&topckgen CLK_TOP_XTAL>;
50 clock-names = "cpu", "intermediate";
51 operating-points-v2 = <&cluster0_opp>;
52 mediatek,cci = <&cci>;
53 };
54
55 cpu1: cpu@1 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a73";
58 enable-method = "psci";
59 reg = <0x1>;
60 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
61 <&topckgen CLK_TOP_XTAL>;
62 clock-names = "cpu", "intermediate";
63 operating-points-v2 = <&cluster0_opp>;
64 mediatek,cci = <&cci>;
65 };
66
67 cpu2: cpu@2 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a73";
70 enable-method = "psci";
71 reg = <0x2>;
72 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
73 <&topckgen CLK_TOP_XTAL>;
74 clock-names = "cpu", "intermediate";
75 operating-points-v2 = <&cluster0_opp>;
76 mediatek,cci = <&cci>;
77 };
78
79 cpu3: cpu@3 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a73";
82 enable-method = "psci";
83 reg = <0x3>;
84 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
85 <&topckgen CLK_TOP_XTAL>;
86 clock-names = "cpu", "intermediate";
87 operating-points-v2 = <&cluster0_opp>;
88 mediatek,cci = <&cci>;
89 };
90
91 cluster0_opp: opp_table0 {
92 compatible = "operating-points-v2";
93 opp-shared;
94 opp00 {
95 opp-hz = /bits/ 64 <800000000>;
96 opp-microvolt = <850000>;
97 };
98 opp01 {
99 opp-hz = /bits/ 64 <1100000000>;
100 opp-microvolt = <850000>;
101 };
102 opp02 {
103 opp-hz = /bits/ 64 <1500000000>;
104 opp-microvolt = <850000>;
105 };
106 opp03 {
107 opp-hz = /bits/ 64 <1800000000>;
108 opp-microvolt = <900000>;
109 };
110 };
111 };
112
113 cci_opp: opp_table_cci {
114 compatible = "operating-points-v2";
115 opp-shared;
116 opp00 {
117 opp-hz = /bits/ 64 <480000000>;
118 opp-microvolt = <850000>;
119 };
120 opp01 {
121 opp-hz = /bits/ 64 <660000000>;
122 opp-microvolt = <850000>;
123 };
124 opp02 {
125 opp-hz = /bits/ 64 <900000000>;
126 opp-microvolt = <850000>;
127 };
128 opp03 {
129 opp-hz = /bits/ 64 <1080000000>;
130 opp-microvolt = <900000>;
131 };
132 };
133
134 clk40m: oscillator@0 {
135 compatible = "fixed-clock";
136 clock-frequency = <40000000>;
137 #clock-cells = <0>;
138 clock-output-names = "clkxtal";
139 };
140
141 fan: pwm-fan {
142 compatible = "pwm-fan";
143 /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
144 cooling-levels = <0 128 255>;
145 #cooling-cells = <2>;
146 #thermal-sensor-cells = <1>;
147 status = "disabled";
148 };
149
150 pmu {
151 compatible = "arm,cortex-a73-pmu";
152 interrupt-parent = <&gic>;
153 interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
154 };
155
156 psci {
157 compatible = "arm,psci-0.2";
158 method = "smc";
159 };
160
161 reg_1p8v: regulator-1p8v {
162 compatible = "regulator-fixed";
163 regulator-name = "fixed-1.8V";
164 regulator-min-microvolt = <1800000>;
165 regulator-max-microvolt = <1800000>;
166 regulator-boot-on;
167 regulator-always-on;
168 };
169
170 reg_3p3v: regulator-3p3v {
171 compatible = "regulator-fixed";
172 regulator-name = "fixed-3.3V";
173 regulator-min-microvolt = <3300000>;
174 regulator-max-microvolt = <3300000>;
175 regulator-boot-on;
176 regulator-always-on;
177 };
178
179 reserved-memory {
180 #address-cells = <2>;
181 #size-cells = <2>;
182 ranges;
183
184 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
185 secmon_reserved: secmon@43000000 {
186 reg = <0 0x43000000 0 0x50000>;
187 no-map;
188 };
189 };
190
191 soc {
192 #address-cells = <2>;
193 #size-cells = <2>;
194 compatible = "simple-bus";
195 ranges;
196
197 gic: interrupt-controller@c000000 {
198 compatible = "arm,gic-v3";
199 #interrupt-cells = <3>;
200 interrupt-parent = <&gic>;
201 interrupt-controller;
202 reg = <0 0x0c000000 0 0x40000>, /* GICD */
203 <0 0x0c080000 0 0x200000>, /* GICR */
204 <0 0x0c400000 0 0x2000>, /* GICC */
205 <0 0x0c410000 0 0x1000>, /* GICH */
206 <0 0x0c420000 0 0x2000>; /* GICV */
207
208 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
209 };
210
211 phyfw: phy-firmware@f000000 {
212 compatible = "mediatek,2p5gphy-fw";
213 reg = <0 0x0f000000 0 0x8000>,
214 <0 0x0f100000 0 0x20000>,
215 <0 0x0f0f0000 0 0x200>;
216 };
217
218 infracfg: infracfg@10001000 {
219 compatible = "mediatek,mt7988-infracfg", "syscon";
220 reg = <0 0x10001000 0 0x1000>;
221 #clock-cells = <1>;
222 #reset-cells = <1>;
223 };
224
225 topckgen: topckgen@1001b000 {
226 compatible = "mediatek,mt7988-topckgen", "syscon";
227 reg = <0 0x1001b000 0 0x1000>;
228 #clock-cells = <1>;
229 };
230
231 watchdog: watchdog@1001c000 {
232 compatible = "mediatek,mt7988-wdt",
233 "mediatek,mt6589-wdt",
234 "syscon";
235 reg = <0 0x1001c000 0 0x1000>;
236 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
237 #reset-cells = <1>;
238 };
239
240 apmixedsys: apmixedsys@1001e000 {
241 compatible = "mediatek,mt7988-apmixedsys";
242 reg = <0 0x1001e000 0 0x1000>;
243 #clock-cells = <1>;
244 };
245
246 pio: pinctrl@1001f000 {
247 compatible = "mediatek,mt7988-pinctrl", "syscon";
248 reg = <0 0x1001f000 0 0x1000>,
249 <0 0x11c10000 0 0x1000>,
250 <0 0x11d00000 0 0x1000>,
251 <0 0x11d20000 0 0x1000>,
252 <0 0x11e00000 0 0x1000>,
253 <0 0x11f00000 0 0x1000>,
254 <0 0x1000b000 0 0x1000>;
255 reg-names = "gpio_base", "iocfg_tr_base",
256 "iocfg_br_base", "iocfg_rb_base",
257 "iocfg_lb_base", "iocfg_tl_base", "eint";
258 gpio-controller;
259 #gpio-cells = <2>;
260 gpio-ranges = <&pio 0 0 84>;
261 interrupt-controller;
262 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
263 interrupt-parent = <&gic>;
264 #interrupt-cells = <2>;
265
266 mdio0_pins: mdio0-pins {
267 mux {
268 function = "eth";
269 groups = "mdc_mdio0";
270 };
271
272 conf {
273 groups = "mdc_mdio0";
274 drive-strength = <MTK_DRIVE_8mA>;
275 };
276 };
277
278 i2c0_pins: i2c0-pins-g0 {
279 mux {
280 function = "i2c";
281 groups = "i2c0_1";
282 };
283 };
284
285 i2c1_pins: i2c1-pins-g0 {
286 mux {
287 function = "i2c";
288 groups = "i2c1_0";
289 };
290 };
291
292 i2c1_sfp_pins: i2c1-sfp-pins-g0 {
293 mux {
294 function = "i2c";
295 groups = "i2c1_sfp";
296 };
297 };
298
299 i2c2_pins: i2c2-pins {
300 mux {
301 function = "i2c";
302 groups = "i2c2";
303 };
304 };
305
306 i2c2_0_pins: i2c2-pins-g0 {
307 mux {
308 function = "i2c";
309 groups = "i2c2_0";
310 };
311 };
312
313 i2c2_1_pins: i2c2-pins-g1 {
314 mux {
315 function = "i2c";
316 groups = "i2c2_1";
317 };
318 };
319
320 gbe0_led0_pins: gbe0-led0-pins {
321 mux {
322 function = "led";
323 groups = "gbe0_led0";
324 };
325 };
326
327 gbe1_led0_pins: gbe1-led0-pins {
328 mux {
329 function = "led";
330 groups = "gbe1_led0";
331 };
332 };
333
334 gbe2_led0_pins: gbe2-led0-pins {
335 mux {
336 function = "led";
337 groups = "gbe2_led0";
338 };
339 };
340
341 gbe3_led0_pins: gbe3-led0-pins {
342 mux {
343 function = "led";
344 groups = "gbe3_led0";
345 };
346 };
347
348 gbe0_led1_pins: gbe0-led1-pins {
349 mux {
350 function = "led";
351 groups = "gbe0_led1";
352 };
353 };
354
355 gbe1_led1_pins: gbe1-led1-pins {
356 mux {
357 function = "led";
358 groups = "gbe1_led1";
359 };
360 };
361
362 gbe2_led1_pins: gbe2-led1-pins {
363 mux {
364 function = "led";
365 groups = "gbe2_led1";
366 };
367 };
368
369 gbe3_led1_pins: gbe3-led1-pins {
370 mux {
371 function = "led";
372 groups = "gbe3_led1";
373 };
374 };
375
376 i2p5gbe_led0_pins: 2p5gbe-led0-pins {
377 mux {
378 function = "led";
379 groups = "2p5gbe_led0";
380 };
381 };
382
383 i2p5gbe_led1_pins: 2p5gbe-led1-pins {
384 mux {
385 function = "led";
386 groups = "2p5gbe_led1";
387 };
388 };
389
390 mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
391 mux {
392 function = "flash";
393 groups = "emmc_45";
394 };
395 };
396
397 mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
398 mux {
399 function = "flash";
400 groups = "emmc_51";
401 };
402 };
403
404 mmc0_pins_sdcard: mmc0-pins-sdcard {
405 mux {
406 function = "flash";
407 groups = "sdcard";
408 };
409 };
410
411 uart0_pins: uart0-pins {
412 mux {
413 function = "uart";
414 groups = "uart0";
415 };
416 };
417
418 snfi_pins: snfi-pins {
419 mux {
420 function = "flash";
421 groups = "snfi";
422 };
423 };
424
425 spi0_pins: spi0-pins {
426 mux {
427 function = "spi";
428 groups = "spi0";
429 };
430 };
431
432 spi0_flash_pins: spi0-flash-pins {
433 mux {
434 function = "spi";
435 groups = "spi0", "spi0_wp_hold";
436 };
437 };
438
439 spi1_pins: spi1-pins {
440 mux {
441 function = "spi";
442 groups = "spi1";
443 };
444 };
445
446 spi2_pins: spi2-pins {
447 mux {
448 function = "spi";
449 groups = "spi2";
450 };
451 };
452
453 spi2_flash_pins: spi2-flash-pins {
454 mux {
455 function = "spi";
456 groups = "spi2", "spi2_wp_hold";
457 };
458 };
459
460 pcie0_pins: pcie0-pins {
461 mux {
462 function = "pcie";
463 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
464 "pcie_wake_n0_0";
465 };
466 };
467
468 pcie1_pins: pcie1-pins {
469 mux {
470 function = "pcie";
471 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
472 "pcie_wake_n1_0";
473 };
474 };
475
476 pcie2_pins: pcie2-pins {
477 mux {
478 function = "pcie";
479 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
480 "pcie_wake_n2_0";
481 };
482 };
483
484 pcie3_pins: pcie3-pins {
485 mux {
486 function = "pcie";
487 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
488 "pcie_wake_n3_0";
489 };
490 };
491 };
492
493 pwm: pwm@10048000 {
494 compatible = "mediatek,mt7988-pwm";
495 reg = <0 0x10048000 0 0x1000>;
496 #pwm-cells = <2>;
497 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
498 <&infracfg CLK_INFRA_66M_PWM_HCK>,
499 <&infracfg CLK_INFRA_66M_PWM_CK1>,
500 <&infracfg CLK_INFRA_66M_PWM_CK2>,
501 <&infracfg CLK_INFRA_66M_PWM_CK3>,
502 <&infracfg CLK_INFRA_66M_PWM_CK4>,
503 <&infracfg CLK_INFRA_66M_PWM_CK5>,
504 <&infracfg CLK_INFRA_66M_PWM_CK6>,
505 <&infracfg CLK_INFRA_66M_PWM_CK7>,
506 <&infracfg CLK_INFRA_66M_PWM_CK8>;
507 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
508 "pwm4","pwm5","pwm6","pwm7","pwm8";
509 status = "disabled";
510 };
511
512 sgmiisys0: syscon@10060000 {
513 compatible = "mediatek,mt7988-sgmiisys",
514 "mediatek,mt7988-sgmiisys0",
515 "syscon",
516 "simple-mfd";
517 reg = <0 0x10060000 0 0x1000>;
518 resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
519 #clock-cells = <1>;
520
521 sgmiipcs0: pcs {
522 compatible = "mediatek,mt7988-sgmii";
523 clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
524 <&sgmiisys0 CLK_SGM0_TX_EN>,
525 <&sgmiisys0 CLK_SGM0_RX_EN>;
526 clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
527 };
528 };
529
530 sgmiisys1: syscon@10070000 {
531 compatible = "mediatek,mt7988-sgmiisys",
532 "mediatek,mt7988-sgmiisys1",
533 "syscon",
534 "simple-mfd";
535 reg = <0 0x10070000 0 0x1000>;
536 resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>;
537 #clock-cells = <1>;
538
539 sgmiipcs1: pcs {
540 compatible = "mediatek,mt7988-sgmii";
541 clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
542 <&sgmiisys1 CLK_SGM1_TX_EN>,
543 <&sgmiisys1 CLK_SGM1_RX_EN>;
544 clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
545 };
546 };
547
548 usxgmiisys0: pcs@10080000 {
549 compatible = "mediatek,mt7988-usxgmiisys";
550 reg = <0 0x10080000 0 0x1000>;
551 resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
552 clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
553 };
554
555 usxgmiisys1: pcs@10081000 {
556 compatible = "mediatek,mt7988-usxgmiisys";
557 reg = <0 0x10081000 0 0x1000>;
558 resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>;
559 clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
560 };
561
562 mcusys: mcusys@100e0000 {
563 compatible = "mediatek,mt7988-mcusys", "syscon";
564 reg = <0 0x100e0000 0 0x1000>;
565 #clock-cells = <1>;
566 };
567
568 uart0: serial@11000000 {
569 compatible = "mediatek,mt7986-uart",
570 "mediatek,mt6577-uart";
571 reg = <0 0x11000000 0 0x100>;
572 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
573 /*
574 * 8250-mtk driver don't control "baud" clock since commit
575 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
576 * still need to be passed to the driver to prevent probe fail
577 */
578 clocks = <&topckgen CLK_TOP_UART_SEL>,
579 <&infracfg CLK_INFRA_52M_UART0_CK>;
580 clock-names = "baud", "bus";
581 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
582 <&infracfg CLK_INFRA_MUX_UART0_SEL>;
583 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
584 <&topckgen CLK_TOP_UART_SEL>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&uart0_pins>;
587 status = "disabled";
588 };
589
590 snand: spi@11001000 {
591 compatible = "mediatek,mt7986-snand";
592 reg = <0 0x11001000 0 0x1000>;
593 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&infracfg CLK_INFRA_SPINFI>,
595 <&infracfg CLK_INFRA_NFI>;
596 clock-names = "pad_clk", "nfi_clk";
597 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
598 <&topckgen CLK_TOP_NFI1X_SEL>;
599 assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
600 <&topckgen CLK_TOP_MPLL_D8>;
601 nand-ecc-engine = <&bch>;
602 mediatek,quad-spi;
603 #address-cells = <1>;
604 #size-cells = <0>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&snfi_pins>;
607 status = "disabled";
608 };
609
610 bch: ecc@11002000 {
611 compatible = "mediatek,mt7686-ecc";
612 reg = <0 0x11002000 0 0x1000>;
613 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
615 clock-names = "nfiecc_clk";
616 status = "disabled";
617 };
618
619 i2c0: i2c@11003000 {
620 compatible = "mediatek,mt7988-i2c",
621 "mediatek,mt7981-i2c";
622 reg = <0 0x11003000 0 0x1000>,
623 <0 0x10217080 0 0x80>;
624 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
625 clock-div = <1>;
626 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
627 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
628 clock-names = "main", "dma";
629 #address-cells = <1>;
630 #size-cells = <0>;
631 status = "disabled";
632 };
633
634 i2c1: i2c@11004000 {
635 compatible = "mediatek,mt7988-i2c",
636 "mediatek,mt7981-i2c";
637 reg = <0 0x11004000 0 0x1000>,
638 <0 0x10217100 0 0x80>;
639 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
640 clock-div = <1>;
641 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
642 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
643 clock-names = "main", "dma";
644 #address-cells = <1>;
645 #size-cells = <0>;
646 status = "disabled";
647 };
648
649 i2c2: i2c@11005000 {
650 compatible = "mediatek,mt7988-i2c",
651 "mediatek,mt7981-i2c";
652 reg = <0 0x11005000 0 0x1000>,
653 <0 0x10217180 0 0x80>;
654 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
655 clock-div = <1>;
656 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
657 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
658 clock-names = "main", "dma";
659 #address-cells = <1>;
660 #size-cells = <0>;
661 status = "disabled";
662 };
663
664 spi0: spi@11007000 {
665 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
666 reg = <0 0x11007000 0 0x100>;
667 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&topckgen CLK_TOP_MPLL_D2>,
669 <&topckgen CLK_TOP_SPI_SEL>,
670 <&infracfg CLK_INFRA_104M_SPI0>,
671 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
672 clock-names = "parent-clk", "sel-clk", "spi-clk",
673 "spi-hclk";
674 #address-cells = <1>;
675 #size-cells = <0>;
676 status = "disabled";
677 };
678
679 spi1: spi@11008000 {
680 compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
681 reg = <0 0x11008000 0 0x100>;
682 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&topckgen CLK_TOP_MPLL_D2>,
684 <&topckgen CLK_TOP_SPI_SEL>,
685 <&infracfg CLK_INFRA_104M_SPI1>,
686 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
687 clock-names = "parent-clk", "sel-clk", "spi-clk",
688 "spi-hclk";
689 #address-cells = <1>;
690 #size-cells = <0>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&spi1_pins>;
693 status = "disabled";
694 };
695
696 spi2: spi@11009000 {
697 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
698 reg = <0 0x11009000 0 0x100>;
699 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&topckgen CLK_TOP_MPLL_D2>,
701 <&topckgen CLK_TOP_SPI_SEL>,
702 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
703 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
704 clock-names = "parent-clk", "sel-clk", "spi-clk",
705 "spi-hclk";
706 #address-cells = <1>;
707 #size-cells = <0>;
708 status = "disabled";
709 };
710
711 lvts: lvts@1100a000 {
712 compatible = "mediatek,mt7988-lvts-ap";
713 #thermal-sensor-cells = <1>;
714 reg = <0 0x1100a000 0 0x1000>;
715 clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
716 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
717 resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
718 nvmem-cells = <&lvts_calibration>;
719 nvmem-cell-names = "lvts-calib-data-1";
720 };
721
722 ssusb0: usb@11190000 {
723 compatible = "mediatek,mt7988-xhci",
724 "mediatek,mtk-xhci";
725 reg = <0 0x11190000 0 0x2e00>,
726 <0 0x11193e00 0 0x0100>;
727 reg-names = "mac", "ippc";
728 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
729 phys = <&xphyu2port0 PHY_TYPE_USB2>,
730 <&xphyu3port0 PHY_TYPE_USB3>;
731 clocks = <&infracfg CLK_INFRA_USB_SYS>,
732 <&infracfg CLK_INFRA_USB_XHCI>,
733 <&infracfg CLK_INFRA_USB_REF>,
734 <&infracfg CLK_INFRA_66M_USB_HCK>,
735 <&infracfg CLK_INFRA_133M_USB_HCK>;
736 clock-names = "sys_ck",
737 "xhci_ck",
738 "ref_ck",
739 "mcu_ck",
740 "dma_ck";
741 #address-cells = <2>;
742 #size-cells = <2>;
743 mediatek,p0_speed_fixup;
744 status = "disabled";
745 };
746
747 ssusb1: usb@11200000 {
748 compatible = "mediatek,mt7988-xhci",
749 "mediatek,mtk-xhci";
750 reg = <0 0x11200000 0 0x2e00>,
751 <0 0x11203e00 0 0x0100>;
752 reg-names = "mac", "ippc";
753 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
754 phys = <&tphyu2port0 PHY_TYPE_USB2>,
755 <&tphyu3port0 PHY_TYPE_USB3>;
756 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
757 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
758 <&infracfg CLK_INFRA_USB_CK_P1>,
759 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
760 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
761 clock-names = "sys_ck",
762 "xhci_ck",
763 "ref_ck",
764 "mcu_ck",
765 "dma_ck";
766 #address-cells = <2>;
767 #size-cells = <2>;
768 status = "disabled";
769 };
770
771 afe: audio-controller@11210000 {
772 compatible = "mediatek,mt79xx-audio";
773 reg = <0 0x11210000 0 0x9000>;
774 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
776 <&infracfg CLK_INFRA_AUD_26M>,
777 <&infracfg CLK_INFRA_AUD_L>,
778 <&infracfg CLK_INFRA_AUD_AUD>,
779 <&infracfg CLK_INFRA_AUD_EG2>,
780 <&topckgen CLK_TOP_AUD_SEL>,
781 <&topckgen CLK_TOP_AUD_I2S_M>;
782 clock-names = "aud_bus_ck",
783 "aud_26m_ck",
784 "aud_l_ck",
785 "aud_aud_ck",
786 "aud_eg2_ck",
787 "aud_sel",
788 "aud_i2s_m";
789 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
790 <&topckgen CLK_TOP_A1SYS_SEL>,
791 <&topckgen CLK_TOP_AUD_L_SEL>,
792 <&topckgen CLK_TOP_A_TUNER_SEL>;
793 assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
794 <&topckgen CLK_TOP_APLL2_D4>,
795 <&apmixedsys CLK_APMIXED_APLL2>,
796 <&topckgen CLK_TOP_APLL2_D4>;
797 status = "disabled";
798 };
799
800 mmc0: mmc@11230000 {
801 compatible = "mediatek,mt7986-mmc",
802 "mediatek,mt7981-mmc";
803 reg = <0 0x11230000 0 0x1000>,
804 <0 0x11D60000 0 0x1000>;
805 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&infracfg CLK_INFRA_MSDC400>,
807 <&infracfg CLK_INFRA_MSDC2_HCK>,
808 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
809 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
810 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
811 <&topckgen CLK_TOP_EMMC_400M_SEL>;
812 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
813 <&apmixedsys CLK_APMIXED_MSDCPLL>;
814 clock-names = "source",
815 "hclk",
816 "axi_cg",
817 "ahb_cg";
818 #address-cells = <1>;
819 #size-cells = <0>;
820 status = "disabled";
821 };
822
823 pcie2: pcie@11280000 {
824 compatible = "mediatek,mt7988-pcie",
825 "mediatek,mt7986-pcie",
826 "mediatek,mt8192-pcie";
827 device_type = "pci";
828 #address-cells = <3>;
829 #size-cells = <2>;
830 reg = <0 0x11280000 0 0x2000>;
831 reg-names = "pcie-mac";
832 linux,pci-domain = <3>;
833 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
834 bus-range = <0x00 0xff>;
835 ranges = <0x81000000 0x00 0x20000000 0x00
836 0x20000000 0x00 0x00200000>,
837 <0x82000000 0x00 0x20200000 0x00
838 0x20200000 0x00 0x07e00000>;
839 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
840 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
841 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
842 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
843 clock-names = "pl_250m", "tl_26m", "peri_26m",
844 "top_133m";
845 pinctrl-names = "default";
846 pinctrl-0 = <&pcie2_pins>;
847 status = "disabled";
848
849 phys = <&xphyu3port0 PHY_TYPE_PCIE>;
850 phy-names = "pcie-phy";
851
852 #interrupt-cells = <1>;
853 interrupt-map-mask = <0 0 0 0x7>;
854 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
855 <0 0 0 2 &pcie_intc2 1>,
856 <0 0 0 3 &pcie_intc2 2>,
857 <0 0 0 4 &pcie_intc2 3>;
858 pcie_intc2: interrupt-controller {
859 #address-cells = <0>;
860 #interrupt-cells = <1>;
861 interrupt-controller;
862 };
863 };
864
865 pcie3: pcie@11290000 {
866 compatible = "mediatek,mt7988-pcie",
867 "mediatek,mt7986-pcie",
868 "mediatek,mt8192-pcie";
869 device_type = "pci";
870 #address-cells = <3>;
871 #size-cells = <2>;
872 reg = <0 0x11290000 0 0x2000>;
873 reg-names = "pcie-mac";
874 linux,pci-domain = <2>;
875 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
876 bus-range = <0x00 0xff>;
877 ranges = <0x81000000 0x00 0x28000000 0x00
878 0x28000000 0x00 0x00200000>,
879 <0x82000000 0x00 0x28200000 0x00
880 0x28200000 0x00 0x07e00000>;
881 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
882 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
883 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
884 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
885 clock-names = "pl_250m", "tl_26m", "peri_26m",
886 "top_133m";
887 pinctrl-names = "default";
888 pinctrl-0 = <&pcie3_pins>;
889 status = "disabled";
890
891 #interrupt-cells = <1>;
892 interrupt-map-mask = <0 0 0 0x7>;
893 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
894 <0 0 0 2 &pcie_intc3 1>,
895 <0 0 0 3 &pcie_intc3 2>,
896 <0 0 0 4 &pcie_intc3 3>;
897 pcie_intc3: interrupt-controller {
898 #address-cells = <0>;
899 #interrupt-cells = <1>;
900 interrupt-controller;
901 };
902 };
903
904 pcie0: pcie@11300000 {
905 compatible = "mediatek,mt7988-pcie",
906 "mediatek,mt7986-pcie",
907 "mediatek,mt8192-pcie";
908 device_type = "pci";
909 #address-cells = <3>;
910 #size-cells = <2>;
911 reg = <0 0x11300000 0 0x2000>;
912 reg-names = "pcie-mac";
913 linux,pci-domain = <0>;
914 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
915 bus-range = <0x00 0xff>;
916 ranges = <0x81000000 0x00 0x30000000 0x00
917 0x30000000 0x00 0x00200000>,
918 <0x82000000 0x00 0x30200000 0x00
919 0x30200000 0x00 0x07e00000>;
920 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
921 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
922 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
923 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
924 clock-names = "pl_250m", "tl_26m", "peri_26m",
925 "top_133m";
926 pinctrl-names = "default";
927 pinctrl-0 = <&pcie0_pins>;
928 status = "disabled";
929
930 #interrupt-cells = <1>;
931 interrupt-map-mask = <0 0 0 0x7>;
932 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
933 <0 0 0 2 &pcie_intc0 1>,
934 <0 0 0 3 &pcie_intc0 2>,
935 <0 0 0 4 &pcie_intc0 3>;
936 pcie_intc0: interrupt-controller {
937 #address-cells = <0>;
938 #interrupt-cells = <1>;
939 interrupt-controller;
940 };
941 };
942
943 pcie1: pcie@11310000 {
944 compatible = "mediatek,mt7988-pcie",
945 "mediatek,mt7986-pcie",
946 "mediatek,mt8192-pcie";
947 device_type = "pci";
948 #address-cells = <3>;
949 #size-cells = <2>;
950 reg = <0 0x11310000 0 0x2000>;
951 reg-names = "pcie-mac";
952 linux,pci-domain = <1>;
953 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
954 bus-range = <0x00 0xff>;
955 ranges = <0x81000000 0x00 0x38000000 0x00
956 0x38000000 0x00 0x00200000>,
957 <0x82000000 0x00 0x38200000 0x00
958 0x38200000 0x00 0x07e00000>;
959 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
960 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
961 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
962 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
963 clock-names = "pl_250m", "tl_26m", "peri_26m",
964 "top_133m";
965 pinctrl-names = "default";
966 pinctrl-0 = <&pcie1_pins>;
967 status = "disabled";
968
969 #interrupt-cells = <1>;
970 interrupt-map-mask = <0 0 0 0x7>;
971 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
972 <0 0 0 2 &pcie_intc1 1>,
973 <0 0 0 3 &pcie_intc1 2>,
974 <0 0 0 4 &pcie_intc1 3>;
975 pcie_intc1: interrupt-controller {
976 #address-cells = <0>;
977 #interrupt-cells = <1>;
978 interrupt-controller;
979 };
980 };
981
982 tphy: tphy@11c50000 {
983 compatible = "mediatek,mt7988",
984 "mediatek,generic-tphy-v2";
985 #address-cells = <2>;
986 #size-cells = <2>;
987 ranges;
988 status = "disabled";
989 tphyu2port0: usb-phy@11c50000 {
990 reg = <0 0x11c50000 0 0x700>;
991 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
992 clock-names = "ref";
993 #phy-cells = <1>;
994 };
995 tphyu3port0: usb-phy@11c50700 {
996 reg = <0 0x11c50700 0 0x900>;
997 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
998 clock-names = "ref";
999 #phy-cells = <1>;
1000 mediatek,usb3-pll-ssc-delta;
1001 mediatek,usb3-pll-ssc-delta1;
1002 };
1003 };
1004
1005 topmisc: topmisc@11d10000 {
1006 compatible = "mediatek,mt7988-topmisc", "syscon",
1007 "mediatek,mt7988-power-controller";
1008 reg = <0 0x11d10000 0 0x10000>;
1009 #clock-cells = <1>;
1010 #power-domain-cells = <1>;
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1013 };
1014
1015 xphy: xphy@11e10000 {
1016 compatible = "mediatek,mt7988",
1017 "mediatek,xsphy";
1018 #address-cells = <2>;
1019 #size-cells = <2>;
1020 ranges;
1021 status = "disabled";
1022
1023 xphyu2port0: usb-phy@11e10000 {
1024 reg = <0 0x11e10000 0 0x400>;
1025 clocks = <&infracfg CLK_INFRA_USB_UTMI>;
1026 clock-names = "ref";
1027 #phy-cells = <1>;
1028 };
1029
1030 xphyu3port0: usb-phy@11e13000 {
1031 reg = <0 0x11e13400 0 0x500>;
1032 clocks = <&infracfg CLK_INFRA_USB_PIPE>;
1033 clock-names = "ref";
1034 #phy-cells = <1>;
1035 mediatek,syscon-type = <&topmisc 0x218 0>;
1036 };
1037 };
1038
1039 xfi_tphy0: phy@11f20000 {
1040 compatible = "mediatek,mt7988-xfi-tphy";
1041 reg = <0 0x11f20000 0 0x10000>;
1042 resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
1043 clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
1044 clock-names = "xfipll", "topxtal";
1045 mediatek,usxgmii-performance-errata;
1046 #phy-cells = <0>;
1047 };
1048
1049 xfi_tphy1: phy@11f30000 {
1050 compatible = "mediatek,mt7988-xfi-tphy";
1051 reg = <0 0x11f30000 0 0x10000>;
1052 resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>;
1053 clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
1054 clock-names = "xfipll", "topxtal";
1055 #phy-cells = <0>;
1056 };
1057
1058 xfi_pll: clock-controller@11f40000 {
1059 compatible = "mediatek,mt7988-xfi-pll";
1060 reg = <0 0x11f40000 0 0x1000>;
1061 resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>;
1062 #clock-cells = <1>;
1063 };
1064
1065 efuse: efuse@11f50000 {
1066 compatible = "mediatek,efuse";
1067 reg = <0 0x11f50000 0 0x1000>;
1068 #address-cells = <1>;
1069 #size-cells = <1>;
1070
1071 lvts_calibration: calib@918 {
1072 reg = <0x918 0x28>;
1073 };
1074 phy_calibration_p0: calib@940 {
1075 reg = <0x940 0x10>;
1076 };
1077 phy_calibration_p1: calib@954 {
1078 reg = <0x954 0x10>;
1079 };
1080 phy_calibration_p2: calib@968 {
1081 reg = <0x968 0x10>;
1082 };
1083 phy_calibration_p3: calib@97c {
1084 reg = <0x97c 0x10>;
1085 };
1086 cpufreq_calibration: calib@278 {
1087 reg = <0x278 0x1>;
1088 };
1089 };
1090
1091 ethsys: syscon@15000000 {
1092 #address-cells = <1>;
1093 #size-cells = <1>;
1094 compatible = "mediatek,mt7988-ethsys", "syscon";
1095 reg = <0 0x15000000 0 0x1000>;
1096 #clock-cells = <1>;
1097 #reset-cells = <1>;
1098 };
1099
1100 switch: switch@15020000 {
1101 #address-cells = <1>;
1102 #size-cells = <1>;
1103 compatible = "mediatek,mt7988-switch";
1104 reg = <0 0x15020000 0 0x8000>;
1105 interrupt-controller;
1106 #interrupt-cells = <1>;
1107 interrupt-parent = <&gic>;
1108 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1109 resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
1110
1111 ports {
1112 #address-cells = <1>;
1113 #size-cells = <0>;
1114
1115 port@0 {
1116 reg = <0>;
1117 label = "lan0";
1118 phy-mode = "internal";
1119 phy-handle = <&gsw_phy0>;
1120 };
1121
1122 port@1 {
1123 reg = <1>;
1124 label = "lan1";
1125 phy-mode = "internal";
1126 phy-handle = <&gsw_phy1>;
1127 };
1128
1129 port@2 {
1130 reg = <2>;
1131 label = "lan2";
1132 phy-mode = "internal";
1133 phy-handle = <&gsw_phy2>;
1134 };
1135
1136 port@3 {
1137 reg = <3>;
1138 label = "lan3";
1139 phy-mode = "internal";
1140 phy-handle = <&gsw_phy3>;
1141 };
1142
1143 port@6 {
1144 reg = <6>;
1145 ethernet = <&gmac0>;
1146 phy-mode = "internal";
1147
1148 fixed-link {
1149 speed = <10000>;
1150 full-duplex;
1151 pause;
1152 };
1153 };
1154 };
1155
1156 mdio {
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1159 mediatek,pio = <&pio>;
1160
1161 gsw_phy0: ethernet-phy@0 {
1162 compatible = "ethernet-phy-ieee802.3-c22";
1163 reg = <0>;
1164 phy-mode = "internal";
1165 nvmem-cells = <&phy_calibration_p0>;
1166 nvmem-cell-names = "phy-cal-data";
1167
1168 leds {
1169 #address-cells = <1>;
1170 #size-cells = <0>;
1171
1172 gsw_phy0_led0: gsw-phy0-led0@0 {
1173 reg = <0>;
1174 function = LED_FUNCTION_LAN;
1175 status = "disabled";
1176 };
1177
1178 gsw_phy0_led1: gsw-phy0-led1@1 {
1179 reg = <1>;
1180 function = LED_FUNCTION_LAN;
1181 status = "disabled";
1182 };
1183 };
1184 };
1185
1186 gsw_phy1: ethernet-phy@1 {
1187 compatible = "ethernet-phy-ieee802.3-c22";
1188 reg = <1>;
1189 phy-mode = "internal";
1190 nvmem-cells = <&phy_calibration_p1>;
1191 nvmem-cell-names = "phy-cal-data";
1192
1193 leds {
1194 #address-cells = <1>;
1195 #size-cells = <0>;
1196
1197 gsw_phy1_led0: gsw-phy1-led0@0 {
1198 reg = <0>;
1199 function = LED_FUNCTION_LAN;
1200 status = "disabled";
1201 };
1202
1203 gsw_phy1_led1: gsw-phy1-led1@1 {
1204 reg = <1>;
1205 function = LED_FUNCTION_LAN;
1206 status = "disabled";
1207 };
1208 };
1209 };
1210
1211 gsw_phy2: ethernet-phy@2 {
1212 compatible = "ethernet-phy-ieee802.3-c22";
1213 reg = <2>;
1214 phy-mode = "internal";
1215 nvmem-cells = <&phy_calibration_p2>;
1216 nvmem-cell-names = "phy-cal-data";
1217
1218 leds {
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1221
1222 gsw_phy2_led0: gsw-phy2-led0@0 {
1223 reg = <0>;
1224 function = LED_FUNCTION_LAN;
1225 status = "disabled";
1226 };
1227
1228 gsw_phy2_led1: gsw-phy2-led1@1 {
1229 reg = <1>;
1230 function = LED_FUNCTION_LAN;
1231 status = "disabled";
1232 };
1233 };
1234 };
1235
1236 gsw_phy3: ethernet-phy@3 {
1237 compatible = "ethernet-phy-ieee802.3-c22";
1238 reg = <3>;
1239 phy-mode = "internal";
1240 nvmem-cells = <&phy_calibration_p3>;
1241 nvmem-cell-names = "phy-cal-data";
1242
1243 leds {
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1246
1247 gsw_phy3_led0: gsw-phy3-led0@0 {
1248 reg = <0>;
1249 function = LED_FUNCTION_LAN;
1250 status = "disabled";
1251 };
1252
1253 gsw_phy3_led1: gsw-phy3-led1@1 {
1254 reg = <1>;
1255 function = LED_FUNCTION_LAN;
1256 status = "disabled";
1257 };
1258 };
1259 };
1260 };
1261 };
1262
1263 ethwarp: clock-controller@15031000 {
1264 compatible = "mediatek,mt7988-ethwarp";
1265 reg = <0 0x15031000 0 0x1000>;
1266 #clock-cells = <1>;
1267 #reset-cells = <1>;
1268 };
1269
1270 eth: ethernet@15100000 {
1271 compatible = "mediatek,mt7988-eth";
1272 reg = <0 0x15100000 0 0x80000>,
1273 <0 0x15400000 0 0x380000>;
1274 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
1279 <&ethsys CLK_ETHDMA_XGP2_EN>,
1280 <&ethsys CLK_ETHDMA_XGP3_EN>,
1281 <&ethsys CLK_ETHDMA_FE_EN>,
1282 <&ethsys CLK_ETHDMA_GP2_EN>,
1283 <&ethsys CLK_ETHDMA_GP1_EN>,
1284 <&ethsys CLK_ETHDMA_GP3_EN>,
1285 <&ethsys CLK_ETHDMA_ESW_EN>,
1286 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
1287 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
1288 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
1289 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
1290 <&topckgen CLK_TOP_ETH_GMII_SEL>,
1291 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
1292 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
1293 <&topckgen CLK_TOP_ETH_SYS_SEL>,
1294 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
1295 <&topckgen CLK_TOP_ETH_MII_SEL>,
1296 <&topckgen CLK_TOP_NETSYS_SEL>,
1297 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
1298 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
1299 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
1300 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
1301 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
1302 clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
1303 "gp3", "esw", "crypto",
1304 "ethwarp_wocpu2", "ethwarp_wocpu1",
1305 "ethwarp_wocpu0", "top_eth_gmii_sel",
1306 "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
1307 "top_eth_sys_sel", "top_eth_xgmii_sel",
1308 "top_eth_mii_sel", "top_netsys_sel",
1309 "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
1310 "top_netsys_sync_250m_sel",
1311 "top_netsys_ppefb_250m_sel",
1312 "top_netsys_warp_sel";
1313 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
1314 <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
1315 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1316 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1317 <&topckgen CLK_TOP_SGM_0_SEL>,
1318 <&topckgen CLK_TOP_SGM_1_SEL>;
1319 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
1320 <&topckgen CLK_TOP_NET1PLL_D4>,
1321 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1322 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1323 <&apmixedsys CLK_APMIXED_SGMPLL>,
1324 <&apmixedsys CLK_APMIXED_SGMPLL>;
1325 mediatek,ethsys = <&ethsys>;
1326 mediatek,infracfg = <&topmisc>;
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1329
1330 gmac0: mac@0 {
1331 compatible = "mediatek,eth-mac";
1332 reg = <0>;
1333 phy-mode = "internal";
1334 status = "disabled";
1335
1336 fixed-link {
1337 speed = <10000>;
1338 full-duplex;
1339 pause;
1340 };
1341 };
1342
1343 gmac1: mac@1 {
1344 compatible = "mediatek,eth-mac";
1345 reg = <1>;
1346 status = "disabled";
1347 pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
1348 phys = <&xfi_tphy1>;
1349 };
1350
1351 gmac2: mac@2 {
1352 compatible = "mediatek,eth-mac";
1353 reg = <2>;
1354 status = "disabled";
1355 pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
1356 phys = <&xfi_tphy0>;
1357 };
1358
1359 mdio_bus: mdio-bus {
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1362
1363 /* internal 2.5G PHY */
1364 int_2p5g_phy: ethernet-phy@15 {
1365 reg = <15>;
1366 compatible = "ethernet-phy-ieee802.3-c45";
1367 phy-mode = "internal";
1368 };
1369 };
1370 };
1371
1372 crypto: crypto@15600000 {
1373 compatible = "inside-secure,safexcel-eip197b";
1374 reg = <0 0x15600000 0 0x180000>;
1375 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1379 interrupt-names = "ring0", "ring1", "ring2", "ring3";
1380 status = "okay";
1381 };
1382 };
1383
1384 thermal-zones {
1385 cpu_thermal: cpu-thermal {
1386 polling-delay-passive = <1000>;
1387 polling-delay = <1000>;
1388 thermal-sensors = <&lvts 0>;
1389 trips {
1390 cpu_trip_crit: crit {
1391 temperature = <125000>;
1392 hysteresis = <2000>;
1393 type = "critical";
1394 };
1395
1396 cpu_trip_hot: hot {
1397 temperature = <120000>;
1398 hysteresis = <2000>;
1399 type = "hot";
1400 };
1401
1402 cpu_trip_active_high: active-high {
1403 temperature = <115000>;
1404 hysteresis = <2000>;
1405 type = "active";
1406 };
1407
1408 cpu_trip_active_med: active-med {
1409 temperature = <85000>;
1410 hysteresis = <2000>;
1411 type = "active";
1412 };
1413
1414 cpu_trip_active_low: active-low {
1415 temperature = <40000>;
1416 hysteresis = <2000>;
1417 type = "active";
1418 };
1419 };
1420
1421 cooling-maps {
1422 cpu-active-high {
1423 /* active: set fan to cooling level 2 */
1424 cooling-device = <&fan 3 3>;
1425 trip = <&cpu_trip_active_high>;
1426 };
1427
1428 cpu-active-low {
1429 /* active: set fan to cooling level 1 */
1430 cooling-device = <&fan 2 2>;
1431 trip = <&cpu_trip_active_med>;
1432 };
1433
1434 cpu-passive {
1435 /* passive: set fan to cooling level 0 */
1436 cooling-device = <&fan 1 1>;
1437 trip = <&cpu_trip_active_low>;
1438 };
1439 };
1440 };
1441 };
1442
1443 timer {
1444 compatible = "arm,armv8-timer";
1445 interrupt-parent = <&gic>;
1446 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1447 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1448 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1449 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
1450 };
1451 };
Staging tree of Daniel Golle