target/linux/bcm27xx/patches-6.1/950-0941-drm-vc4-hvs-Use-switch-statement-to-simplify-enablin.patch

   1 From 72bfb10c9393688d00e4e0b00d416e23c2753318 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Fri, 17 Feb 2023 15:07:29 +0100
   4 Subject: [PATCH] drm/vc4: hvs: Use switch statement to simplify
   5  enabling/disabling irq
   6
   7 Since we'll support BCM2712 soon, let's move the logic to enable and
   8 disable the end-of-frame interrupts to a switch to extend it more
   9 easily.
  10
  11 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  12 ---
  13  drivers/gpu/drm/vc4/vc4_hvs.c | 42 ++++++++++++++++++++++++++---------
  14  1 file changed, 32 insertions(+), 10 deletions(-)
  15
  16 --- a/drivers/gpu/drm/vc4/vc4_hvs.c
  17 +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
  18 @@ -416,24 +416,46 @@ static void vc4_hvs_irq_enable_eof(const
  19                                    unsigned int channel)
  20  {
  21         struct vc4_dev *vc4 = hvs->vc4;
  22 -       u32 irq_mask = vc4->gen == VC4_GEN_5 ?
  23 -               SCALER5_DISPCTRL_DSPEIEOF(channel) :
  24 -               SCALER_DISPCTRL_DSPEIEOF(channel);
  25
  26 -       HVS_WRITE(SCALER_DISPCTRL,
  27 -                 HVS_READ(SCALER_DISPCTRL) | irq_mask);
  28 +       switch (vc4->gen) {
  29 +       case VC4_GEN_4:
  30 +               HVS_WRITE(SCALER_DISPCTRL,
  31 +                         HVS_READ(SCALER_DISPCTRL) |
  32 +                         SCALER_DISPCTRL_DSPEIEOF(channel));
  33 +               break;
  34 +
  35 +       case VC4_GEN_5:
  36 +               HVS_WRITE(SCALER_DISPCTRL,
  37 +                         HVS_READ(SCALER_DISPCTRL) |
  38 +                         SCALER5_DISPCTRL_DSPEIEOF(channel));
  39 +               break;
  40 +
  41 +       default:
  42 +               break;
  43 +       }
  44  }
  45
  46  static void vc4_hvs_irq_clear_eof(const struct vc4_hvs *hvs,
  47                                   unsigned int channel)
  48  {
  49         struct vc4_dev *vc4 = hvs->vc4;
  50 -       u32 irq_mask = vc4->gen == VC4_GEN_5 ?
  51 -               SCALER5_DISPCTRL_DSPEIEOF(channel) :
  52 -               SCALER_DISPCTRL_DSPEIEOF(channel);
  53
  54 -       HVS_WRITE(SCALER_DISPCTRL,
  55 -                 HVS_READ(SCALER_DISPCTRL) & ~irq_mask);
  56 +       switch (vc4->gen) {
  57 +       case VC4_GEN_4:
  58 +               HVS_WRITE(SCALER_DISPCTRL,
  59 +                         HVS_READ(SCALER_DISPCTRL) &
  60 +                         ~SCALER_DISPCTRL_DSPEIEOF(channel));
  61 +               break;
  62 +
  63 +       case VC4_GEN_5:
  64 +               HVS_WRITE(SCALER_DISPCTRL,
  65 +                         HVS_READ(SCALER_DISPCTRL) &
  66 +                         ~SCALER5_DISPCTRL_DSPEIEOF(channel));
  67 +               break;
  68 +
  69 +       default:
  70 +               break;
  71 +       }
  72  }
  73
  74  static struct vc4_hvs_dlist_allocation *