bcm27xx: update 6.1 patches to latest version
[openwrt/staging/dangole.git] / target / linux / bcm27xx / patches-6.1 / 950-0846-hwrng-iproc-rng200-Add-BCM2838-support.patch
1 From e079555a4c68356e58249cfc041b28f6eb455bd5 Mon Sep 17 00:00:00 2001
2 From: Stefan Wahren <wahrenst@gmx.net>
3 Date: Sat, 4 May 2019 17:06:15 +0200
4 Subject: [PATCH] hwrng: iproc-rng200: Add BCM2838 support
5
6 The HWRNG on the BCM2838 is compatible to iproc-rng200, so add the
7 support to this driver instead of bcm2835-rng.
8
9 Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
10
11 hwrng: iproc-rng200: Correct SoC name
12
13 The Pi 4 SoC is called BCM2711, not BCM2838.
14
15 Fixes: "hwrng: iproc-rng200: Add BCM2838 support"
16
17 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
18 ---
19 drivers/char/hw_random/Kconfig | 2 +-
20 drivers/char/hw_random/iproc-rng200.c | 79 ++++++++++++++++++++++++++-
21 2 files changed, 77 insertions(+), 4 deletions(-)
22
23 --- a/drivers/char/hw_random/Kconfig
24 +++ b/drivers/char/hw_random/Kconfig
25 @@ -104,7 +104,7 @@ config HW_RANDOM_IPROC_RNG200
26 default HW_RANDOM
27 help
28 This driver provides kernel-side support for the RNG200
29 - hardware found on the Broadcom iProc and STB SoCs.
30 + hardware found on the Broadcom iProc, BCM2711 and STB SoCs.
31
32 To compile this driver as a module, choose M here: the
33 module will be called iproc-rng200
34 --- a/drivers/char/hw_random/iproc-rng200.c
35 +++ b/drivers/char/hw_random/iproc-rng200.c
36 @@ -14,6 +14,7 @@
37 #include <linux/module.h>
38 #include <linux/of_address.h>
39 #include <linux/of_platform.h>
40 +#include <linux/of.h>
41 #include <linux/platform_device.h>
42 #include <linux/delay.h>
43
44 @@ -21,6 +22,7 @@
45 #define RNG_CTRL_OFFSET 0x00
46 #define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF
47 #define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001
48 +#define RNG_CTRL_RNG_DIV_CTRL_SHIFT 13
49
50 #define RNG_SOFT_RESET_OFFSET 0x04
51 #define RNG_SOFT_RESET 0x00000001
52 @@ -28,16 +30,23 @@
53 #define RBG_SOFT_RESET_OFFSET 0x08
54 #define RBG_SOFT_RESET 0x00000001
55
56 +#define RNG_TOTAL_BIT_COUNT_OFFSET 0x0C
57 +
58 +#define RNG_TOTAL_BIT_COUNT_THRESHOLD_OFFSET 0x10
59 +
60 #define RNG_INT_STATUS_OFFSET 0x18
61 #define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK 0x80000000
62 #define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK 0x00020000
63 #define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK 0x00000020
64 #define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK 0x00000001
65
66 +#define RNG_INT_ENABLE_OFFSET 0x1C
67 +
68 #define RNG_FIFO_DATA_OFFSET 0x20
69
70 #define RNG_FIFO_COUNT_OFFSET 0x24
71 #define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK 0x000000FF
72 +#define RNG_FIFO_COUNT_RNG_FIFO_THRESHOLD_SHIFT 8
73
74 struct iproc_rng200_dev {
75 struct hwrng rng;
76 @@ -158,6 +167,64 @@ static int iproc_rng200_init(struct hwrn
77 return 0;
78 }
79
80 +static int bcm2711_rng200_read(struct hwrng *rng, void *buf, size_t max,
81 + bool wait)
82 +{
83 + struct iproc_rng200_dev *priv = to_rng_priv(rng);
84 + u32 max_words = max / sizeof(u32);
85 + u32 num_words, count, val;
86 +
87 + /* ensure warm up period has elapsed */
88 + while (1) {
89 + val = ioread32(priv->base + RNG_TOTAL_BIT_COUNT_OFFSET);
90 + if (val > 16)
91 + break;
92 + cpu_relax();
93 + }
94 +
95 + /* ensure fifo is not empty */
96 + while (1) {
97 + num_words = ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) &
98 + RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK;
99 + if (num_words)
100 + break;
101 + if (!wait)
102 + return 0;
103 + cpu_relax();
104 + }
105 +
106 + if (num_words > max_words)
107 + num_words = max_words;
108 +
109 + for (count = 0; count < num_words; count++) {
110 + ((u32 *)buf)[count] = ioread32(priv->base +
111 + RNG_FIFO_DATA_OFFSET);
112 + }
113 +
114 + return num_words * sizeof(u32);
115 +}
116 +
117 +static int bcm2711_rng200_init(struct hwrng *rng)
118 +{
119 + struct iproc_rng200_dev *priv = to_rng_priv(rng);
120 + uint32_t val;
121 +
122 + if (ioread32(priv->base + RNG_CTRL_OFFSET) & RNG_CTRL_RNG_RBGEN_MASK)
123 + return 0;
124 +
125 + /* initial numbers generated are "less random" so will be discarded */
126 + val = 0x40000;
127 + iowrite32(val, priv->base + RNG_TOTAL_BIT_COUNT_THRESHOLD_OFFSET);
128 + /* min fifo count to generate full interrupt */
129 + val = 2 << RNG_FIFO_COUNT_RNG_FIFO_THRESHOLD_SHIFT;
130 + iowrite32(val, priv->base + RNG_FIFO_COUNT_OFFSET);
131 + /* enable the rng - 1Mhz sample rate */
132 + val = (0x3 << RNG_CTRL_RNG_DIV_CTRL_SHIFT) | RNG_CTRL_RNG_RBGEN_MASK;
133 + iowrite32(val, priv->base + RNG_CTRL_OFFSET);
134 +
135 + return 0;
136 +}
137 +
138 static void iproc_rng200_cleanup(struct hwrng *rng)
139 {
140 struct iproc_rng200_dev *priv = to_rng_priv(rng);
141 @@ -184,11 +251,17 @@ static int iproc_rng200_probe(struct pla
142
143 dev_set_drvdata(dev, priv);
144
145 - priv->rng.name = "iproc-rng200";
146 - priv->rng.read = iproc_rng200_read;
147 - priv->rng.init = iproc_rng200_init;
148 + priv->rng.name = pdev->name;
149 priv->rng.cleanup = iproc_rng200_cleanup;
150
151 + if (of_device_is_compatible(dev->of_node, "brcm,bcm2711-rng200")) {
152 + priv->rng.init = bcm2711_rng200_init;
153 + priv->rng.read = bcm2711_rng200_read;
154 + } else {
155 + priv->rng.init = iproc_rng200_init;
156 + priv->rng.read = iproc_rng200_read;
157 + }
158 +
159 /* Register driver */
160 ret = devm_hwrng_register(dev, &priv->rng);
161 if (ret) {