package/boot/uboot-mediatek/patches/101-03-spi-mtk_spim-get-spi-clk-rate-only-once.patch

   1 From 0d6d8a408f80358dd47984320ea9c65e555ac4c9 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Wed, 19 Jul 2023 17:15:54 +0800
   4 Subject: [PATCH 03/29] spi: mtk_spim: get spi clk rate only once
   5
   6 We don't really need to switch clk rate during operating SPIM controller.
   7 Get clk rate only once at driver probing.
   8
   9 Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
  10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  11 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
  12 ---
  13  drivers/spi/mtk_spim.c | 21 +++++++++++++--------
  14  1 file changed, 13 insertions(+), 8 deletions(-)
  15
  16 --- a/drivers/spi/mtk_spim.c
  17 +++ b/drivers/spi/mtk_spim.c
  18 @@ -137,6 +137,8 @@ struct mtk_spim_capability {
  19   * @state:             Controller state
  20   * @sel_clk:           Pad clock
  21   * @spi_clk:           Core clock
  22 + * @pll_clk_rate:      Controller's PLL source clock rate, which is different
  23 + *                     from SPI bus clock rate
  24   * @xfer_len:          Current length of data for transfer
  25   * @hw_cap:            Controller capabilities
  26   * @tick_dly:          Used to postpone SPI sampling time
  27 @@ -149,6 +151,7 @@ struct mtk_spim_priv {
  28         void __iomem *base;
  29         u32 state;
  30         struct clk sel_clk, spi_clk;
  31 +       u32 pll_clk_rate;
  32         u32 xfer_len;
  33         struct mtk_spim_capability hw_cap;
  34         u32 tick_dly;
  35 @@ -253,11 +256,10 @@ static int mtk_spim_hw_init(struct spi_s
  36  static void mtk_spim_prepare_transfer(struct mtk_spim_priv *priv,
  37                                       u32 speed_hz)
  38  {
  39 -       u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
  40 +       u32 div, sck_time, cs_time, reg_val;
  41
  42 -       spi_clk_hz = clk_get_rate(&priv->spi_clk);
  43 -       if (speed_hz <= spi_clk_hz / 4)
  44 -               div = DIV_ROUND_UP(spi_clk_hz, speed_hz);
  45 +       if (speed_hz <= priv->pll_clk_rate / 4)
  46 +               div = DIV_ROUND_UP(priv->pll_clk_rate, speed_hz);
  47         else
  48                 div = 4;
  49
  50 @@ -404,7 +406,7 @@ static int mtk_spim_transfer_wait(struct
  51  {
  52         struct udevice *bus = dev_get_parent(slave->dev);
  53         struct mtk_spim_priv *priv = dev_get_priv(bus);
  54 -       u32 sck_l, sck_h, spi_bus_clk, clk_count, reg;
  55 +       u32 sck_l, sck_h, clk_count, reg;
  56         ulong us = 1;
  57         int ret = 0;
  58
  59 @@ -413,12 +415,11 @@ static int mtk_spim_transfer_wait(struct
  60         else
  61                 clk_count = op->data.nbytes;
  62
  63 -       spi_bus_clk = clk_get_rate(&priv->spi_clk);
  64         sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET;
  65         sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK;
  66 -       do_div(spi_bus_clk, sck_l + sck_h + 2);
  67 +       do_div(priv->pll_clk_rate, sck_l + sck_h + 2);
  68
  69 -       us = CLK_TO_US(spi_bus_clk, clk_count * 8);
  70 +       us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8);
  71         us += 1000 * 1000; /* 1s tolerance */
  72
  73         if (us > UINT_MAX)
  74 @@ -662,6 +663,10 @@ static int mtk_spim_probe(struct udevice
  75         clk_enable(&priv->sel_clk);
  76         clk_enable(&priv->spi_clk);
  77
  78 +       priv->pll_clk_rate = clk_get_rate(&priv->spi_clk);
  79 +       if (priv->pll_clk_rate == 0)
  80 +               return -EINVAL;
  81 +
  82         return 0;
  83  }
  84