ipq806x: fix EA8500 switch control

EA8500 has pcie2 slot unequipped.
By EA8500 hw design default pcie2 reset gpio (gpio63) is used to
reset the switch. That's why enabling pcie2 brings the switch into
a working state.

So let's just control the gpio63 without enabling the pcie2 slot.

We have to remove the pcie2_pins node so the gpio63 is not defined
twice. Because pcie2 node has a reference to pcie2_pins we have to
remove it as well.

Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
[slh: rebase for kernel v4.14 as well]
Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>

diff --git a/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
index 2c8fe922f47d9ceb3450ea1cb49e3d98363d6eae..cd8fa633b1965f40c30042b34da4c2c78d3657ee 100644 (file)
--- a/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
+++ b/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
@@ -39,6 +39,10 @@
 
        soc {
                pinmux@800000 {
+
+                       pinctrl-0 = <&switch_reset>;
+                       pinctrl-names = "default";
+
                        button_pins: button_pins {
                                mux {
                                        pins = "gpio65", "gpio67", "gpio68";
@@ -66,6 +70,16 @@
                                };
                        };
 
+                       switch_reset: switch_reset_pins {
+                               mux {
+                                       pins = "gpio63";
+                                       function = "gpio";
+                                       drive-strength = <2>;
+                                       bias-disable;
+                                       output-low;
+                               };
+                       };
+
                        mdio0_pins: mdio0_pins {
                                mux {
                                        pins = "gpio0", "gpio1";
@@ -164,10 +178,6 @@
                        status = "ok";
                };
 
-               pcie2: pci@1b900000 {
-                       status = "ok";
-               };
-
                nand@1ac00000 {
                        status = "ok";
 
@@ -404,3 +414,7 @@
                };
        };
 };
+
+/delete-node/ &pcie2_pins;
+/delete-node/ &pcie2;
+ 

diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
index 7f49db28288589e5d7ce61921a3da41b3aa1afad..8e1a9c418344cf3a105e98b404e4dd52b0791e5c 100644 (file)
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
+++ b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
@@ -39,6 +39,10 @@
 
        soc {
                pinmux@800000 {
+
+                       pinctrl-0 = <&switch_reset>;
+                       pinctrl-names = "default";
+
                        button_pins: button_pins {
                                mux {
                                        pins = "gpio65", "gpio67", "gpio68";
@@ -66,6 +70,16 @@
                                };
                        };
 
+                       switch_reset: switch_reset_pins {
+                               mux {
+                                       pins = "gpio63";
+                                       function = "gpio";
+                                       drive-strength = <2>;
+                                       bias-disable;
+                                       output-low;
+                               };
+                       };
+
                        mdio0_pins: mdio0_pins {
                                mux {
                                        pins = "gpio0", "gpio1";
@@ -164,10 +178,6 @@
                        status = "ok";
                };
 
-               pcie2: pci@1b900000 {
-                       status = "ok";
-               };
-
                nand@1ac00000 {
                        status = "ok";
 
@@ -404,3 +414,7 @@
                };
        };
 };
+
+/delete-node/ &pcie2_pins;
+/delete-node/ &pcie2;
+