target/linux/ramips/patches-4.4/100-mt7621-core-detect-hack.patch

   1 There is a variant of MT7621 which contains only one CPU core instead of 2.
   2 This is not reflected in the config register, so the kernel detects more
   3 physical cores, which leads to a hang on SMP bringup.
   4 Add a hack to detect missing cores.
   5
   6 Signed-off-by: Felix Fietkau <nbd@nbd.name>
   7
   8 Index: linux-4.4.74/arch/mips/kernel/smp-cps.c
   9 ===================================================================
  10 --- linux-4.4.74.orig/arch/mips/kernel/smp-cps.c
  11 +++ linux-4.4.74/arch/mips/kernel/smp-cps.c
  12 @@ -44,6 +44,11 @@ static unsigned core_vpe_count(unsigned
  13         return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
  14  }
  15
  16 +bool __weak plat_cpu_core_present(int core)
  17 +{
  18 +       return true;
  19 +}
  20 +
  21  static void __init cps_smp_setup(void)
  22  {
  23         unsigned int ncores, nvpes, core_vpes;
  24 @@ -53,6 +58,8 @@ static void __init cps_smp_setup(void)
  25         ncores = mips_cm_numcores();
  26         pr_info("VPE topology ");
  27         for (c = nvpes = 0; c < ncores; c++) {
  28 +               if (!plat_cpu_core_present(c))
  29 +                       continue;
  30                 core_vpes = core_vpe_count(c);
  31                 pr_cont("%c%u", c ? ',' : '{', core_vpes);
  32
  33 Index: linux-4.4.74/arch/mips/ralink/mt7621.c
  34 ===================================================================
  35 --- linux-4.4.74.orig/arch/mips/ralink/mt7621.c
  36 +++ linux-4.4.74/arch/mips/ralink/mt7621.c
  37 @@ -20,6 +20,7 @@
  38  #include <asm/mips-cpc.h>
  39  #include <asm/mach-ralink/ralink_regs.h>
  40  #include <asm/mach-ralink/mt7621.h>
  41 +#include <asm/mips-boards/launch.h>
  42
  43  #include <pinmux.h>
  44
  45 @@ -163,6 +164,20 @@ void __init ralink_of_remap(void)
  46                 panic("Failed to remap core resources");
  47  }
  48
  49 +bool plat_cpu_core_present(int core)
  50 +{
  51 +       struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
  52 +
  53 +       if (!core)
  54 +               return true;
  55 +       launch += core * 2; /* 2 VPEs per core */
  56 +       if (!(launch->flags & LAUNCH_FREADY))
  57 +               return false;
  58 +       if (launch->flags & (LAUNCH_FGO | LAUNCH_FGONE))
  59 +               return false;
  60 +       return true;
  61 +}
  62 +
  63  void prom_soc_init(struct ralink_soc_info *soc_info)
  64  {
  65         void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);