target/linux/lantiq/files/arch/mips/boot/dts/EASY80920.dtsi

   1 #include "vr9.dtsi"
   2
   3 #include <dt-bindings/input/input.h>
   4 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
   5
   6 / {
   7         compatible = "lantiq,easy80920", "lantiq,xway", "lantiq,vr9";
   8
   9         chosen {
  10                 bootargs = "console=ttyLTQ0,115200";
  11         };
  12
  13         aliases {
  14                 led-boot = &power;
  15                 led-failsafe = &power;
  16                 led-running = &power;
  17                 led-upgrade = &power;
  18
  19                 led-usb = &led_usb1;
  20                 led-usb2 = &led_usb2;
  21         };
  22
  23         memory@0 {
  24                 device_type = "memory";
  25                 reg = <0x0 0x4000000>;
  26         };
  27
  28         gpio-keys-polled {
  29                 compatible = "gpio-keys-polled";
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32                 poll-interval = <100>;
  33 /*              reset {
  34                         label = "reset";
  35                         gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
  36                         linux,code = <KEY_RESTART>;
  37                 };*/
  38                 paging {
  39                         label = "paging";
  40                         gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
  41                         linux,code = <KEY_PHONE>;
  42                 };
  43         };
  44
  45         gpio-leds {
  46                 compatible = "gpio-leds";
  47
  48                 power: power {
  49                         label = "easy80920:green:power";
  50                         gpios = <&stp 9 GPIO_ACTIVE_HIGH>;
  51                         default-state = "keep";
  52                 };
  53                 warning {
  54                         label = "easy80920:green:warning";
  55                         gpios = <&stp 22 GPIO_ACTIVE_HIGH>;
  56                 };
  57                 fxs1 {
  58                         label = "easy80920:green:fxs1";
  59                         gpios = <&stp 21 GPIO_ACTIVE_HIGH>;
  60                 };
  61                 fxs2 {
  62                         label = "easy80920:green:fxs2";
  63                         gpios = <&stp 20 GPIO_ACTIVE_HIGH>;
  64                 };
  65                 fxo {
  66                         label = "easy80920:green:fxo";
  67                         gpios = <&stp 19 GPIO_ACTIVE_HIGH>;
  68                 };
  69                 led_usb1: usb1 {
  70                         label = "easy80920:green:usb1";
  71                         gpios = <&stp 18 GPIO_ACTIVE_HIGH>;
  72                 };
  73                 led_usb2: usb2 {
  74                         label = "easy80920:green:usb2";
  75                         gpios = <&stp 15 GPIO_ACTIVE_HIGH>;
  76                 };
  77                 sd {
  78                         label = "easy80920:green:sd";
  79                         gpios = <&stp 14 GPIO_ACTIVE_HIGH>;
  80                 };
  81                 wps {
  82                         label = "easy80920:green:wps";
  83                         gpios = <&stp 12 GPIO_ACTIVE_HIGH>;
  84                 };
  85         };
  86
  87         usb_vbus: regulator-usb-vbus {
  88                 compatible = "regulator-fixed";
  89
  90                 regulator-name = "USB_VBUS";
  91
  92                 regulator-min-microvolt = <5000000>;
  93                 regulator-max-microvolt = <5000000>;
  94
  95                 gpio = <&gpio 33 GPIO_ACTIVE_HIGH>;
  96                 enable-active-high;
  97         };
  98 };
  99
 100 &eth0 {
 101         lan: interface@0 {
 102                 compatible = "lantiq,xrx200-pdi";
 103                 #address-cells = <1>;
 104                 #size-cells = <0>;
 105                 reg = <0>;
 106                 lantiq,switch;
 107
 108                 ethernet@4 {
 109                         compatible = "lantiq,xrx200-pdi-port";
 110                         reg = <4>;
 111                         phy-mode = "gmii";
 112                         phy-handle = <&phy13>;
 113                 };
 114                 ethernet@2 {
 115                         compatible = "lantiq,xrx200-pdi-port";
 116                         reg = <2>;
 117                         phy-mode = "gmii";
 118                         phy-handle = <&phy11>;
 119                 };
 120                 ethernet@1 {
 121                         compatible = "lantiq,xrx200-pdi-port";
 122                         reg = <1>;
 123                         phy-mode = "rgmii";
 124                         phy-handle = <&phy1>;
 125                 };
 126                 ethernet@0 {
 127                         compatible = "lantiq,xrx200-pdi-port";
 128                         reg = <0>;
 129                         phy-mode = "rgmii";
 130                         phy-handle = <&phy0>;
 131                 };
 132         };
 133
 134         wan: interface@1 {
 135                 compatible = "lantiq,xrx200-pdi";
 136                 #address-cells = <1>;
 137                 #size-cells = <0>;
 138                 reg = <1>;
 139                 lantiq,wan;
 140
 141                 ethernet@5 {
 142                         compatible = "lantiq,xrx200-pdi-port";
 143                         reg = <5>;
 144                         phy-mode = "rgmii";
 145                         phy-handle = <&phy5>;
 146                 };
 147         };
 148
 149         mdio@0 {
 150                 #address-cells = <1>;
 151                 #size-cells = <0>;
 152                 compatible = "lantiq,xrx200-mdio";
 153                 reg = <0>;
 154
 155                 phy0: ethernet-phy@0 {
 156                         reg = <0x0>;
 157                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 158                 };
 159                 phy1: ethernet-phy@1 {
 160                         reg = <0x1>;
 161                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 162                 };
 163                 phy5: ethernet-phy@5 {
 164                         reg = <0x5>;
 165                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 166                 };
 167                 phy11: ethernet-phy@11 {
 168                         reg = <0x11>;
 169                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 170                 };
 171                 phy13: ethernet-phy@13 {
 172                         reg = <0x13>;
 173                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 174                 };
 175         };
 176 };
 177
 178 &gphy0 {
 179         lantiq,gphy-mode = <GPHY_MODE_GE>;
 180 };
 181
 182 &gphy1 {
 183         lantiq,gphy-mode = <GPHY_MODE_GE>;
 184 };
 185
 186 &gpio {
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&state_default>;
 189
 190         state_default: pinmux {
 191                 exin3 {
 192                         lantiq,groups = "exin3";
 193                         lantiq,function = "exin";
 194                 };
 195                 stp {
 196                         lantiq,groups = "stp";
 197                         lantiq,function = "stp";
 198                 };
 199                 nand {
 200                         lantiq,groups = "nand cle", "nand ale",
 201                                         "nand rd", "nand rdy";
 202                         lantiq,function = "ebu";
 203                 };
 204                 mdio {
 205                         lantiq,groups = "mdio";
 206                         lantiq,function = "mdio";
 207                 };
 208                 pci {
 209                         lantiq,groups = "gnt1", "req1";
 210                         lantiq,function = "pci";
 211                 };
 212                 conf_out {
 213                         lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */
 214                                         "io4", "io5", "io6", /* stp */
 215                                         "io21",
 216                                         "io33";
 217                         lantiq,open-drain;
 218                         lantiq,pull = <0>;
 219                         lantiq,output = <1>;
 220                 };
 221                 pcie-rst {
 222                         lantiq,pins = "io38";
 223                         lantiq,pull = <0>;
 224                         lantiq,output = <1>;
 225                 };
 226                 conf_in {
 227                         lantiq,pins = "io39", /* exin3 */
 228                                         "io48"; /* nand rdy */
 229                         lantiq,pull = <2>;
 230                 };
 231         };
 232         pins_spi_default: pins_spi_default {
 233                 spi_in {
 234                         lantiq,groups = "spi_di";
 235                         lantiq,function = "spi";
 236                 };
 237                 spi_out {
 238                         lantiq,groups = "spi_do", "spi_clk",
 239                                 "spi_cs4";
 240                         lantiq,function = "spi";
 241                         lantiq,output = <1>;
 242                 };
 243         };
 244 };
 245
 246 &spi {
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&pins_spi_default>;
 249
 250         status = "okay";
 251
 252         m25p80@4 {
 253                 #address-cells = <1>;
 254                 #size-cells = <1>;
 255                 compatible = "jedec,spi-nor";
 256                 reg = <4 0>;
 257                 spi-max-frequency = <1000000>;
 258
 259                 partitions {
 260                         compatible = "fixed-partitions";
 261                         #address-cells = <1>;
 262                         #size-cells = <1>;
 263
 264                         partition@0 {
 265                                 reg = <0x0 0x20000>;
 266                                 label = "SPI (RO) U-Boot Image";
 267                                 read-only;
 268                         };
 269
 270                         partition@20000 {
 271                                 reg = <0x20000 0x10000>;
 272                                 label = "ENV_MAC";
 273                                 read-only;
 274                         };
 275
 276                         partition@30000 {
 277                                 reg = <0x30000 0x10000>;
 278                                 label = "DPF";
 279                                 read-only;
 280                         };
 281
 282                         partition@40000 {
 283                                 reg = <0x40000 0x10000>;
 284                                 label = "NVRAM";
 285                                 read-only;
 286                         };
 287
 288                         partition@500000 {
 289                                 reg = <0x50000 0x003a0000>;
 290                                 label = "kernel";
 291                         };
 292                 };
 293         };
 294 };
 295
 296 &stp {
 297         status = "okay";
 298
 299         lantiq,shadow = <0xffff>;
 300         lantiq,groups = <0x7>;
 301         lantiq,dsl = <0x3>;
 302         lantiq,phy1 = <0x7>;
 303         lantiq,phy2 = <0x7>;
 304         /* lantiq,rising; */
 305 };
 306
 307 &usb_phy0 {
 308         status = "okay";
 309 };
 310
 311 &usb0 {
 312         status = "okay";
 313         vbus-supply = <&usb_vbus>;
 314 };