target/linux/ipq806x/patches-4.9/312-ipq4019-pcie-dts-nodes.patch

   1 Index: linux-4.9.20/arch/arm/boot/dts/qcom-ipq4019.dtsi
   2 ===================================================================
   3 --- linux-4.9.20.orig/arch/arm/boot/dts/qcom-ipq4019.dtsi
   4 +++ linux-4.9.20/arch/arm/boot/dts/qcom-ipq4019.dtsi
   5 @@ -475,5 +475,72 @@
   6                                           "legacy";
   7                         status = "disabled";
   8                 };
   9 +
  10 +               pcie0: pci@40000000 {
  11 +                       compatible = "qcom,pcie-ipq4019";
  12 +                       reg =  <0x40000000 0xf1d
  13 +                               0x40000f20 0xa8
  14 +                               0x80000 0x2000
  15 +                               0x40100000 0x1000>;
  16 +                       reg-names = "dbi", "elbi", "parf", "config";
  17 +                       device_type = "pci";
  18 +                       linux,pci-domain = <0>;
  19 +                       bus-range = <0x00 0xff>;
  20 +                       num-lanes = <1>;
  21 +                       #address-cells = <3>;
  22 +                       #size-cells = <2>;
  23 +
  24 +                       ranges = <0x81000000 0 0x40200000 0x40200000
  25 +                                 0 0x00100000   /* downstream I/O */
  26 +                                 0x82000000 0 0x40300000 0x40300000
  27 +                                 0 0x100000 /* non-prefetchable memory */
  28 +                                 0x82000000 0 0x40400000 0x40400000
  29 +                                 0 0x200000>; /* non-prefetchable memory */
  30 +                       interrupts = <0 141 0>;
  31 +                       interrupt-names = "msi";
  32 +                       #interrupt-cells = <1>;
  33 +                       interrupt-map-mask = <0 0 0 0x7>;
  34 +                       interrupt-map = <0 0 0 1 &intc 0 142
  35 +                                        IRQ_TYPE_LEVEL_HIGH>, /* int_a */
  36 +                                       <0 0 0 2 &intc 0 143
  37 +                                        IRQ_TYPE_LEVEL_HIGH>, /* int_b */
  38 +                                       <0 0 0 3 &intc 0 144
  39 +                                        IRQ_TYPE_LEVEL_HIGH>, /* int_c */
  40 +                                       <0 0 0 4 &intc 0 145
  41 +                                        IRQ_TYPE_LEVEL_HIGH>; /* int_d */
  42 +                       clocks = <&gcc GCC_PCIE_AHB_CLK>,
  43 +                                <&gcc GCC_PCIE_AXI_M_CLK>,
  44 +                                <&gcc GCC_PCIE_AXI_S_CLK>;
  45 +                       clock-names = "ahb",
  46 +                                     "axi_m",
  47 +                                     "axi_s";
  48 +
  49 +                       resets = <&gcc PCIE_AXI_M_ARES>,
  50 +                                <&gcc PCIE_AXI_S_ARES>,
  51 +                                <&gcc PCIE_PIPE_ARES>,
  52 +                                <&gcc PCIE_AXI_M_VMIDMT_ARES>,
  53 +                                <&gcc PCIE_AXI_S_XPU_ARES>,
  54 +                                <&gcc PCIE_PARF_XPU_ARES>,
  55 +                                <&gcc PCIE_PHY_ARES>,
  56 +                                <&gcc PCIE_AXI_M_STICKY_ARES>,
  57 +                                <&gcc PCIE_PIPE_STICKY_ARES>,
  58 +                                <&gcc PCIE_PWR_ARES>,
  59 +                                <&gcc PCIE_AHB_ARES>,
  60 +                                <&gcc PCIE_PHY_AHB_ARES>;
  61 +                       reset-names = "axi_m",
  62 +                                     "axi_s",
  63 +                                     "pipe",
  64 +                                     "axi_m_vmid",
  65 +                                     "axi_s_xpu",
  66 +                                     "parf",
  67 +                                     "phy",
  68 +                                     "axi_m_sticky",
  69 +                                     "pipe_sticky",
  70 +                                     "pwr",
  71 +                                     "ahb",
  72 +                                     "phy_ahb";
  73 +                       status = "disabled";
  74 +               };
  75 +
  76         };
  77  };