target/linux/ipq806x/patches-4.1/700-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch

   1 From 2fbb18f85826a9ba308fedb2cf90d3a661a39fd7 Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Fri, 27 Mar 2015 00:16:14 -0700
   4 Subject: [PATCH] clk: qcom: Add support for NSS/GMAC clocks and resets
   5
   6 Add the NSS/GMAC clocks and the TCM clock and NSS resets.
   7
   8 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
   9 ---
  10  drivers/clk/qcom/gcc-ipq806x.c               | 594 ++++++++++++++++++++++++++-
  11  drivers/clk/qcom/gcc-ipq806x.c.rej           |  50 +++
  12  include/dt-bindings/clock/qcom,gcc-ipq806x.h |   2 +
  13  include/dt-bindings/reset/qcom,gcc-ipq806x.h |  43 ++
  14  4 files changed, 688 insertions(+), 1 deletion(-)
  15  create mode 100644 drivers/clk/qcom/gcc-ipq806x.c.rej
  16
  17 --- a/drivers/clk/qcom/gcc-ipq806x.c
  18 +++ b/drivers/clk/qcom/gcc-ipq806x.c
  19 @@ -220,12 +220,47 @@ static struct clk_regmap pll14_vote = {
  20         },
  21  };
  22
  23 +#define NSS_PLL_RATE(f, _l, _m, _n, i) \
  24 +       {  \
  25 +               .freq = f,  \
  26 +               .l = _l, \
  27 +               .m = _m, \
  28 +               .n = _n, \
  29 +               .ibits = i, \
  30 +       }
  31 +
  32 +static struct pll_freq_tbl pll18_freq_tbl[] = {
  33 +       NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
  34 +       NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
  35 +};
  36 +
  37 +static struct clk_pll pll18 = {
  38 +       .l_reg = 0x31a4,
  39 +       .m_reg = 0x31a8,
  40 +       .n_reg = 0x31ac,
  41 +       .config_reg = 0x31b4,
  42 +       .mode_reg = 0x31a0,
  43 +       .status_reg = 0x31b8,
  44 +       .status_bit = 16,
  45 +       .post_div_shift = 16,
  46 +       .post_div_width = 1,
  47 +       .freq_tbl = pll18_freq_tbl,
  48 +       .clkr.hw.init = &(struct clk_init_data){
  49 +               .name = "pll18",
  50 +               .parent_names = (const char *[]){ "pxo" },
  51 +               .num_parents = 1,
  52 +               .ops = &clk_pll_ops,
  53 +       },
  54 +};
  55 +
  56  enum {
  57         P_PXO,
  58         P_PLL8,
  59         P_PLL3,
  60         P_PLL0,
  61         P_CXO,
  62 +       P_PLL14,
  63 +       P_PLL18,
  64  };
  65
  66  static const struct parent_map gcc_pxo_pll8_map[] = {
  67 @@ -277,6 +312,22 @@ static const char *gcc_pxo_pll8_pll0_map
  68         "pll0_vote",
  69  };
  70
  71 +static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
  72 +       { P_PXO, 0 },
  73 +       { P_PLL8, 4 },
  74 +       { P_PLL0, 2 },
  75 +       { P_PLL14, 5 },
  76 +       { P_PLL18, 1 },
  77 +};
  78 +
  79 +static const char *gcc_pxo_pll8_pll14_pll18_pll0[] = {
  80 +       "pxo",
  81 +       "pll8_vote",
  82 +       "pll0_vote",
  83 +       "pll14",
  84 +       "pll18",
  85 +};
  86 +
  87  static struct freq_tbl clk_tbl_gsbi_uart[] = {
  88         {  1843200, P_PLL8, 2,  6, 625 },
  89         {  3686400, P_PLL8, 2, 12, 625 },
  90 @@ -2282,6 +2333,472 @@ static struct clk_branch ebi2_aon_clk =
  91         },
  92  };
  93
  94 +static const struct freq_tbl clk_tbl_gmac[] = {
  95 +       { 133000000, P_PLL0, 1,  50, 301 },
  96 +       { 266000000, P_PLL0, 1, 127, 382 },
  97 +       { }
  98 +};
  99 +
 100 +static struct clk_dyn_rcg gmac_core1_src = {
 101 +       .ns_reg[0] = 0x3cac,
 102 +       .ns_reg[1] = 0x3cb0,
 103 +       .md_reg[0] = 0x3ca4,
 104 +       .md_reg[1] = 0x3ca8,
 105 +       .bank_reg = 0x3ca0,
 106 +       .mn[0] = {
 107 +               .mnctr_en_bit = 8,
 108 +               .mnctr_reset_bit = 7,
 109 +               .mnctr_mode_shift = 5,
 110 +               .n_val_shift = 16,
 111 +               .m_val_shift = 16,
 112 +               .width = 8,
 113 +       },
 114 +       .mn[1] = {
 115 +               .mnctr_en_bit = 8,
 116 +               .mnctr_reset_bit = 7,
 117 +               .mnctr_mode_shift = 5,
 118 +               .n_val_shift = 16,
 119 +               .m_val_shift = 16,
 120 +               .width = 8,
 121 +       },
 122 +       .s[0] = {
 123 +               .src_sel_shift = 0,
 124 +               .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
 125 +       },
 126 +       .s[1] = {
 127 +               .src_sel_shift = 0,
 128 +               .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
 129 +       },
 130 +       .p[0] = {
 131 +               .pre_div_shift = 3,
 132 +               .pre_div_width = 2,
 133 +       },
 134 +       .p[1] = {
 135 +               .pre_div_shift = 3,
 136 +               .pre_div_width = 2,
 137 +       },
 138 +       .mux_sel_bit = 0,
 139 +       .freq_tbl = clk_tbl_gmac,
 140 +       .clkr = {
 141 +               .enable_reg = 0x3ca0,
 142 +               .enable_mask = BIT(1),
 143 +               .hw.init = &(struct clk_init_data){
 144 +                       .name = "gmac_core1_src",
 145 +                       .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
 146 +                       .num_parents = 5,
 147 +                       .ops = &clk_dyn_rcg_ops,
 148 +               },
 149 +       },
 150 +};
 151 +
 152 +static struct clk_branch gmac_core1_clk = {
 153 +       .halt_reg = 0x3c20,
 154 +       .halt_bit = 4,
 155 +       .hwcg_reg = 0x3cb4,
 156 +       .hwcg_bit = 6,
 157 +       .clkr = {
 158 +               .enable_reg = 0x3cb4,
 159 +               .enable_mask = BIT(4),
 160 +               .hw.init = &(struct clk_init_data){
 161 +                       .name = "gmac_core1_clk",
 162 +                       .parent_names = (const char *[]){
 163 +                               "gmac_core1_src",
 164 +                       },
 165 +                       .num_parents = 1,
 166 +                       .ops = &clk_branch_ops,
 167 +                       .flags = CLK_SET_RATE_PARENT,
 168 +               },
 169 +       },
 170 +};
 171 +
 172 +static struct clk_dyn_rcg gmac_core2_src = {
 173 +       .ns_reg[0] = 0x3ccc,
 174 +       .ns_reg[1] = 0x3cd0,
 175 +       .md_reg[0] = 0x3cc4,
 176 +       .md_reg[1] = 0x3cc8,
 177 +       .bank_reg = 0x3ca0,
 178 +       .mn[0] = {
 179 +               .mnctr_en_bit = 8,
 180 +               .mnctr_reset_bit = 7,
 181 +               .mnctr_mode_shift = 5,
 182 +               .n_val_shift = 16,
 183 +               .m_val_shift = 16,
 184 +               .width = 8,
 185 +       },
 186 +       .mn[1] = {
 187 +               .mnctr_en_bit = 8,
 188 +               .mnctr_reset_bit = 7,
 189 +               .mnctr_mode_shift = 5,
 190 +               .n_val_shift = 16,
 191 +               .m_val_shift = 16,
 192 +               .width = 8,
 193 +       },
 194 +       .s[0] = {
 195 +               .src_sel_shift = 0,
 196 +               .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
 197 +       },
 198 +       .s[1] = {
 199 +               .src_sel_shift = 0,
 200 +               .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
 201 +       },
 202 +       .p[0] = {
 203 +               .pre_div_shift = 3,
 204 +               .pre_div_width = 2,
 205 +       },
 206 +       .p[1] = {
 207 +               .pre_div_shift = 3,
 208 +               .pre_div_width = 2,
 209 +       },
 210 +       .mux_sel_bit = 0,
 211 +       .freq_tbl = clk_tbl_gmac,
 212 +       .clkr = {
 213 +               .enable_reg = 0x3cc0,
 214 +               .enable_mask = BIT(1),
 215 +               .hw.init = &(struct clk_init_data){
 216 +                       .name = "gmac_core2_src",
 217 +                       .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
 218 +                       .num_parents = 5,
 219 +                       .ops = &clk_dyn_rcg_ops,
 220 +               },
 221 +       },
 222 +};
 223 +
 224 +static struct clk_branch gmac_core2_clk = {
 225 +       .halt_reg = 0x3c20,
 226 +       .halt_bit = 5,
 227 +       .hwcg_reg = 0x3cd4,
 228 +       .hwcg_bit = 6,
 229 +       .clkr = {
 230 +               .enable_reg = 0x3cd4,
 231 +               .enable_mask = BIT(4),
 232 +               .hw.init = &(struct clk_init_data){
 233 +                       .name = "gmac_core2_clk",
 234 +                       .parent_names = (const char *[]){
 235 +                               "gmac_core2_src",
 236 +                       },
 237 +                       .num_parents = 1,
 238 +                       .ops = &clk_branch_ops,
 239 +                       .flags = CLK_SET_RATE_PARENT,
 240 +               },
 241 +       },
 242 +};
 243 +
 244 +static struct clk_dyn_rcg gmac_core3_src = {
 245 +       .ns_reg[0] = 0x3cec,
 246 +       .ns_reg[1] = 0x3cf0,
 247 +       .md_reg[0] = 0x3ce4,
 248 +       .md_reg[1] = 0x3ce8,
 249 +       .bank_reg = 0x3ce0,
 250 +       .mn[0] = {
 251 +               .mnctr_en_bit = 8,
 252 +               .mnctr_reset_bit = 7,
 253 +               .mnctr_mode_shift = 5,
 254 +               .n_val_shift = 16,
 255 +               .m_val_shift = 16,
 256 +               .width = 8,
 257 +       },
 258 +       .mn[1] = {
 259 +               .mnctr_en_bit = 8,
 260 +               .mnctr_reset_bit = 7,
 261 +               .mnctr_mode_shift = 5,
 262 +               .n_val_shift = 16,
 263 +               .m_val_shift = 16,
 264 +               .width = 8,
 265 +       },
 266 +       .s[0] = {
 267 +               .src_sel_shift = 0,
 268 +               .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
 269 +       },
 270 +       .s[1] = {
 271 +               .src_sel_shift = 0,
 272 +               .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
 273 +       },
 274 +       .p[0] = {
 275 +               .pre_div_shift = 3,
 276 +               .pre_div_width = 2,
 277 +       },
 278 +       .p[1] = {
 279 +               .pre_div_shift = 3,
 280 +               .pre_div_width = 2,
 281 +       },
 282 +       .mux_sel_bit = 0,
 283 +       .freq_tbl = clk_tbl_gmac,
 284 +       .clkr = {
 285 +               .enable_reg = 0x3ce0,
 286 +               .enable_mask = BIT(1),
 287 +               .hw.init = &(struct clk_init_data){
 288 +                       .name = "gmac_core3_src",
 289 +                       .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
 290 +                       .num_parents = 5,
 291 +                       .ops = &clk_dyn_rcg_ops,
 292 +               },
 293 +       },
 294 +};
 295 +
 296 +static struct clk_branch gmac_core3_clk = {
 297 +       .halt_reg = 0x3c20,
 298 +       .halt_bit = 6,
 299 +       .hwcg_reg = 0x3cf4,
 300 +       .hwcg_bit = 6,
 301 +       .clkr = {
 302 +               .enable_reg = 0x3cf4,
 303 +               .enable_mask = BIT(4),
 304 +               .hw.init = &(struct clk_init_data){
 305 +                       .name = "gmac_core3_clk",
 306 +                       .parent_names = (const char *[]){
 307 +                               "gmac_core3_src",
 308 +                       },
 309 +                       .num_parents = 1,
 310 +                       .ops = &clk_branch_ops,
 311 +                       .flags = CLK_SET_RATE_PARENT,
 312 +               },
 313 +       },
 314 +};
 315 +
 316 +static struct clk_dyn_rcg gmac_core4_src = {
 317 +       .ns_reg[0] = 0x3d0c,
 318 +       .ns_reg[1] = 0x3d10,
 319 +       .md_reg[0] = 0x3d04,
 320 +       .md_reg[1] = 0x3d08,
 321 +       .bank_reg = 0x3d00,
 322 +       .mn[0] = {
 323 +               .mnctr_en_bit = 8,
 324 +               .mnctr_reset_bit = 7,
 325 +               .mnctr_mode_shift = 5,
 326 +               .n_val_shift = 16,
 327 +               .m_val_shift = 16,
 328 +               .width = 8,
 329 +       },
 330 +       .mn[1] = {
 331 +               .mnctr_en_bit = 8,
 332 +               .mnctr_reset_bit = 7,
 333 +               .mnctr_mode_shift = 5,
 334 +               .n_val_shift = 16,
 335 +               .m_val_shift = 16,
 336 +               .width = 8,
 337 +       },
 338 +       .s[0] = {
 339 +               .src_sel_shift = 0,
 340 +               .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
 341 +       },
 342 +       .s[1] = {
 343 +               .src_sel_shift = 0,
 344 +               .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
 345 +       },
 346 +       .p[0] = {
 347 +               .pre_div_shift = 3,
 348 +               .pre_div_width = 2,
 349 +       },
 350 +       .p[1] = {
 351 +               .pre_div_shift = 3,
 352 +               .pre_div_width = 2,
 353 +       },
 354 +       .mux_sel_bit = 0,
 355 +       .freq_tbl = clk_tbl_gmac,
 356 +       .clkr = {
 357 +               .enable_reg = 0x3d00,
 358 +               .enable_mask = BIT(1),
 359 +               .hw.init = &(struct clk_init_data){
 360 +                       .name = "gmac_core4_src",
 361 +                       .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
 362 +                       .num_parents = 5,
 363 +                       .ops = &clk_dyn_rcg_ops,
 364 +               },
 365 +       },
 366 +};
 367 +
 368 +static struct clk_branch gmac_core4_clk = {
 369 +       .halt_reg = 0x3c20,
 370 +       .halt_bit = 7,
 371 +       .hwcg_reg = 0x3d14,
 372 +       .hwcg_bit = 6,
 373 +       .clkr = {
 374 +               .enable_reg = 0x3d14,
 375 +               .enable_mask = BIT(4),
 376 +               .hw.init = &(struct clk_init_data){
 377 +                       .name = "gmac_core4_clk",
 378 +                       .parent_names = (const char *[]){
 379 +                               "gmac_core4_src",
 380 +                       },
 381 +                       .num_parents = 1,
 382 +                       .ops = &clk_branch_ops,
 383 +                       .flags = CLK_SET_RATE_PARENT,
 384 +               },
 385 +       },
 386 +};
 387 +
 388 +static const struct freq_tbl clk_tbl_nss_tcm[] = {
 389 +       { 266000000, P_PLL0, 3, 0, 0 },
 390 +       { 400000000, P_PLL0, 2, 0, 0 },
 391 +       { }
 392 +};
 393 +
 394 +static struct clk_dyn_rcg nss_tcm_src = {
 395 +       .ns_reg[0] = 0x3dc4,
 396 +       .ns_reg[1] = 0x3dc8,
 397 +       .bank_reg = 0x3dc0,
 398 +       .s[0] = {
 399 +               .src_sel_shift = 0,
 400 +               .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
 401 +       },
 402 +       .s[1] = {
 403 +               .src_sel_shift = 0,
 404 +               .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
 405 +       },
 406 +       .p[0] = {
 407 +               .pre_div_shift = 3,
 408 +               .pre_div_width = 4,
 409 +       },
 410 +       .p[1] = {
 411 +               .pre_div_shift = 3,
 412 +               .pre_div_width = 4,
 413 +       },
 414 +       .mux_sel_bit = 0,
 415 +       .freq_tbl = clk_tbl_nss_tcm,
 416 +       .clkr = {
 417 +               .enable_reg = 0x3dc0,
 418 +               .enable_mask = BIT(1),
 419 +               .hw.init = &(struct clk_init_data){
 420 +                       .name = "nss_tcm_src",
 421 +                       .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
 422 +                       .num_parents = 5,
 423 +                       .ops = &clk_dyn_rcg_ops,
 424 +               },
 425 +       },
 426 +};
 427 +
 428 +static struct clk_branch nss_tcm_clk = {
 429 +       .halt_reg = 0x3c20,
 430 +       .halt_bit = 14,
 431 +       .clkr = {
 432 +               .enable_reg = 0x3dd0,
 433 +               .enable_mask = BIT(6) | BIT(4),
 434 +               .hw.init = &(struct clk_init_data){
 435 +                       .name = "nss_tcm_clk",
 436 +                       .parent_names = (const char *[]){
 437 +                               "nss_tcm_src",
 438 +                       },
 439 +                       .num_parents = 1,
 440 +                       .ops = &clk_branch_ops,
 441 +                       .flags = CLK_SET_RATE_PARENT,
 442 +               },
 443 +       },
 444 +};
 445 +
 446 +static const struct freq_tbl clk_tbl_nss[] = {
 447 +       { 110000000, P_PLL18, 1, 1, 5 },
 448 +       { 275000000, P_PLL18, 2, 0, 0 },
 449 +       { 550000000, P_PLL18, 1, 0, 0 },
 450 +       { 733000000, P_PLL18, 1, 0, 0 },
 451 +       { }
 452 +};
 453 +
 454 +static struct clk_dyn_rcg ubi32_core1_src_clk = {
 455 +       .ns_reg[0] = 0x3d2c,
 456 +       .ns_reg[1] = 0x3d30,
 457 +       .md_reg[0] = 0x3d24,
 458 +       .md_reg[1] = 0x3d28,
 459 +       .bank_reg = 0x3d20,
 460 +       .mn[0] = {
 461 +               .mnctr_en_bit = 8,
 462 +               .mnctr_reset_bit = 7,
 463 +               .mnctr_mode_shift = 5,
 464 +               .n_val_shift = 16,
 465 +               .m_val_shift = 16,
 466 +               .width = 8,
 467 +       },
 468 +       .mn[1] = {
 469 +               .mnctr_en_bit = 8,
 470 +               .mnctr_reset_bit = 7,
 471 +               .mnctr_mode_shift = 5,
 472 +               .n_val_shift = 16,
 473 +               .m_val_shift = 16,
 474 +               .width = 8,
 475 +       },
 476 +       .s[0] = {
 477 +               .src_sel_shift = 0,
 478 +               .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
 479 +       },
 480 +       .s[1] = {
 481 +               .src_sel_shift = 0,
 482 +               .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
 483 +       },
 484 +       .p[0] = {
 485 +               .pre_div_shift = 3,
 486 +               .pre_div_width = 2,
 487 +       },
 488 +       .p[1] = {
 489 +               .pre_div_shift = 3,
 490 +               .pre_div_width = 2,
 491 +       },
 492 +       .mux_sel_bit = 0,
 493 +       .freq_tbl = clk_tbl_nss,
 494 +       .clkr = {
 495 +               .enable_reg = 0x3d20,
 496 +               .enable_mask = BIT(1),
 497 +               .hw.init = &(struct clk_init_data){
 498 +                       .name = "ubi32_core1_src_clk",
 499 +                       .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
 500 +                       .num_parents = 5,
 501 +                       .ops = &clk_dyn_rcg_ops,
 502 +                       .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 503 +               },
 504 +       },
 505 +};
 506 +
 507 +static struct clk_dyn_rcg ubi32_core2_src_clk = {
 508 +       .ns_reg[0] = 0x3d4c,
 509 +       .ns_reg[1] = 0x3d50,
 510 +       .md_reg[0] = 0x3d44,
 511 +       .md_reg[1] = 0x3d48,
 512 +       .bank_reg = 0x3d40,
 513 +       .mn[0] = {
 514 +               .mnctr_en_bit = 8,
 515 +               .mnctr_reset_bit = 7,
 516 +               .mnctr_mode_shift = 5,
 517 +               .n_val_shift = 16,
 518 +               .m_val_shift = 16,
 519 +               .width = 8,
 520 +       },
 521 +       .mn[1] = {
 522 +               .mnctr_en_bit = 8,
 523 +               .mnctr_reset_bit = 7,
 524 +               .mnctr_mode_shift = 5,
 525 +               .n_val_shift = 16,
 526 +               .m_val_shift = 16,
 527 +               .width = 8,
 528 +       },
 529 +       .s[0] = {
 530 +               .src_sel_shift = 0,
 531 +               .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
 532 +       },
 533 +       .s[1] = {
 534 +               .src_sel_shift = 0,
 535 +               .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
 536 +       },
 537 +       .p[0] = {
 538 +               .pre_div_shift = 3,
 539 +               .pre_div_width = 2,
 540 +       },
 541 +       .p[1] = {
 542 +               .pre_div_shift = 3,
 543 +               .pre_div_width = 2,
 544 +       },
 545 +       .mux_sel_bit = 0,
 546 +       .freq_tbl = clk_tbl_nss,
 547 +       .clkr = {
 548 +               .enable_reg = 0x3d40,
 549 +               .enable_mask = BIT(1),
 550 +               .hw.init = &(struct clk_init_data){
 551 +                       .name = "ubi32_core2_src_clk",
 552 +                       .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
 553 +                       .num_parents = 5,
 554 +                       .ops = &clk_dyn_rcg_ops,
 555 +                       .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 556 +               },
 557 +       },
 558 +};
 559 +
 560  static struct clk_regmap *gcc_ipq806x_clks[] = {
 561         [PLL0] = &pll0.clkr,
 562         [PLL0_VOTE] = &pll0_vote,
 563 @@ -2291,6 +2808,7 @@ static struct clk_regmap *gcc_ipq806x_cl
 564         [PLL8_VOTE] = &pll8_vote,
 565         [PLL14] = &pll14.clkr,
 566         [PLL14_VOTE] = &pll14_vote,
 567 +       [PLL18] = &pll18.clkr,
 568         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
 569         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
 570         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
 571 @@ -2390,6 +2908,18 @@ static struct clk_regmap *gcc_ipq806x_cl
 572         [PLL9] = &hfpll0.clkr,
 573         [PLL10] = &hfpll1.clkr,
 574         [PLL12] = &hfpll_l2.clkr,
 575 +       [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr,
 576 +       [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr,
 577 +       [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr,
 578 +       [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr,
 579 +       [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr,
 580 +       [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr,
 581 +       [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr,
 582 +       [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr,
 583 +       [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr,
 584 +       [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
 585 +       [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
 586 +       [NSSTCM_CLK] = &nss_tcm_clk.clkr,
 587  };
 588
 589  static const struct qcom_reset_map gcc_ipq806x_resets[] = {
 590 @@ -2508,6 +3038,48 @@ static const struct qcom_reset_map gcc_i
 591         [USB30_1_PHY_RESET] = { 0x3b58, 0 },
 592         [NSSFB0_RESET] = { 0x3b60, 6 },
 593         [NSSFB1_RESET] = { 0x3b60, 7 },
 594 +       [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3},
 595 +       [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 },
 596 +       [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 },
 597 +       [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 },
 598 +       [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 },
 599 +       [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 },
 600 +       [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 },
 601 +       [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 },
 602 +       [GMAC_CORE1_RESET] = { 0x3cbc, 0 },
 603 +       [GMAC_CORE2_RESET] = { 0x3cdc, 0 },
 604 +       [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
 605 +       [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
 606 +       [GMAC_AHB_RESET] = { 0x3e24, 0 },
 607 +       [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
 608 +       [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
 609 +       [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
 610 +       [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 },
 611 +       [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 },
 612 +       [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 },
 613 +       [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 },
 614 +       [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 },
 615 +       [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 },
 616 +       [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 },
 617 +       [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 },
 618 +       [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 },
 619 +       [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 },
 620 +       [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 },
 621 +       [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 },
 622 +       [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 },
 623 +       [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 },
 624 +       [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 },
 625 +       [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 },
 626 +       [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 },
 627 +       [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 },
 628 +       [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 },
 629 +       [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 },
 630 +       [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 },
 631 +       [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 },
 632 +       [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 },
 633 +       [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 },
 634 +       [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 },
 635 +       [NSS_SRDS_N_RESET] = { 0x3b60, 28 },
 636  };
 637
 638  static const struct regmap_config gcc_ipq806x_regmap_config = {
 639 @@ -2536,6 +3108,8 @@ static int gcc_ipq806x_probe(struct plat
 640  {
 641         struct clk *clk;
 642         struct device *dev = &pdev->dev;
 643 +       struct regmap *regmap;
 644 +       int ret;
 645
 646         /* Temporary until RPM clocks supported */
 647         clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000);
 648 @@ -2546,7 +3120,25 @@ static int gcc_ipq806x_probe(struct plat
 649         if (IS_ERR(clk))
 650                 return PTR_ERR(clk);
 651
 652 -       return qcom_cc_probe(pdev, &gcc_ipq806x_desc);
 653 +       ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
 654 +       if (ret)
 655 +               return ret;
 656 +
 657 +       regmap = dev_get_regmap(dev, NULL);
 658 +       if (!regmap)
 659 +               return -ENODEV;
 660 +
 661 +       /* Setup PLL18 static bits */
 662 +       regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400);
 663 +       regmap_write(regmap, 0x31b0, 0x3080);
 664 +
 665 +       /* Set GMAC footswitch sleep/wakeup values */
 666 +       regmap_write(regmap, 0x3cb8, 8);
 667 +       regmap_write(regmap, 0x3cd8, 8);
 668 +       regmap_write(regmap, 0x3cf8, 8);
 669 +       regmap_write(regmap, 0x3d18, 8);
 670 +
 671 +       return 0;
 672  }
 673
 674  static int gcc_ipq806x_remove(struct platform_device *pdev)
 675 --- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
 676 +++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
 677 @@ -129,4 +129,47 @@
 678  #define USB30_1_PHY_RESET                              112
 679  #define NSSFB0_RESET                                   113
 680  #define NSSFB1_RESET                                   114
 681 +#define UBI32_CORE1_CLKRST_CLAMP_RESET                 115
 682 +#define UBI32_CORE1_CLAMP_RESET                                116
 683 +#define UBI32_CORE1_AHB_RESET                          117
 684 +#define UBI32_CORE1_AXI_RESET                          118
 685 +#define UBI32_CORE2_CLKRST_CLAMP_RESET                 119
 686 +#define UBI32_CORE2_CLAMP_RESET                                120
 687 +#define UBI32_CORE2_AHB_RESET                          121
 688 +#define UBI32_CORE2_AXI_RESET                          122
 689 +#define GMAC_CORE1_RESET                               123
 690 +#define GMAC_CORE2_RESET                               124
 691 +#define GMAC_CORE3_RESET                               125
 692 +#define GMAC_CORE4_RESET                               126
 693 +#define GMAC_AHB_RESET                                 127
 694 +#define NSS_CH0_RST_RX_CLK_N_RESET                     128
 695 +#define NSS_CH0_RST_TX_CLK_N_RESET                     129
 696 +#define NSS_CH0_RST_RX_125M_N_RESET                    130
 697 +#define NSS_CH0_HW_RST_RX_125M_N_RESET                 131
 698 +#define NSS_CH0_RST_TX_125M_N_RESET                    132
 699 +#define NSS_CH1_RST_RX_CLK_N_RESET                     133
 700 +#define NSS_CH1_RST_TX_CLK_N_RESET                     134
 701 +#define NSS_CH1_RST_RX_125M_N_RESET                    135
 702 +#define NSS_CH1_HW_RST_RX_125M_N_RESET                 136
 703 +#define NSS_CH1_RST_TX_125M_N_RESET                    137
 704 +#define NSS_CH2_RST_RX_CLK_N_RESET                     138
 705 +#define NSS_CH2_RST_TX_CLK_N_RESET                     139
 706 +#define NSS_CH2_RST_RX_125M_N_RESET                    140
 707 +#define NSS_CH2_HW_RST_RX_125M_N_RESET                 141
 708 +#define NSS_CH2_RST_TX_125M_N_RESET                    142
 709 +#define NSS_CH3_RST_RX_CLK_N_RESET                     143
 710 +#define NSS_CH3_RST_TX_CLK_N_RESET                     144
 711 +#define NSS_CH3_RST_RX_125M_N_RESET                    145
 712 +#define NSS_CH3_HW_RST_RX_125M_N_RESET                 146
 713 +#define NSS_CH3_RST_TX_125M_N_RESET                    147
 714 +#define NSS_RST_RX_250M_125M_N_RESET                   148
 715 +#define NSS_RST_TX_250M_125M_N_RESET                   149
 716 +#define NSS_QSGMII_TXPI_RST_N_RESET                    150
 717 +#define NSS_QSGMII_CDR_RST_N_RESET                     151
 718 +#define NSS_SGMII2_CDR_RST_N_RESET                     152
 719 +#define NSS_SGMII3_CDR_RST_N_RESET                     153
 720 +#define NSS_CAL_PRBS_RST_N_RESET                       154
 721 +#define NSS_LCKDT_RST_N_RESET                          155
 722 +#define NSS_SRDS_N_RESET                               156
 723 +
 724  #endif
 725 --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
 726 +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
 727 @@ -289,5 +289,7 @@
 728  #define UBI32_CORE1_CLK                                279
 729  #define UBI32_CORE2_CLK                                280
 730  #define EBI2_AON_CLK                           281
 731 +#define NSSTCM_CLK_SRC                         282
 732 +#define NSSTCM_CLK                             283
 733
 734  #endif