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ipq806x: add support for RPM message RAM
[openwrt/staging/blogic.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8065.dtsi
1 /dts-v1/;
2
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
6 #include <dt-bindings/mfd/qcom-rpm.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/gpio/gpio.h>
12
13 / {
14 model = "Qualcomm IPQ8065";
15 compatible = "qcom,ipq8065", "qcom,ipq8064";
16 interrupt-parent = <&intc>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
25 device_type = "cpu";
26 reg = <0>;
27 next-level-cache = <&L2>;
28 qcom,acc = <&acc0>;
29 qcom,saw = <&saw0>;
30 clocks = <&kraitcc 0>, <&kraitcc 4>;
31 clock-names = "cpu", "l2";
32 qcom,imem = <&imem>;
33 clock-latency = <100000>;
34 cpu-supply = <&smb208_s2a>;
35 voltage-tolerance = <5>;
36 cooling-min-state = <0>;
37 cooling-max-state = <10>;
38 #cooling-cells = <2>;
39 cpu-idle-states = <&CPU_SPC>;
40 };
41
42 cpu1: cpu@1 {
43 compatible = "qcom,krait";
44 enable-method = "qcom,kpss-acc-v1";
45 device_type = "cpu";
46 reg = <1>;
47 next-level-cache = <&L2>;
48 qcom,acc = <&acc1>;
49 qcom,saw = <&saw1>;
50 clocks = <&kraitcc 1>, <&kraitcc 4>;
51 clock-names = "cpu", "l2";
52 qcom,imem = <&imem>;
53 clock-latency = <100000>;
54 cpu-supply = <&smb208_s2b>;
55 cooling-min-state = <0>;
56 cooling-max-state = <10>;
57 #cooling-cells = <2>;
58 cpu-idle-states = <&CPU_SPC>;
59 };
60
61 L2: l2-cache {
62 compatible = "cache";
63 cache-level = <2>;
64 qcom,saw = <&saw_l2>;
65 };
66
67 qcom,l2 {
68 qcom,l2-rates = <384000000 1000000000 1200000000>;
69 };
70
71 idle-states {
72 CPU_SPC: spc {
73 compatible = "qcom,idle-state-spc",
74 "arm,idle-state";
75 entry-latency-us = <400>;
76 exit-latency-us = <900>;
77 min-residency-us = <3000>;
78 };
79 };
80 };
81
82 cpu-pmu {
83 compatible = "qcom,krait-pmu";
84 interrupts = <1 10 0x304>;
85 };
86
87 reserved-memory {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 ranges;
91
92 nss@40000000 {
93 reg = <0x40000000 0x1000000>;
94 no-map;
95 };
96
97 smem: smem@41000000 {
98 reg = <0x41000000 0x200000>;
99 no-map;
100 };
101 };
102
103 clocks {
104
105 cxo_board {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <25000000>;
109 };
110
111 pxo_board {
112 compatible = "fixed-clock";
113 #clock-cells = <0>;
114 clock-frequency = <25000000>;
115 };
116
117 sleep_clk: sleep_clk {
118 compatible = "fixed-clock";
119 clock-frequency = <32768>;
120 #clock-cells = <0>;
121 };
122 };
123
124 kraitcc: clock-controller {
125 compatible = "qcom,krait-cc-v1";
126 #clock-cells = <1>;
127 };
128
129 qcom,pvs {
130 qcom,pvs-format-a;
131 qcom,speed0-pvs0-bin-v0 =
132 < 1725000000 1262500 >,
133 < 1400000000 1175000 >,
134 < 1000000000 1100000 >,
135 < 800000000 1050000 >,
136 < 600000000 1000000 >,
137 < 384000000 975000 >;
138 qcom,speed0-pvs1-bin-v0 =
139 < 1725000000 1262500 >,
140 < 1400000000 1175000 >,
141 < 1000000000 1100000 >,
142 < 800000000 1050000 >,
143 < 600000000 1000000 >,
144 < 384000000 950000 >;
145 qcom,speed0-pvs2-bin-v0 =
146 < 1725000000 1200000 >,
147 < 1400000000 1125000 >,
148 < 1000000000 1050000 >,
149 < 800000000 1000000 >,
150 < 600000000 950000 >,
151 < 384000000 925000 >;
152 qcom,speed0-pvs3-bin-v0 =
153 < 1725000000 1175000 >,
154 < 1400000000 1100000 >,
155 < 1000000000 1025000 >,
156 < 800000000 975000 >,
157 < 600000000 925000 >,
158 < 384000000 900000 >;
159 qcom,speed0-pvs4-bin-v0 =
160 < 1725000000 1150000 >,
161 < 1400000000 1075000 >,
162 < 1000000000 1000000 >,
163 < 800000000 950000 >,
164 < 600000000 900000 >,
165 < 384000000 875000 >;
166 qcom,speed0-pvs5-bin-v0 =
167 < 1725000000 1100000 >,
168 < 1400000000 1025000 >,
169 < 1000000000 950000 >,
170 < 800000000 900000 >,
171 < 600000000 850000 >,
172 < 384000000 825000 >;
173 qcom,speed0-pvs6-bin-v0 =
174 < 1725000000 1050000 >,
175 < 1400000000 975000 >,
176 < 1000000000 900000 >,
177 < 800000000 850000 >,
178 < 600000000 800000 >,
179 < 384000000 775000 >;
180 };
181
182 soc: soc {
183 #address-cells = <1>;
184 #size-cells = <1>;
185 ranges;
186 compatible = "simple-bus";
187
188 lpass@28100000 {
189 compatible = "qcom,lpass-cpu";
190 status = "disabled";
191 clocks = <&lcc AHBIX_CLK>,
192 <&lcc MI2S_OSR_CLK>,
193 <&lcc MI2S_BIT_CLK>;
194 clock-names = "ahbix-clk",
195 "mi2s-osr-clk",
196 "mi2s-bit-clk";
197 interrupts = <0 85 1>;
198 interrupt-names = "lpass-irq-lpaif";
199 reg = <0x28100000 0x10000>;
200 reg-names = "lpass-lpaif";
201 };
202
203 imem: memory@700000 {
204 compatible = "qcom,qfprom", "syscon";
205 reg = <0x00700000 0x1000>;
206 #address-cells = <1>;
207 #size-cells = <1>;
208 stride = <1>;
209 ranges = <0x0 0x00700000 0x1000>;
210 };
211
212 rpm@108000 {
213 compatible = "qcom,rpm-ipq8064";
214 reg = <0x108000 0x1000>;
215 qcom,ipc = <&l2cc 0x8 2>;
216
217 interrupts = <0 19 0>,
218 <0 21 0>,
219 <0 22 0>;
220 interrupt-names = "ack",
221 "err",
222 "wakeup";
223
224 #address-cells = <1>;
225 #size-cells = <0>;
226
227 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
228 clock-names = "ram";
229
230 rpmcc: clock-controller {
231 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
232 #clock-cells = <1>;
233 };
234
235 smb208_regulators {
236 compatible = "qcom,rpm-smb208-regulators";
237
238 smb208_s1a: s1a {
239 regulator-min-microvolt = <1050000>;
240 regulator-max-microvolt = <1150000>;
241 qcom,switch-mode-frequency = <1200000>;
242 };
243
244 smb208_s1b: s1b {
245 regulator-min-microvolt = <1050000>;
246 regulator-max-microvolt = <1150000>;
247 qcom,switch-mode-frequency = <1200000>;
248 };
249
250 smb208_s2a: s2a {
251 regulator-min-microvolt = < 800000>;
252 regulator-max-microvolt = <1275000>;
253 qcom,switch-mode-frequency = <1200000>;
254 };
255
256 smb208_s2b: s2b {
257 regulator-min-microvolt = < 800000>;
258 regulator-max-microvolt = <1275000>;
259 qcom,switch-mode-frequency = <1200000>;
260 };
261 };
262 };
263
264 rng@1a500000 {
265 compatible = "qcom,prng";
266 reg = <0x1a500000 0x200>;
267 clocks = <&gcc PRNG_CLK>;
268 clock-names = "core";
269 };
270
271 qcom,msm-imem@2A03F000 {
272 compatible = "qcom,msm-imem";
273 reg = <0x2A03F000 0x1000>; /* Address and size of IMEM */
274 ranges = <0x0 0x2A03F000 0x1000>;
275 #address-cells = <1>;
276 #size-cells = <1>;
277
278 download_mode@0 {
279 compatible = "qcom,msm-imem-download_mode";
280 reg = <0x0 8>;
281 };
282
283 restart_reason@65c {
284 compatible = "qcom,msm-imem-restart_reason";
285 reg = <0x65c 4>;
286 };
287
288 l2_dump_offset@14 {
289 compatible = "qcom,msm-imem-l2_dump_offset";
290 reg = <0x14 8>;
291 };
292 };
293
294 qcom_pinmux: pinmux@800000 {
295 compatible = "qcom,ipq8064-pinctrl";
296 reg = <0x800000 0x4000>;
297
298 gpio-controller;
299 #gpio-cells = <2>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
302 interrupts = <0 16 0x4>;
303
304 pcie0_pins: pcie0_pinmux {
305 mux {
306 pins = "gpio3";
307 function = "pcie1_rst";
308 drive-strength = <12>;
309 bias-disable;
310 };
311 };
312
313 pcie1_pins: pcie1_pinmux {
314 mux {
315 pins = "gpio48";
316 function = "pcie2_rst";
317 drive-strength = <12>;
318 bias-disable;
319 };
320 };
321
322 pcie2_pins: pcie2_pinmux {
323 mux {
324 pins = "gpio63";
325 function = "pcie3_rst";
326 drive-strength = <12>;
327 bias-disable;
328 };
329 };
330 };
331
332 intc: interrupt-controller@2000000 {
333 compatible = "qcom,msm-qgic2";
334 interrupt-controller;
335 #interrupt-cells = <3>;
336 reg = <0x02000000 0x1000>,
337 <0x02002000 0x1000>;
338 };
339
340 timer@200a000 {
341 compatible = "qcom,kpss-timer", "qcom,msm-timer";
342 interrupts = <1 1 0x301>,
343 <1 2 0x301>,
344 <1 3 0x301>,
345 <1 4 0x301>,
346 <1 5 0x301>;
347 reg = <0x0200a000 0x100>;
348 clock-frequency = <25000000>,
349 <32768>;
350 clocks = <&sleep_clk>;
351 clock-names = "sleep";
352 cpu-offset = <0x80000>;
353 };
354
355 acc0: clock-controller@2088000 {
356 compatible = "qcom,kpss-acc-v1";
357 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
358 clock-output-names = "acpu0_aux";
359 };
360
361 acc1: clock-controller@2098000 {
362 compatible = "qcom,kpss-acc-v1";
363 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
364 clock-output-names = "acpu1_aux";
365 };
366
367 l2cc: clock-controller@2011000 {
368 compatible = "qcom,kpss-gcc", "syscon";
369 reg = <0x2011000 0x1000>;
370 clock-output-names = "acpu_l2_aux";
371 };
372
373 saw0: regulator@2089000 {
374 compatible = "qcom,saw2", "syscon";
375 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
376 regulator;
377 };
378
379 saw1: regulator@2099000 {
380 compatible = "qcom,saw2", "syscon";
381 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
382 regulator;
383 };
384
385 saw_l2: regulator@02012000 {
386 compatible = "qcom,saw2", "syscon";
387 reg = <0x02012000 0x1000>;
388 regulator;
389 };
390
391 sic_non_secure: sic-non-secure@12100000 {
392 compatible = "syscon";
393 reg = <0x12100000 0x10000>;
394 };
395
396 gsbi1: gsbi@12440000 {
397 compatible = "qcom,gsbi-v1.0.0";
398 cell-index = <1>;
399 reg = <0x12440000 0x100>;
400 clocks = <&gcc GSBI1_H_CLK>;
401 clock-names = "iface";
402 #address-cells = <1>;
403 #size-cells = <1>;
404 ranges;
405 status = "disabled";
406
407 syscon-tcsr = <&tcsr>;
408
409 uart1: serial@12450000 {
410 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
411 reg = <0x12450000 0x1000>,
412 <0x12440000 0x1000>;
413 interrupts = <0 193 0x0>;
414 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
415 clock-names = "core", "iface";
416 status = "disabled";
417 };
418
419 i2c@12460000 {
420 compatible = "qcom,i2c-qup-v1.1.1";
421 reg = <0x12460000 0x1000>;
422 interrupts = <0 194 0>;
423
424 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
425 clock-names = "core", "iface";
426 status = "disabled";
427
428 #address-cells = <1>;
429 #size-cells = <0>;
430 };
431
432 };
433
434 gsbi2: gsbi@12480000 {
435 compatible = "qcom,gsbi-v1.0.0";
436 cell-index = <2>;
437 reg = <0x12480000 0x100>;
438 clocks = <&gcc GSBI2_H_CLK>;
439 clock-names = "iface";
440 #address-cells = <1>;
441 #size-cells = <1>;
442 ranges;
443 status = "disabled";
444
445 syscon-tcsr = <&tcsr>;
446
447 uart2: serial@12490000 {
448 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
449 reg = <0x12490000 0x1000>,
450 <0x12480000 0x1000>;
451 interrupts = <0 195 0x0>;
452 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
453 clock-names = "core", "iface";
454 status = "disabled";
455 };
456
457 i2c@124a0000 {
458 compatible = "qcom,i2c-qup-v1.1.1";
459 reg = <0x124a0000 0x1000>;
460 interrupts = <0 196 0>;
461
462 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
463 clock-names = "core", "iface";
464 status = "disabled";
465
466 #address-cells = <1>;
467 #size-cells = <0>;
468 };
469
470 };
471
472 gsbi4: gsbi@16300000 {
473 compatible = "qcom,gsbi-v1.0.0";
474 cell-index = <4>;
475 reg = <0x16300000 0x100>;
476 clocks = <&gcc GSBI4_H_CLK>;
477 clock-names = "iface";
478 #address-cells = <1>;
479 #size-cells = <1>;
480 ranges;
481 status = "disabled";
482
483 syscon-tcsr = <&tcsr>;
484
485 uart4: serial@16340000 {
486 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
487 reg = <0x16340000 0x1000>,
488 <0x16300000 0x1000>;
489 interrupts = <0 152 0x0>;
490 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
491 clock-names = "core", "iface";
492 status = "disabled";
493 };
494
495 i2c@16380000 {
496 compatible = "qcom,i2c-qup-v1.1.1";
497 reg = <0x16380000 0x1000>;
498 interrupts = <0 153 0>;
499
500 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
501 clock-names = "core", "iface";
502 status = "disabled";
503
504 #address-cells = <1>;
505 #size-cells = <0>;
506 };
507 };
508
509 gsbi5: gsbi@1a200000 {
510 compatible = "qcom,gsbi-v1.0.0";
511 cell-index = <5>;
512 reg = <0x1a200000 0x100>;
513 clocks = <&gcc GSBI5_H_CLK>;
514 clock-names = "iface";
515 #address-cells = <1>;
516 #size-cells = <1>;
517 ranges;
518 status = "disabled";
519
520 syscon-tcsr = <&tcsr>;
521
522 uart5: serial@1a240000 {
523 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
524 reg = <0x1a240000 0x1000>,
525 <0x1a200000 0x1000>;
526 interrupts = <0 154 0x0>;
527 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
528 clock-names = "core", "iface";
529 status = "disabled";
530 };
531
532 i2c@1a280000 {
533 compatible = "qcom,i2c-qup-v1.1.1";
534 reg = <0x1a280000 0x1000>;
535 interrupts = <0 155 0>;
536
537 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
538 clock-names = "core", "iface";
539 status = "disabled";
540
541 #address-cells = <1>;
542 #size-cells = <0>;
543 };
544
545 spi@1a280000 {
546 compatible = "qcom,spi-qup-v1.1.1";
547 reg = <0x1a280000 0x1000>;
548 interrupts = <0 155 0>;
549
550 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
551 clock-names = "core", "iface";
552 status = "disabled";
553
554 #address-cells = <1>;
555 #size-cells = <0>;
556 };
557 };
558
559 gsbi6: gsbi@16500000 {
560 compatible = "qcom,gsbi-v1.0.0";
561 cell-index = <6>;
562 reg = <0x16500000 0x100>;
563 clocks = <&gcc GSBI6_H_CLK>;
564 clock-names = "iface";
565 #address-cells = <1>;
566 #size-cells = <1>;
567 ranges;
568 status = "disabled";
569
570 syscon-tcsr = <&tcsr>;
571
572 uart6: serial@16540000 {
573 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
574 reg = <0x16540000 0x1000>,
575 <0x16500000 0x1000>;
576 interrupts = <0 156 0x0>;
577 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
578 clock-names = "core", "iface";
579 status = "disabled";
580 };
581
582 i2c@16580000 {
583 compatible = "qcom,i2c-qup-v1.1.1";
584 reg = <0x16580000 0x1000>;
585 interrupts = <0 157 0>;
586
587 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
588 clock-names = "core", "iface";
589 status = "disabled";
590
591 #address-cells = <1>;
592 #size-cells = <0>;
593 };
594
595 spi@16580000 {
596 compatible = "qcom,spi-qup-v1.1.1";
597 reg = <0x16580000 0x1000>;
598 interrupts = <0 157 0>;
599
600 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
601 clock-names = "core", "iface";
602 status = "disabled";
603
604 #address-cells = <1>;
605 #size-cells = <0>;
606 };
607 };
608
609 gsbi7: gsbi@16600000 {
610 compatible = "qcom,gsbi-v1.0.0";
611 cell-index = <7>;
612 reg = <0x16600000 0x100>;
613 clocks = <&gcc GSBI7_H_CLK>;
614 clock-names = "iface";
615 #address-cells = <1>;
616 #size-cells = <1>;
617 ranges;
618 status = "disabled";
619
620 syscon-tcsr = <&tcsr>;
621
622 uart7: serial@16640000 {
623 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
624 reg = <0x16640000 0x1000>,
625 <0x16600000 0x1000>;
626 interrupts = <0 158 0x0>;
627 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
628 clock-names = "core", "iface";
629 status = "disabled";
630 };
631
632 i2c@16680000 {
633 compatible = "qcom,i2c-qup-v1.1.1";
634 reg = <0x16680000 0x1000>;
635 interrupts = <0 159 0>;
636
637 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
638 clock-names = "core", "iface";
639 status = "disabled";
640
641 #address-cells = <1>;
642 #size-cells = <0>;
643 };
644
645 };
646
647 sata_phy: sata-phy@1b400000 {
648 compatible = "qcom,ipq806x-sata-phy";
649 reg = <0x1b400000 0x200>;
650
651 clocks = <&gcc SATA_PHY_CFG_CLK>;
652 clock-names = "cfg";
653
654 #phy-cells = <0>;
655 status = "disabled";
656 };
657
658 sata@29000000 {
659 compatible = "qcom,ipq806x-ahci", "generic-ahci";
660 reg = <0x29000000 0x180>;
661
662 interrupts = <0 209 0x0>;
663
664 clocks = <&gcc SFAB_SATA_S_H_CLK>,
665 <&gcc SATA_H_CLK>,
666 <&gcc SATA_A_CLK>,
667 <&gcc SATA_RXOOB_CLK>,
668 <&gcc SATA_PMALIVE_CLK>;
669 clock-names = "slave_face", "iface", "core",
670 "rxoob", "pmalive";
671
672 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
673 assigned-clock-rates = <100000000>, <100000000>;
674
675 phys = <&sata_phy>;
676 phy-names = "sata-phy";
677 status = "disabled";
678 };
679
680 qcom,ssbi@500000 {
681 compatible = "qcom,ssbi";
682 reg = <0x00500000 0x1000>;
683 qcom,controller-type = "pmic-arbiter";
684 };
685
686 gcc: clock-controller@900000 {
687 compatible = "qcom,gcc-ipq8064";
688 reg = <0x00900000 0x4000>;
689 #clock-cells = <1>;
690 #reset-cells = <1>;
691 #power-domain-cells = <1>;
692 };
693
694 lcc: clock-controller@28000000 {
695 compatible = "qcom,lcc-ipq8064";
696 reg = <0x28000000 0x1000>;
697 #clock-cells = <1>;
698 #reset-cells = <1>;
699 };
700
701 tcsr: syscon@1a400000 {
702 compatible = "qcom,tcsr-ipq8064", "syscon";
703 reg = <0x1a400000 0x100>;
704 };
705
706 tsens: tsens-ipq806x {
707 compatible = "qcom,ipq806x-tsens";
708 reg = <0x900000 0x3678>, <0x700000 0x420>;
709 reg-names = "tsens_physical", "tsens_eeprom_physical";
710 interrupts = <0 178 0>;
711 qcom,sensors = <11>;
712 qcom,tsens_factor = <1000>;
713 qcom,slope = <1176 1176 1154 1176 1111 1132 1132 1199 1132 1199 1132>;
714 };
715
716 qcom,msm-thermal {
717 compatible = "qcom,msm-thermal";
718 qcom,sensor-id = <0>;
719 qcom,poll-ms = <250>;
720 qcom,limit-temp = <105>;
721 qcom,temp-hysteresis = <10>;
722 qcom,freq-step = <2>;
723 qcom,core-limit-temp = <115>;
724 qcom,core-temp-hysteresis = <10>;
725 qcom,core-control-mask = <0xe>;
726 };
727
728 sfpb_mutex_block: syscon@1200600 {
729 compatible = "syscon";
730 reg = <0x01200600 0x100>;
731 };
732
733 hs_phy_1: phy@100f8800 {
734 compatible = "qcom,dwc3-hs-usb-phy";
735 reg = <0x100f8800 0x30>;
736 clocks = <&gcc USB30_1_UTMI_CLK>;
737 clock-names = "ref";
738 #phy-cells = <0>;
739
740 status = "disabled";
741 };
742
743 ss_phy_1: phy@100f8830 {
744 compatible = "qcom,dwc3-ss-usb-phy";
745 reg = <0x100f8830 0x30>;
746 clocks = <&gcc USB30_1_MASTER_CLK>;
747 clock-names = "ref";
748 #phy-cells = <0>;
749
750 status = "disabled";
751 };
752
753 hs_phy_0: phy@110f8800 {
754 compatible = "qcom,dwc3-hs-usb-phy";
755 reg = <0x110f8800 0x30>;
756 clocks = <&gcc USB30_0_UTMI_CLK>;
757 clock-names = "ref";
758 #phy-cells = <0>;
759
760 status = "disabled";
761 };
762
763 ss_phy_0: phy@110f8830 {
764 compatible = "qcom,dwc3-ss-usb-phy";
765 reg = <0x110f8830 0x30>;
766 clocks = <&gcc USB30_0_MASTER_CLK>;
767 clock-names = "ref";
768 #phy-cells = <0>;
769
770 status = "disabled";
771 };
772
773 usb3_0: usb30@0 {
774 compatible = "qcom,dwc3";
775 #address-cells = <1>;
776 #size-cells = <1>;
777 clocks = <&gcc USB30_0_MASTER_CLK>;
778 clock-names = "core";
779
780 ranges;
781
782 status = "disabled";
783 resets = <&gcc USB30_0_MASTER_RESET>;
784 reset-names = "usb30_mstr_rst";
785
786 dwc3@11000000 {
787 compatible = "snps,dwc3";
788 reg = <0x11000000 0xcd00>;
789 interrupts = <0 110 0x4>;
790 phys = <&hs_phy_0>, <&ss_phy_0>;
791 phy-names = "usb2-phy", "usb3-phy";
792 tx-fifo-resize;
793 dr_mode = "host";
794 };
795 };
796
797 usb3_1: usb30@1 {
798 compatible = "qcom,dwc3";
799 #address-cells = <1>;
800 #size-cells = <1>;
801 clocks = <&gcc USB30_1_MASTER_CLK>;
802 clock-names = "core";
803
804 ranges;
805
806 status = "disabled";
807
808 dwc3@10000000 {
809 compatible = "snps,dwc3";
810 reg = <0x10000000 0xcd00>;
811 interrupts = <0 205 0x4>;
812 phys = <&hs_phy_1>, <&ss_phy_1>;
813 phy-names = "usb2-phy", "usb3-phy";
814 tx-fifo-resize;
815 dr_mode = "host";
816 };
817 };
818
819 pcie0: pci@1b500000 {
820 compatible = "qcom,pcie-v0";
821 reg = <0x1b500000 0x1000
822 0x1b502000 0x80
823 0x1b600000 0x100
824 0x0ff00000 0x100000>;
825 reg-names = "dbi", "elbi", "parf", "config";
826 device_type = "pci";
827 linux,pci-domain = <0>;
828 bus-range = <0x00 0xff>;
829 num-lanes = <1>;
830 #address-cells = <3>;
831 #size-cells = <2>;
832
833 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
834 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
835
836 interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
837 interrupt-names = "msi";
838 #interrupt-cells = <1>;
839 interrupt-map-mask = <0 0 0 0x7>;
840 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
841 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
842 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
843 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
844
845 clocks = <&gcc PCIE_A_CLK>,
846 <&gcc PCIE_H_CLK>,
847 <&gcc PCIE_PHY_CLK>,
848 <&gcc PCIE_AUX_CLK>,
849 <&gcc PCIE_ALT_REF_CLK>;
850 clock-names = "core", "iface", "phy", "aux", "ref";
851
852 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
853 assigned-clock-rates = <100000000>;
854
855 resets = <&gcc PCIE_ACLK_RESET>,
856 <&gcc PCIE_HCLK_RESET>,
857 <&gcc PCIE_POR_RESET>,
858 <&gcc PCIE_PCI_RESET>,
859 <&gcc PCIE_PHY_RESET>,
860 <&gcc PCIE_EXT_RESET>;
861 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
862
863 pinctrl-0 = <&pcie0_pins>;
864 pinctrl-names = "default";
865
866 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
867
868 status = "disabled";
869 };
870
871 pcie1: pci@1b700000 {
872 compatible = "qcom,pcie-v0";
873 reg = <0x1b700000 0x1000
874 0x1b702000 0x80
875 0x1b800000 0x100
876 0x31f00000 0x100000>;
877 reg-names = "dbi", "elbi", "parf", "config";
878 device_type = "pci";
879 linux,pci-domain = <1>;
880 bus-range = <0x00 0xff>;
881 num-lanes = <1>;
882 #address-cells = <3>;
883 #size-cells = <2>;
884
885 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
886 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
887
888 interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
889 interrupt-names = "msi";
890 #interrupt-cells = <1>;
891 interrupt-map-mask = <0 0 0 0x7>;
892 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
893 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
894 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
895 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
896
897 clocks = <&gcc PCIE_1_A_CLK>,
898 <&gcc PCIE_1_H_CLK>,
899 <&gcc PCIE_1_PHY_CLK>,
900 <&gcc PCIE_1_AUX_CLK>,
901 <&gcc PCIE_1_ALT_REF_CLK>;
902 clock-names = "core", "iface", "phy", "aux", "ref";
903
904 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
905 assigned-clock-rates = <100000000>;
906
907 resets = <&gcc PCIE_1_ACLK_RESET>,
908 <&gcc PCIE_1_HCLK_RESET>,
909 <&gcc PCIE_1_POR_RESET>,
910 <&gcc PCIE_1_PCI_RESET>,
911 <&gcc PCIE_1_PHY_RESET>,
912 <&gcc PCIE_1_EXT_RESET>;
913 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
914
915 pinctrl-0 = <&pcie1_pins>;
916 pinctrl-names = "default";
917
918 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
919
920 status = "disabled";
921 };
922
923 pcie2: pci@1b900000 {
924 compatible = "qcom,pcie-v0";
925 reg = <0x1b900000 0x1000
926 0x1b902000 0x80
927 0x1ba00000 0x100
928 0x35f00000 0x100000>;
929 reg-names = "dbi", "elbi", "parf", "config";
930 device_type = "pci";
931 linux,pci-domain = <2>;
932 bus-range = <0x00 0xff>;
933 num-lanes = <1>;
934 #address-cells = <3>;
935 #size-cells = <2>;
936
937 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
938 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
939
940 interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
941 interrupt-names = "msi";
942 #interrupt-cells = <1>;
943 interrupt-map-mask = <0 0 0 0x7>;
944 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
945 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
946 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
947 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
948
949 clocks = <&gcc PCIE_2_A_CLK>,
950 <&gcc PCIE_2_H_CLK>,
951 <&gcc PCIE_2_PHY_CLK>,
952 <&gcc PCIE_2_AUX_CLK>,
953 <&gcc PCIE_2_ALT_REF_CLK>;
954 clock-names = "core", "iface", "phy", "aux", "ref";
955
956 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
957 assigned-clock-rates = <100000000>;
958
959 resets = <&gcc PCIE_2_ACLK_RESET>,
960 <&gcc PCIE_2_HCLK_RESET>,
961 <&gcc PCIE_2_POR_RESET>,
962 <&gcc PCIE_2_PCI_RESET>,
963 <&gcc PCIE_2_PHY_RESET>,
964 <&gcc PCIE_2_EXT_RESET>;
965 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
966
967 pinctrl-0 = <&pcie2_pins>;
968 pinctrl-names = "default";
969
970 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
971
972 status = "disabled";
973 };
974
975 adm_dma: dma@18300000 {
976 compatible = "qcom,adm";
977 reg = <0x18300000 0x100000>;
978 interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
979 #dma-cells = <1>;
980
981 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
982 clock-names = "core", "iface";
983
984 resets = <&gcc ADM0_RESET>,
985 <&gcc ADM0_PBUS_RESET>,
986 <&gcc ADM0_C0_RESET>,
987 <&gcc ADM0_C1_RESET>,
988 <&gcc ADM0_C2_RESET>;
989 reset-names = "clk", "pbus", "c0", "c1", "c2";
990 qcom,ee = <0>;
991
992 status = "disabled";
993 };
994
995 nand@1ac00000 {
996 compatible = "qcom,ebi2-nandc";
997 reg = <0x1ac00000 0x800>;
998
999 clocks = <&gcc EBI2_CLK>,
1000 <&gcc EBI2_AON_CLK>;
1001 clock-names = "core", "aon";
1002
1003 dmas = <&adm_dma 3>;
1004 dma-names = "rxtx";
1005 qcom,cmd-crci = <15>;
1006 qcom,data-crci = <3>;
1007
1008 status = "disabled";
1009 };
1010
1011 nss_common: syscon@03000000 {
1012 compatible = "syscon";
1013 reg = <0x03000000 0x0000FFFF>;
1014 };
1015
1016 qsgmii_csr: syscon@1bb00000 {
1017 compatible = "syscon";
1018 reg = <0x1bb00000 0x000001FF>;
1019 };
1020
1021 gmac0: ethernet@37000000 {
1022 device_type = "network";
1023 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1024 reg = <0x37000000 0x200000>;
1025 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1026 interrupt-names = "macirq";
1027
1028 qcom,nss-common = <&nss_common>;
1029 qcom,qsgmii-csr = <&qsgmii_csr>;
1030
1031 clocks = <&gcc GMAC_CORE1_CLK>;
1032 clock-names = "stmmaceth";
1033
1034 resets = <&gcc GMAC_CORE1_RESET>;
1035 reset-names = "stmmaceth";
1036
1037 status = "disabled";
1038 };
1039
1040 gmac1: ethernet@37200000 {
1041 device_type = "network";
1042 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1043 reg = <0x37200000 0x200000>;
1044 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1045 interrupt-names = "macirq";
1046
1047 qcom,nss-common = <&nss_common>;
1048 qcom,qsgmii-csr = <&qsgmii_csr>;
1049
1050 clocks = <&gcc GMAC_CORE2_CLK>;
1051 clock-names = "stmmaceth";
1052
1053 resets = <&gcc GMAC_CORE2_RESET>;
1054 reset-names = "stmmaceth";
1055
1056 status = "disabled";
1057 };
1058
1059 gmac2: ethernet@37400000 {
1060 device_type = "network";
1061 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1062 reg = <0x37400000 0x200000>;
1063 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1064 interrupt-names = "macirq";
1065
1066 qcom,nss-common = <&nss_common>;
1067 qcom,qsgmii-csr = <&qsgmii_csr>;
1068
1069 clocks = <&gcc GMAC_CORE3_CLK>;
1070 clock-names = "stmmaceth";
1071
1072 resets = <&gcc GMAC_CORE3_RESET>;
1073 reset-names = "stmmaceth";
1074
1075 status = "disabled";
1076 };
1077
1078 gmac3: ethernet@37600000 {
1079 device_type = "network";
1080 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1081 reg = <0x37600000 0x200000>;
1082 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1083 interrupt-names = "macirq";
1084
1085 qcom,nss-common = <&nss_common>;
1086 qcom,qsgmii-csr = <&qsgmii_csr>;
1087
1088 clocks = <&gcc GMAC_CORE4_CLK>;
1089 clock-names = "stmmaceth";
1090
1091 resets = <&gcc GMAC_CORE4_RESET>;
1092 reset-names = "stmmaceth";
1093
1094 status = "disabled";
1095 };
1096
1097 /* Temporary fixed regulator */
1098 vsdcc_fixed: vsdcc-regulator {
1099 compatible = "regulator-fixed";
1100 regulator-name = "SDCC Power";
1101 regulator-min-microvolt = <3300000>;
1102 regulator-max-microvolt = <3300000>;
1103 regulator-always-on;
1104 };
1105
1106 sdcc1bam:dma@12402000 {
1107 compatible = "qcom,bam-v1.3.0";
1108 reg = <0x12402000 0x8000>;
1109 interrupts = <0 98 0>;
1110 clocks = <&gcc SDC1_H_CLK>;
1111 clock-names = "bam_clk";
1112 #dma-cells = <1>;
1113 qcom,ee = <0>;
1114 };
1115
1116 sdcc3bam:dma@12182000 {
1117 compatible = "qcom,bam-v1.3.0";
1118 reg = <0x12182000 0x8000>;
1119 interrupts = <0 96 0>;
1120 clocks = <&gcc SDC3_H_CLK>;
1121 clock-names = "bam_clk";
1122 #dma-cells = <1>;
1123 qcom,ee = <0>;
1124 };
1125
1126 amba {
1127 compatible = "arm,amba-bus";
1128 #address-cells = <1>;
1129 #size-cells = <1>;
1130 ranges;
1131 sdcc1: sdcc@12400000 {
1132 status = "disabled";
1133 compatible = "arm,pl18x", "arm,primecell";
1134 arm,primecell-periphid = <0x00051180>;
1135 reg = <0x12400000 0x2000>;
1136 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1137 interrupt-names = "cmd_irq";
1138 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1139 clock-names = "mclk", "apb_pclk";
1140 bus-width = <8>;
1141 max-frequency = <48000000>;
1142 non-removable;
1143 cap-sd-highspeed;
1144 cap-mmc-highspeed;
1145 vmmc-supply = <&vsdcc_fixed>;
1146 #dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1147 #dma-names = "tx", "rx";
1148 };
1149
1150 sdcc3: sdcc@12180000 {
1151 compatible = "arm,pl18x", "arm,primecell";
1152 arm,primecell-periphid = <0x00051180>;
1153 status = "disabled";
1154 reg = <0x12180000 0x2000>;
1155 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1156 interrupt-names = "cmd_irq";
1157 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1158 clock-names = "mclk", "apb_pclk";
1159 bus-width = <8>;
1160 cap-sd-highspeed;
1161 cap-mmc-highspeed;
1162 max-frequency = <192000000>;
1163 #mmc-ddr-1_8v;
1164 sd-uhs-sdr50;
1165 vmmc-supply = <&vsdcc_fixed>;
1166 #dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1167 #dma-names = "tx", "rx";
1168 };
1169 };
1170 };
1171
1172 sfpb_mutex: sfpb-mutex {
1173 compatible = "qcom,sfpb-mutex";
1174 syscon = <&sfpb_mutex_block 4 4>;
1175
1176 #hwlock-cells = <1>;
1177 };
1178
1179 smem {
1180 compatible = "qcom,smem";
1181 memory-region = <&smem>;
1182 hwlocks = <&sfpb_mutex 3>;
1183 };
1184 };
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