ipq40xx: directly define voltage per opp
[openwrt/staging/blogic.git] / target / linux / ipq40xx / patches-4.19 / 084-ARM-dts-qcom-ipq4019-Fix-MSI-IRQ-type.patch
1 From: Niklas Cassel <niklas.cassel@linaro.org>
2 Subject: [PATCH] ARM: dts: qcom: ipq4019: Fix MSI IRQ type
3 Date: Thu, 24 Jan 2019 14:00:47 +0100
4
5 The databook clearly states that the MSI IRQ (msi_ctrl_int) is a level
6 triggered interrupt.
7
8 The msi_ctrl_int will be high for as long as any MSI status bit is set,
9 thus the IRQ type should be set to IRQ_TYPE_LEVEL_HIGH, causing the
10 IRQ handler to keep getting called, as long as any MSI status bit is set.
11
12 A git grep shows that ipq4019 is the only SoC using snps,dw-pcie that has
13 configured this IRQ incorrectly.
14
15 Not having the correct IRQ type defined will cause us to lose interrupts,
16 which in turn causes timeouts in the PCIe endpoint drivers.
17
18 Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
19 Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
20 ---
21
22 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
23 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
24 @@ -408,7 +408,7 @@
25 ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
26 <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
27
28 - interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
29 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
30 interrupt-names = "msi";
31 #interrupt-cells = <1>;
32 interrupt-map-mask = <0 0 0 0x7>;