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uboot-kirkwood: add uboot for pogoplug v4
[openwrt/staging/blogic.git] / package / boot / uboot-kirkwood / patches / 010-pogoplug_v4.patch
1 --- a/arch/arm/mach-kirkwood/Kconfig
2 +++ b/arch/arm/mach-kirkwood/Kconfig
3 @@ -25,6 +25,9 @@ config TARGET_LSXL
4 config TARGET_POGO_E02
5 bool "pogo_e02 Board"
6
7 +config TARGET_POGOPLUGV4
8 + bool "Pogoplug V4 Board"
9 +
10 config TARGET_DNS325
11 bool "dns325 Board"
12
13 @@ -77,6 +80,7 @@ source "board/Marvell/guruplug/Kconfig"
14 source "board/Marvell/sheevaplug/Kconfig"
15 source "board/buffalo/lsxl/Kconfig"
16 source "board/cloudengines/pogo_e02/Kconfig"
17 +source "board/cloudengines/pogoplugv4/Kconfig"
18 source "board/d-link/dns325/Kconfig"
19 source "board/iomega/iconnect/Kconfig"
20 source "board/keymile/km_arm/Kconfig"
21 --- a/arch/arm/mach-kirkwood/include/mach/config.h
22 +++ b/arch/arm/mach-kirkwood/include/mach/config.h
23 @@ -77,6 +77,7 @@
24 * Ethernet Driver configuration
25 */
26 #ifdef CONFIG_CMD_NET
27 +#define CONFIG_FEATURE_COMMAND_EDITING
28 #define CONFIG_NETCONSOLE /* include NetConsole support */
29 #define CONFIG_MII /* expose smi ove miiphy interface */
30 #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
31 @@ -110,6 +111,7 @@
32 #define CONFIG_SYS_ATA_STRIDE 4
33 /* Controller supports 48-bits LBA addressing */
34 #define CONFIG_LBA48
35 +#define CONFIG_SYS_64BIT_LBA
36 /* CONFIG_IDE requires some #defines for ATA registers */
37 #define CONFIG_SYS_IDE_MAXBUS 2
38 #define CONFIG_SYS_IDE_MAXDEVICE 2
39 @@ -134,4 +136,15 @@
40 #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
41 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
42
43 +/*
44 + * Boot option
45 + */
46 +#define CONFIG_CMD_BOOTZ
47 +
48 +/*
49 + * GPIO
50 + */
51 +#define CONFIG_CMD_GPIO
52 +#define CONFIG_KIRKWOOD_GPIO
53 +
54 #endif /* _KW_CONFIG_H */
55 --- a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h
56 +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h
57 @@ -16,6 +16,6 @@
58 #define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE
59
60 /* TCLK Core Clock defination */
61 -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
62 +#define CONFIG_SYS_TCLK 166666667 /* 166MHz */
63
64 #endif /* _CONFIG_KW88F6192_H */
65 --- a/arch/arm/mach-kirkwood/include/mach/mpp.h
66 +++ b/arch/arm/mach-kirkwood/include/mach/mpp.h
67 @@ -217,10 +217,12 @@
68 #define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 )
69 #define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 )
70 #define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 )
71 +#define MPP33_SATA1_ACTn MPP( 33, 0x5, 0, 1, 0, 1, 1, 1 )
72
73 #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 )
74 #define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 )
75 #define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 )
76 +#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 1, 1, 1 )
77
78 #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 )
79 #define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 )
80 --- a/arch/arm/mach-mvebu/include/mach/soc.h
81 +++ b/arch/arm/mach-mvebu/include/mach/soc.h
82 @@ -18,6 +18,8 @@
83 #define SOC_88F6810_ID 0x6810
84 #define SOC_88F6820_ID 0x6820
85 #define SOC_88F6828_ID 0x6828
86 +#define SOC_88F6192_ID 0x6192
87 +#define SOC_88F6702_ID 0x6702
88
89 /* A375 revisions */
90 #define MV_88F67XX_A0_ID 0x3
91 --- /dev/null
92 +++ b/board/cloudengines/pogoplugv4/Kconfig
93 @@ -0,0 +1,12 @@
94 +if TARGET_POGOPLUGV4
95 +
96 +config SYS_BOARD
97 + default "pogoplugv4"
98 +
99 +config SYS_VENDOR
100 + default "cloudengines"
101 +
102 +config SYS_CONFIG_NAME
103 + default "pogoplugv4"
104 +
105 +endif
106 --- /dev/null
107 +++ b/board/cloudengines/pogoplugv4/MAINTAINERS
108 @@ -0,0 +1,6 @@
109 +POGOPLUGV4 BOARD
110 +M: Alberto Bursi <alberto.bursi@outlook.it>
111 +S: Maintained
112 +F: board/cloudengines/pogoplugv4/
113 +F: include/configs/pogoplugv4.h
114 +F: configs/pogoplugv4_defconfig
115 --- /dev/null
116 +++ b/board/cloudengines/pogoplugv4/Makefile
117 @@ -0,0 +1,11 @@
118 +#
119 +# (C) Copyright 2009 bodhi <mibodhi@gmail.com>
120 +#
121 +# Based on
122 +# Marvell Semiconductor <www.marvell.com>
123 +# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
124 +#
125 +# SPDX-License-Identifier: GPL-2.0+
126 +#
127 +
128 +obj-y := pogoplugv4.o
129 --- /dev/null
130 +++ b/board/cloudengines/pogoplugv4/kwbimage.cfg
131 @@ -0,0 +1,167 @@
132 +#
133 +# Copyright (C) 2012
134 +# David Purdy <david.c.purdy@gmail.com>
135 +#
136 +# Based on Kirkwood support:
137 +# (C) Copyright 2009
138 +# Marvell Semiconductor <www.marvell.com>
139 +# Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
140 +#
141 +# See file CREDITS for list of people who contributed to this
142 +# project.
143 +#
144 +# This program is free software; you can redistribute it and/or
145 +# modify it under the terms of the GNU General Public License as
146 +# published by the Free Software Foundation; either version 2 of
147 +# the License, or (at your option) any later version.
148 +#
149 +# This program is distributed in the hope that it will be useful,
150 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
151 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
152 +# GNU General Public License for more details.
153 +#
154 +# You should have received a copy of the GNU General Public License
155 +# along with this program; If not, see <http://www.gnu.org/licenses/>.
156 +#
157 +# Refer docs/README.kwimage for more details about how-to configure
158 +# and create kirkwood boot image
159 +#
160 +
161 +# Boot Media configurations (DONE)
162 +BOOT_FROM nand
163 +NAND_ECC_MODE default
164 +NAND_PAGE_SIZE 0x0800
165 +
166 +# SOC registers configuration using bootrom header extension
167 +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
168 +
169 +# Configure RGMII-0 interface pad voltage to 1.8V (SHOULD BE SAME)
170 +DATA 0xffd100e0 0x1b1b1b9b
171 +
172 +#Dram initalization for SINGLE x16 CL=3 @ 200MHz (need CL=3 @ 200MHz?)
173 +DATA 0xffd01400 0x43000618 # DDR Configuration register
174 +# bit13-0: 0x200 (200 DDR2 clks refresh rate)
175 +# bit23-14: zero
176 +# bit24: 1= enable exit self refresh mode on DDR access
177 +# bit25: 1 required
178 +# bit29-26: zero
179 +# bit31-30: 01
180 +
181 +DATA 0xffd01404 0x34143000 # DDR Controller Control Low
182 +# bit 4: 0=addr/cmd in smame cycle
183 +# bit 5: 0=clk is driven during self refresh, we don't care for APX
184 +# bit 6: 0=use recommended falling edge of clk for addr/cmd
185 +# bit14: 0=input buffer always powered up
186 +# bit18: 1=cpu lock transaction enabled
187 +# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
188 +# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
189 +# bit30-28: 3 required
190 +# bit31: 0=no additional STARTBURST delay
191 +
192 +DATA 0xffd01408 0x11012227 # DDR Timing (Low) (active cycles value +1)
193 +# bit3-0: TRAS lsbs
194 +# bit7-4: TRCD
195 +# bit11- 8: TRP
196 +# bit15-12: TWR
197 +# bit19-16: TWTR
198 +# bit20: TRAS msb
199 +# bit23-21: 0x0
200 +# bit27-24: TRRD
201 +# bit31-28: TRTP
202 +
203 +DATA 0xffd0140c 0x00000819 # DDR Timing (High)
204 +# bit6-0: TRFC
205 +# bit8-7: TR2R
206 +# bit10-9: TR2W
207 +# bit12-11: TW2W
208 +# bit31-13: zero required
209 +
210 +DATA 0xffd01410 0x00000001 # DDR Address Control (changed to Dockstar vals)
211 +# bit1-0: 00, Cs0width=x16
212 +# bit3-2: 10, Cs0size=512Mb
213 +# bit5-4: 00, Cs2width=nonexistent
214 +# bit7-6: 00, Cs1size =nonexistent
215 +# bit9-8: 00, Cs2width=nonexistent
216 +# bit11-10: 00, Cs2size =nonexistent
217 +# bit13-12: 00, Cs3width=nonexistent
218 +# bit15-14: 00, Cs3size =nonexistent
219 +# bit16: 0, Cs0AddrSel
220 +# bit17: 0, Cs1AddrSel
221 +# bit18: 0, Cs2AddrSel
222 +# bit19: 0, Cs3AddrSel
223 +# bit31-20: 0 required
224 +
225 +DATA 0xffd01414 0x00000000 # DDR Open Pages Control
226 +# bit0: 0, OpenPage enabled
227 +# bit31-1: 0 required
228 +
229 +DATA 0xffd01418 0x00000000 # DDR Operation
230 +# bit3-0: 0x0, DDR cmd
231 +# bit31-4: 0 required
232 +
233 +DATA 0xffd0141c 0x00000632 # DDR Mode
234 +# bit2-0: 2, BurstLen=2 required
235 +# bit3: 0, BurstType=0 required
236 +# bit6-4: 4, CL=5 (<===== change to CL=3 ?)
237 +# bit7: 0, TestMode=0 normal
238 +# bit8: 0, DLL reset=0 normal
239 +# bit11-9: 6, auto-precharge write recovery ????????????
240 +# bit12: 0, PD must be zero
241 +# bit31-13: 0 required
242 +
243 +DATA 0xffd01420 0x00000040 # DDR Extended Mode
244 +# bit0: 0, DDR DLL enabled
245 +# bit1: 0, DDR drive strenght normal
246 +# bit2: 0, DDR ODT control lsd (disabled)
247 +# bit5-3: 000, required
248 +# bit6: 1, DDR ODT control msb, (disabled)
249 +# bit9-7: 000, required
250 +# bit10: 0, differential DQS enabled
251 +# bit11: 0, required
252 +# bit12: 0, DDR output buffer enabled
253 +# bit31-13: 0 required
254 +
255 +DATA 0xffd01424 0x0000F07F # DDR Controller Control High
256 +# bit2-0: 111, required
257 +# bit3 : 1 , MBUS Burst Chop disabled
258 +# bit6-4: 111, required
259 +# bit7 : 0
260 +# bit8 : 0 , no sample stage
261 +# bit9 : 0 , no half clock cycle addition to dataout
262 +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
263 +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
264 +# bit15-12: 1111 required
265 +# bit31-16: 0 required
266 +
267 +DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
268 +DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
269 +
270 +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
271 +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
272 +# bit0: 1, Window enabled
273 +# bit1: 0, Write Protect disabled
274 +# bit3-2: 00, CS0 hit selected
275 +# bit23-4: ones, required
276 +# bit31-24: 0x07, Size (i.e. 128MB)
277 +
278 +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
279 +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
280 +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
281 +
282 +DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) (DONE)
283 +# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
284 +# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
285 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
286 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
287 +
288 +DATA 0xffd01498 0x00000000 # DDR ODT Control (High) (DONE)
289 +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
290 +# bit3-2: 01, ODT1 active NEVER!
291 +# bit31-4: zero, required
292 +
293 +DATA 0xffd0149c 0x0000e803 # CPU ODT Control (DONE)
294 +DATA 0xffd01480 0x00000001 # DDR Initialization Control (DONE)
295 +#bit0=1, enable DDR init upon this register write
296 +
297 +# End of Header extension
298 +DATA 0x0 0x0
299 --- /dev/null
300 +++ b/board/cloudengines/pogoplugv4/pogoplugv4.c
301 @@ -0,0 +1,223 @@
302 +/*
303 + * Copyright (C) 2016 bodhi <mibodhi@gmail.com>
304 + * Copyright (C) 2014 bodhi <mibodhi@gmail.com>
305 + *
306 + * Based on
307 + *
308 + * Copyright (C) 2014 <ebbes.ebbes@gmail.com>
309 + *
310 + * Copyright (C) 2012
311 + * David Purdy <david.c.purdy@gmail.com>
312 + *
313 + * Based on Kirkwood support:
314 + * (C) Copyright 2009
315 + * Marvell Semiconductor <www.marvell.com>
316 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
317 + *
318 + * See file CREDITS for list of people who contributed to this
319 + * project.
320 + *
321 + * This program is free software; you can redistribute it and/or
322 + * modify it under the terms of the GNU General Public License as
323 + * published by the Free Software Foundation; either version 2 of
324 + * the License, or (at your option) any later version.
325 + *
326 + * This program is distributed in the hope that it will be useful,
327 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
328 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
329 + * GNU General Public License for more details.
330 + *
331 + * You should have received a copy of the GNU General Public License
332 + * along with this program; If not, see <http://www.gnu.org/licenses/>.
333 + */
334 +
335 +#include <common.h>
336 +#include <miiphy.h>
337 +#include <asm/arch/cpu.h>
338 +#include <asm/arch/soc.h>
339 +#include <asm/arch/mpp.h>
340 +#include <asm/io.h>
341 +#include "pogoplugv4.h"
342 +#include <asm/arch/gpio.h>
343 +
344 +#ifdef CONFIG_KIRKWOOD_MMC
345 +#include <kirkwood_mmc.h>
346 +#endif /* CONFIG_KIRKWOOD_MMC */
347 +
348 +
349 +DECLARE_GLOBAL_DATA_PTR;
350 +
351 +int board_early_init_f(void)
352 +{
353 + /*
354 + * default gpio configuration
355 + * There are maximum 64 gpios controlled through 2 sets of registers
356 + * the below configuration configures mainly initial LED status
357 + */
358 + mvebu_config_gpio(POGOPLUGV4_OE_VAL_LOW,
359 + POGOPLUGV4_OE_VAL_HIGH,
360 + POGOPLUGV4_OE_LOW, POGOPLUGV4_OE_HIGH);
361 +
362 + /* Multi-Purpose Pins Functionality configuration */
363 + u32 kwmpp_config[] = {
364 + MPP0_NF_IO2,
365 + MPP1_NF_IO3,
366 + MPP2_NF_IO4,
367 + MPP3_NF_IO5,
368 + MPP4_NF_IO6,
369 + MPP5_NF_IO7,
370 + MPP6_SYSRST_OUTn,
371 + MPP7_GPO,
372 + MPP8_TW_SDA,
373 + MPP9_TW_SCK,
374 + MPP10_UART0_TXD,
375 + MPP11_UART0_RXD,
376 + MPP12_SD_CLK,
377 + MPP13_SD_CMD,
378 + MPP14_SD_D0,
379 + MPP15_SD_D1,
380 + MPP16_SD_D2,
381 + MPP17_SD_D3,
382 + MPP18_NF_IO0,
383 + MPP19_NF_IO1,
384 + MPP20_SATA1_ACTn,
385 + MPP21_SATA0_ACTn,
386 + MPP22_GPIO, /* Green LED */
387 + MPP23_GPIO,
388 + MPP24_GPIO, /* Red LED */
389 + MPP25_GPIO,
390 + MPP26_GPIO,
391 + MPP27_GPIO,
392 + MPP28_GPIO,
393 + MPP29_GPIO, /* Eject button */
394 + MPP30_GPIO,
395 + MPP31_GPIO,
396 + MPP32_GPIO,
397 + MPP33_GPIO,
398 + MPP34_GPIO,
399 + MPP35_GPIO, /* FR6192 has only 36 GPIOs */
400 + 0
401 + };
402 + kirkwood_mpp_conf(kwmpp_config, NULL);
403 +
404 + return 0;
405 +}
406 +
407 +int board_init(void)
408 +{
409 + /* Boot parameters address */
410 + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
411 +
412 + kw_gpio_set_valid(20, 1);
413 + kw_gpio_set_valid(21, 1);
414 + kw_gpio_set_valid(22, 1);
415 + kw_gpio_set_valid(24, 1);
416 +
417 + return 0;
418 +}
419 +
420 +#ifdef CONFIG_RESET_PHY_R
421 +/* Configure and initialize PHY */
422 +void reset_phy(void)
423 +{
424 + u16 reg;
425 + u16 devadr;
426 + char *name = "egiga0";
427 +
428 + if (miiphy_set_current_dev(name))
429 + return;
430 +
431 + /* command to read PHY dev address */
432 + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
433 + printf("Err..(%s) could not read PHY dev address\n", __func__);
434 + return;
435 + }
436 +
437 + /*
438 + * Enable RGMII delay on Tx and Rx for CPU port
439 + * Ref: sec 4.7.2 of chip datasheet
440 + */
441 + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
442 + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
443 + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
444 + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
445 + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
446 +
447 + /* reset the phy */
448 + miiphy_reset(name, devadr);
449 +
450 + debug("88E1116 Initialized on %s\n", name);
451 +}
452 +#endif /* CONFIG_RESET_PHY_R */
453 +
454 +#ifdef CONFIG_KIRKWOOD_MMC
455 +int board_mmc_init(bd_t *bis)
456 +{
457 + kw_mmc_initialize(bis);
458 + return 0;
459 +}
460 +#endif /* CONFIG_KIRKWOOD_MMC */
461 +
462 +
463 +#define GREEN_LED (1 << 22)
464 +#define RED_LED (1 << 24)
465 +#define BOTH_LEDS (GREEN_LED | RED_LED)
466 +#define NEITHER_LED 0
467 +
468 +static void set_leds(u32 leds, u32 blinking)
469 +{
470 + struct kwgpio_registers *r;
471 + u32 oe;
472 + u32 bl;
473 +
474 + r = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
475 + oe = readl(&r->oe) | BOTH_LEDS;
476 + writel(oe & ~leds, &r->oe); /* active low */
477 + bl = readl(&r->blink_en) & ~BOTH_LEDS;
478 + writel(bl | blinking, &r->blink_en);
479 +}
480 +
481 +void show_boot_progress(int val)
482 +{
483 + switch (val) {
484 + case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
485 + set_leds(BOTH_LEDS, NEITHER_LED);
486 + break;
487 + case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
488 + set_leds(GREEN_LED, GREEN_LED);
489 + break;
490 + default:
491 + if (val < 0) /* error */
492 + set_leds(RED_LED, RED_LED);
493 + break;
494 + }
495 +}
496 +
497 +#if defined(CONFIG_KIRKWOOD_GPIO)
498 +/* Return GPIO button status */
499 +/*
500 +un-pressed:
501 + gpio-29 (Eject Button ) in hi (act lo) - IRQ edge (clear )
502 +pressed
503 + gpio-29 (Eject Button ) in lo (act hi) - IRQ edge (clear )
504 +*/
505 +
506 +static int
507 +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
508 +{
509 + if (strcmp(argv[1], "eject") == 0) {
510 + kw_gpio_set_valid(BTN_EJECT, GPIO_INPUT_OK);
511 + kw_gpio_direction_input(BTN_EJECT);
512 + return kw_gpio_get_value(BTN_EJECT);
513 + }
514 + else
515 + return -1;
516 +}
517 +
518 +
519 +U_BOOT_CMD(button, 2, 0, do_read_button,
520 + "Return GPIO button status 0=off 1=on",
521 + "- button eject: test buttons states\n"
522 +);
523 +
524 +#endif
525 --- /dev/null
526 +++ b/board/cloudengines/pogoplugv4/pogoplugv4.h
527 @@ -0,0 +1,50 @@
528 +/*
529 + * Copyright (C) 2016
530 + * bodhi <mibodhi@gmail.com>
531 + *
532 + * Copyright (C) 2012
533 + * David Purdy <david.c.purdy@gmail.com>
534 + *
535 + * Based on Kirkwood support:
536 + * (C) Copyright 2009
537 + * Marvell Semiconductor <www.marvell.com>
538 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
539 + *
540 + * See file CREDITS for list of people who contributed to this
541 + * project.
542 + *
543 + * This program is free software; you can redistribute it and/or
544 + * modify it under the terms of the GNU General Public License as
545 + * published by the Free Software Foundation; either version 2 of
546 + * the License, or (at your option) any later version.
547 + *
548 + * This program is distributed in the hope that it will be useful,
549 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
550 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
551 + * GNU General Public License for more details.
552 + *
553 + * You should have received a copy of the GNU General Public License
554 + * along with this program; If not, see <http://www.gnu.org/licenses/>.
555 + */
556 +
557 +#ifndef __POGOPLUGV4_H
558 +#define __POGOPLUGV4_H
559 +
560 +/* GPIO configuration */
561 +#define POGOPLUGV4_OE_LOW (~(0))
562 +#define POGOPLUGV4_OE_HIGH (~(0))
563 +#define POGOPLUGV4_OE_VAL_LOW (1 << 29)
564 +#define POGOPLUGV4_OE_VAL_HIGH 0
565 +
566 +/* PHY related */
567 +#define MV88E1116_LED_FCTRL_REG 10
568 +#define MV88E1116_CPRSP_CR3_REG 21
569 +#define MV88E1116_MAC_CTRL_REG 21
570 +#define MV88E1116_PGADR_REG 22
571 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
572 +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
573 +
574 +/* button */
575 +#define BTN_EJECT 29
576 +
577 +#endif /* __POGOPLUGV4_H */
578 --- /dev/null
579 +++ b/configs/pogoplugv4_defconfig
580 @@ -0,0 +1,35 @@
581 +CONFIG_ARM=y
582 +CONFIG_KIRKWOOD=y
583 +CONFIG_TARGET_POGOPLUGV4=y
584 +CONFIG_SYS_PROMPT="pogoplugv4> "
585 +CONFIG_IDENT_STRING="\nPogoplug V4"
586 +CONFIG_BOOTDELAY=3
587 +# CONFIG_CMD_IMLS is not set
588 +# CONFIG_CMD_FLASH is not set
589 +CONFIG_SYS_NS16550=y
590 +CONFIG_CMD_FDT=y
591 +CONFIG_OF_LIBFDT=y
592 +CONFIG_CMD_SETEXPR=y
593 +CONFIG_CMD_DHCP=y
594 +CONFIG_CMD_MII=y
595 +CONFIG_CMD_PING=y
596 +CONFIG_CMD_DNS=y
597 +CONFIG_CMD_SNTP=y
598 +CONFIG_CMD_USB=y
599 +CONFIG_CMD_DATE=y
600 +CONFIG_CMD_EXT2=y
601 +CONFIG_CMD_EXT4=y
602 +CONFIG_CMD_FAT=y
603 +CONFIG_CMD_JFFS2=y
604 +CONFIG_CMD_MTDPARTS=y
605 +CONFIG_CMD_ENV=y
606 +CONFIG_CMD_NAND=y
607 +CONFIG_CMD_MMC=y
608 +CONFIG_EFI_PARTITION=y
609 +CONFIG_ENV_IS_IN_NAND=y
610 +CONFIG_CMD_UBI=y
611 +CONFIG_USB=y
612 +CONFIG_USB_EHCI_HCD=y
613 +CONFIG_USB_STORAGE=y
614 +CONFIG_LZMA=y
615 +CONFIG_LZO=y
616 --- a/drivers/gpio/kw_gpio.c
617 +++ b/drivers/gpio/kw_gpio.c
618 @@ -148,3 +148,36 @@ void kw_gpio_set_blink(unsigned pin, int
619 /* Set blinking. */
620 __set_blinking(pin, blink);
621 }
622 +
623 +
624 +/*
625 + * Hooks to GENERIC_GPIO primitives
626 + */
627 +
628 +int gpio_direction_input(unsigned pin)
629 +{
630 + return kw_gpio_direction_input(pin);
631 +}
632 +
633 +int gpio_direction_output(unsigned pin, int value)
634 +{
635 + return kw_gpio_direction_output(pin, value);
636 +}
637 +
638 +void gpio_set_value(unsigned pin, int value) {
639 + kw_gpio_set_value(pin, value);
640 +}
641 +
642 +int gpio_get_value(unsigned pin) {
643 + return kw_gpio_get_value(pin);
644 +}
645 +
646 +int gpio_request(unsigned gpio, const char *label)
647 +{
648 + return 0;
649 +}
650 +
651 +int gpio_free(unsigned gpio)
652 +{
653 + return 0;
654 +}
655 --- a/drivers/mmc/Makefile
656 +++ b/drivers/mmc/Makefile
657 @@ -61,6 +61,7 @@ obj-$(CONFIG_MMC_SDHCI_TANGIER) += tang
658 obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o
659 obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o
660 obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o
661 +obj-$(CONFIG_KIRKWOOD_MMC) += kirkwood_mmc.o
662
663 obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
664 obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
665 --- /dev/null
666 +++ b/drivers/mmc/kirkwood_mmc.c
667 @@ -0,0 +1,482 @@
668 +/*
669 + * (C) Copyright 2014 bodhi <mibodhi@gmail.com>
670 + *
671 + * Based on
672 + *
673 + * (C) Copyright 2014 <ebbes.ebbes@gmail.com>
674 + *
675 + * Based on
676 + *
677 + * Driver for Marvell SDIO/MMC controller
678 + *
679 + * (C) Copyright 2012
680 + * Marvell Semiconductor <www.marvell.com>
681 + * Written-by: Gérald Kerma <uboot at doukki.net>
682 + * See file CREDITS for list of people who contributed to this
683 + * project.
684 + *
685 + * This program is free software; you can redistribute it and/or
686 + * modify it under the terms of the GNU General Public License as
687 + * published by the Free Software Foundation; either version 2 of
688 + * the License, or (at your option) any later version.
689 + *
690 + * This program is distributed in the hope that it will be useful,
691 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
692 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
693 + * GNU General Public License for more details.
694 + *
695 + * You should have received a copy of the GNU General Public License
696 + * along with this program; if not, write to the Free Software
697 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
698 + * MA 02111-1307 USA
699 + */
700 +
701 +#include <common.h>
702 +#include <malloc.h>
703 +#include <part.h>
704 +#include <mmc.h>
705 +#include <asm/io.h>
706 +#include <asm/arch/cpu.h>
707 +#include <asm/arch/soc.h>
708 +
709 +#include <kirkwood_mmc.h>
710 +
711 +#define DRIVER_NAME "kwsdio"
712 +
713 +static int kw_mmc_setup_data(struct mmc_data *data)
714 +{
715 + u32 ctrl_reg;
716 +
717 +#ifdef DEBUG
718 + printf("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME,
719 + (data->flags & MMC_DATA_READ) ? "read" : "write",
720 + data->blocks, data->blocksize);
721 +#endif
722 +
723 + /* default to maximum timeout */
724 + ctrl_reg = kwsd_read(SDIO_HOST_CTRL);
725 + ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
726 + kwsd_write(SDIO_HOST_CTRL, ctrl_reg);
727 +
728 + if (data->flags & MMC_DATA_READ) {
729 + kwsd_write(SDIO_SYS_ADDR_LOW,(u32)data->dest & 0xffff);
730 + kwsd_write(SDIO_SYS_ADDR_HI,(u32)data->dest >> 16);
731 + } else {
732 + kwsd_write(SDIO_SYS_ADDR_LOW,(u32)data->src & 0xffff);
733 + kwsd_write(SDIO_SYS_ADDR_HI,(u32)data->src >> 16);
734 + }
735 +
736 + kwsd_write(SDIO_BLK_COUNT, data->blocks);
737 + kwsd_write(SDIO_BLK_SIZE, data->blocksize);
738 +
739 + return 0;
740 +}
741 +
742 +static int kw_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
743 +{
744 + int timeout = 10;
745 + int err;
746 + ushort waittype = 0;
747 + ushort resptype = 0;
748 + ushort xfertype = 0;
749 + ushort resp_indx = 0;
750 +
751 +#ifdef CONFIG_MMC_DEBUG
752 + printf("cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n", cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
753 +#endif
754 +
755 + udelay(10000);
756 +
757 +#ifdef CONFIG_MMC_DEBUG
758 + printf("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME, cmd->cmdidx, kwsd_read(SDIO_HW_STATE));
759 +#endif
760 +
761 + /* Checking if card is busy */
762 + while ((kwsd_read(SDIO_HW_STATE) & CARD_BUSY)) {
763 + if (timeout == 0) {
764 + printf("%s: card busy!\n", DRIVER_NAME);
765 + return -1;
766 + }
767 + timeout--;
768 + udelay(1000);
769 + }
770 +
771 + /* Set up for a data transfer if we have one */
772 + if (data) {
773 + if ((err = kw_mmc_setup_data(data)))
774 + return err;
775 + }
776 +
777 + resptype = SDIO_CMD_INDEX(cmd->cmdidx);
778 +
779 + /* Analyzing resptype/xfertype/waittype for the command */
780 + if (cmd->resp_type & MMC_RSP_BUSY)
781 + resptype |= SDIO_CMD_RSP_48BUSY;
782 + else if (cmd->resp_type & MMC_RSP_136)
783 + resptype |= SDIO_CMD_RSP_136;
784 + else if (cmd->resp_type & MMC_RSP_PRESENT)
785 + resptype |= SDIO_CMD_RSP_48;
786 + else
787 + resptype |= SDIO_CMD_RSP_NONE;
788 +
789 + if (cmd->resp_type & MMC_RSP_CRC)
790 + resptype |= SDIO_CMD_CHECK_CMDCRC;
791 +
792 + if (cmd->resp_type & MMC_RSP_OPCODE)
793 + resptype |= SDIO_CMD_INDX_CHECK;
794 +
795 + if (cmd->resp_type & MMC_RSP_PRESENT) {
796 + resptype |= SDIO_UNEXPECTED_RESP;
797 + waittype |= SDIO_NOR_UNEXP_RSP;
798 + }
799 +
800 + if (data) {
801 + resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
802 + xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
803 + if (data->flags & MMC_DATA_READ) {
804 + xfertype |= SDIO_XFER_MODE_TO_HOST;
805 + waittype = SDIO_NOR_DMA_INI;
806 + } else
807 + waittype |= SDIO_NOR_XFER_DONE;
808 + } else
809 + waittype |= SDIO_NOR_CMD_DONE;
810 +
811 + /* Setting cmd arguments */
812 + kwsd_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
813 + kwsd_write(SDIO_ARG_HI, cmd->cmdarg >> 16);
814 +
815 + /* Setting Xfer mode */
816 + kwsd_write(SDIO_XFER_MODE, xfertype);
817 +
818 + kwsd_write(SDIO_NOR_INTR_STATUS, ~SDIO_NOR_CARD_INT);
819 + kwsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
820 +
821 + /* Sending command */
822 + kwsd_write(SDIO_CMD, resptype);
823 +/*
824 + kwsd_write(SDIO_CMD, KW_MMC_MAKE_CMD(cmd->cmdidx, resptype));
825 +*/
826 +
827 + kwsd_write(SDIO_NOR_INTR_EN, SDIO_POLL_MASK);
828 + kwsd_write(SDIO_ERR_INTR_EN, SDIO_POLL_MASK);
829 +
830 + /* Waiting for completion */
831 + timeout = 1000000;
832 +
833 + while (!((kwsd_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
834 + if (kwsd_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
835 +#ifdef DEBUG
836 + printf("%s: kw_mmc_send_cmd: error! cmdidx : %d, err reg: %04x\n", DRIVER_NAME, cmd->cmdidx,
837 +wsd_read(SDIO_ERR_INTR_STATUS));
838 +#endif
839 + if (kwsd_read(SDIO_ERR_INTR_STATUS) & (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) {
840 + return -ETIMEDOUT;
841 + }
842 + return -ECOMM;
843 + }
844 +
845 + timeout--;
846 + udelay(1);
847 + if (timeout <= 0) {
848 + printf("%s: command timed out\n", DRIVER_NAME);
849 + return -ETIMEDOUT;
850 + }
851 + }
852 +
853 + /* Handling response */
854 + if (cmd->resp_type & MMC_RSP_136) {
855 + uint response[8];
856 + for (resp_indx = 0; resp_indx < 8; resp_indx++)
857 + response[resp_indx] = kwsd_read(SDIO_RSP(resp_indx));
858 +
859 + cmd->response[0] = ((response[0] & 0x03ff) << 22) |
860 + ((response[1] & 0xffff) << 6) |
861 + ((response[2] & 0xfc00) >> 10);
862 + cmd->response[1] = ((response[2] & 0x03ff) << 22) |
863 + ((response[3] & 0xffff) << 6) |
864 + ((response[4] & 0xfc00) >> 10);
865 + cmd->response[2] = ((response[4] & 0x03ff) << 22) |
866 + ((response[5] & 0xffff) << 6) |
867 + ((response[6] & 0xfc00) >> 10);
868 + cmd->response[3] = ((response[6] & 0x03ff) << 22) |
869 + ((response[7] & 0x3fff) << 8);
870 + } else if (cmd->resp_type & MMC_RSP_PRESENT) {
871 + uint response[3];
872 + for (resp_indx = 0; resp_indx < 3; resp_indx++)
873 + response[resp_indx] = kwsd_read(SDIO_RSP(resp_indx));
874 +
875 + cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) |
876 + ((response[1] & 0xffff) << (14 - 8)) |
877 + ((response[0] & 0x03ff) << (30 - 8));
878 + cmd->response[1] = ((response[0] & 0xfc00) >> 10);
879 + cmd->response[2] = 0;
880 + cmd->response[3] = 0;
881 + }
882 +
883 +#ifdef CONFIG_MMC_DEBUG
884 + printf("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
885 + printf("[0x%x] ", cmd->response[0]);
886 + printf("[0x%x] ", cmd->response[1]);
887 + printf("[0x%x] ", cmd->response[2]);
888 + printf("[0x%x] ", cmd->response[3]);
889 + printf("\n");
890 +#endif
891 +
892 + return 0;
893 +}
894 +
895 +#if 0
896 +/* Disable these three functions as they are not used anyway */
897 +
898 +static void kwsd_power_up(void)
899 +{
900 +#ifdef DEBUG
901 + printf("%s: power up\n", DRIVER_NAME);
902 +#endif
903 + /* disable interrupts */
904 + kwsd_write(SDIO_NOR_INTR_EN, 0);
905 + kwsd_write(SDIO_ERR_INTR_EN, 0);
906 +
907 + /* SW reset */
908 + kwsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
909 +
910 + kwsd_write(SDIO_XFER_MODE, 0);
911 +
912 + /* enable status */
913 + kwsd_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
914 + kwsd_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
915 +
916 + /* enable interrupts status */
917 + kwsd_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
918 + kwsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
919 +}
920 +
921 +static void kwsd_power_down(void)
922 +{
923 +#ifdef DEBUG
924 + printf("%s: power down\n", DRIVER_NAME);
925 +#endif
926 + /* disable interrupts */
927 + kwsd_write(SDIO_NOR_INTR_EN, 0);
928 + kwsd_write(SDIO_ERR_INTR_EN, 0);
929 +
930 + /* SW reset */
931 + kwsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
932 +
933 + kwsd_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
934 +
935 + /* disable status */
936 + kwsd_write(SDIO_NOR_STATUS_EN, 0);
937 + kwsd_write(SDIO_ERR_STATUS_EN, 0);
938 +
939 + /* enable interrupts status */
940 + kwsd_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
941 + kwsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
942 +}
943 +
944 +static u32 kw_mmc_get_base_clock(void)
945 +{
946 + /* Original version did a check for board device id and revision id
947 + * and assigned one of these clocks:
948 + * KW_MMC_BASE_FAST_CLK_100 (revid == 0 && devid != MV88F6282_DEV_ID)
949 + * KW_MMC_BASE_FAST_CLK_200 (revid != 0 || devid == MV88F6282_DEV_ID)
950 + * However, this check was disabled and
951 + * KW_MMC_BASE_FAST_CLOCK
952 + * was returned in every case.
953 + * Therefore, all of the dead logic was removed. */
954 + return KW_MMC_BASE_FAST_CLOCK;
955 +}
956 +#endif /* #if 0 */
957 +
958 +static inline u32 kw_mmc_get_base_clock(void)
959 +{
960 + /* get MMC base clock. If any logic other than just returning
961 + * a fixed value is ever used, remove inline modifier. */
962 +
963 + /* Possible values:
964 + * - KW_MMC_BASE_FAST_CLOCK (166 MHz)
965 + * - KW_MMC_BASE_FAST_CLK_100 (100 MHz)
966 + * - KW_MMC_BASE_FAST_CLK_200 (200 MHz)
967 + *
968 + * Tests have shown that 200 MHz is more reliable than
969 + * 166 MHz, so this value is used. */
970 + return KW_MMC_BASE_FAST_CLK_200;
971 +}
972 +
973 +static void kw_mmc_set_clk(unsigned int clock)
974 +{
975 + unsigned int m;
976 +
977 + if (clock == 0) {
978 +#ifdef DEBUG
979 + printf("%s: clock off\n", DRIVER_NAME);
980 +#endif
981 + kwsd_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
982 + kwsd_write(SDIO_CLK_DIV, KW_MMC_BASE_DIV_MAX);
983 + } else {
984 + m = kw_mmc_get_base_clock() / (2 * clock) - 1;
985 + if (m > KW_MMC_BASE_DIV_MAX)
986 + m = KW_MMC_BASE_DIV_MAX;
987 +#ifdef DEBUG
988 + printf("%s: kw_mmc_set_clk: base = %d dividor = 0x%x clock=%d\n", DRIVER_NAME,
989 +w_mmc_get_base_clock(), m, clock);
990 +#endif
991 + kwsd_write(SDIO_CLK_DIV, m & KW_MMC_BASE_DIV_MAX);
992 + }
993 + udelay(10000);
994 +}
995 +
996 +static void kw_mmc_set_bus(unsigned int bus)
997 +{
998 + u32 ctrl_reg = 0;
999 +
1000 + ctrl_reg = kwsd_read(SDIO_HOST_CTRL);
1001 + ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
1002 +
1003 + switch (bus) {
1004 + case 4:
1005 + ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
1006 + break;
1007 + case 1:
1008 + default:
1009 + ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
1010 + }
1011 + /* default transfer mode */
1012 + ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
1013 + ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
1014 +
1015 + /* default to maximum timeout */
1016 + ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
1017 +
1018 + ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
1019 +
1020 + ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
1021 +
1022 + /*
1023 + * The HI_SPEED_EN bit is causing trouble with many (but not all)
1024 + * high speed SD, SDHC and SDIO cards. Not enabling that bit
1025 + * makes all cards work. So let's just ignore that bit for now
1026 + * and revisit this issue if problems for not enabling this bit
1027 + * are ever reported.
1028 + */
1029 +#if 0
1030 + if (ios->timing == MMC_TIMING_MMC_HS ||
1031 + ios->timing == MMC_TIMING_SD_HS)
1032 + ctrl_reg |= SDIO_HOST_CTRL_HI_SPEED_EN;
1033 +#endif
1034 +
1035 +#ifdef DEBUG
1036 + printf("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg,
1037 + (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
1038 + "push-pull" : "open-drain",
1039 + (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
1040 + "4bit-width" : "1bit-width",
1041 + (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
1042 + "high-speed" : "");
1043 +#endif
1044 +
1045 + kwsd_write(SDIO_HOST_CTRL, ctrl_reg);
1046 + udelay(10000);
1047 +}
1048 +
1049 +static void kw_mmc_set_ios(struct mmc *mmc)
1050 +{
1051 +#ifdef DEBUG
1052 + printf("%s: bus[%d] clock[%d]\n", DRIVER_NAME, mmc->bus_width, mmc->clock);
1053 +#endif
1054 + kw_mmc_set_bus(mmc->bus_width);
1055 + kw_mmc_set_clk(mmc->clock);
1056 +}
1057 +
1058 +static int kw_mmc_init(struct mmc *mmc)
1059 +{
1060 +#ifdef DEBUG
1061 + printf("%s: kw_mmc_init\n", DRIVER_NAME);
1062 +#endif
1063 +
1064 + /*
1065 + * Setting host parameters
1066 + * Initial Host Ctrl : Timeout : max , Normal Speed mode, 4-bit data mode
1067 + * Big Endian, SD memory Card, Push_pull CMD Line
1068 + */
1069 + kwsd_write(SDIO_HOST_CTRL,
1070 + SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
1071 + SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
1072 + SDIO_HOST_CTRL_BIG_ENDIAN |
1073 + SDIO_HOST_CTRL_PUSH_PULL_EN |
1074 + SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
1075 +
1076 + kwsd_write(SDIO_CLK_CTRL, 0);
1077 +
1078 + /* enable status */
1079 + kwsd_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
1080 + kwsd_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
1081 +
1082 + /* disable interrupts */
1083 + kwsd_write(SDIO_NOR_INTR_EN, 0);
1084 + kwsd_write(SDIO_ERR_INTR_EN, 0);
1085 +
1086 + /* SW reset */
1087 + kwsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
1088 +
1089 + udelay(10000);
1090 + return 0;
1091 +}
1092 +
1093 +int kw_mmc_initialize(bd_t *bis)
1094 +{
1095 + struct mmc *mmc = NULL;
1096 + struct mmc_config *cfg = NULL;
1097 + struct mmc_ops *ops = NULL;
1098 + char *name = NULL;
1099 +
1100 +#ifdef DEBUG
1101 + printf("%s: %s base_clock = %d\n", DRIVER_NAME, kirkwood_id(), kw_mmc_get_base_clock());
1102 +#endif
1103 + mmc = malloc(sizeof(struct mmc));
1104 + if (!mmc)
1105 + return -1;
1106 + memset(mmc, 0, sizeof(*mmc));
1107 +
1108 + cfg = malloc(sizeof(*cfg));
1109 + if (cfg == NULL)
1110 + return -1;
1111 + memset(cfg, 0, sizeof(*cfg));
1112 + mmc->cfg = cfg; /* provided configuration */
1113 +
1114 + ops = malloc(sizeof(*ops));
1115 + if (ops == NULL)
1116 + return -1;
1117 + memset(ops, 0, sizeof(*ops));
1118 + cfg->ops = ops;
1119 +
1120 + name = malloc(sizeof(DRIVER_NAME)+1);
1121 + if (name == NULL)
1122 + return -1;
1123 + cfg->name = name;
1124 +
1125 + sprintf(cfg->name, DRIVER_NAME);
1126 +
1127 + ops->send_cmd = kw_mmc_send_cmd;
1128 + ops->set_ios = kw_mmc_set_ios;
1129 + ops->init = kw_mmc_init;
1130 +
1131 + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1132 + cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS;
1133 +
1134 + cfg->f_min = kw_mmc_get_base_clock()/KW_MMC_BASE_DIV_MAX;
1135 + cfg->f_max = KW_MMC_CLOCKRATE_MAX;
1136 + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1137 +
1138 + mmc = mmc_create (cfg, NULL);
1139 +
1140 + if (mmc == NULL) {
1141 + free(name);
1142 + free(ops);
1143 + free(cfg);
1144 + printf("\nFailed to Initialize MMC\n");
1145 + return -1;
1146 + }
1147 +
1148 + return 0;
1149 +}
1150 --- a/include/configs/mv-common.h
1151 +++ b/include/configs/mv-common.h
1152 @@ -130,4 +130,16 @@
1153 #define CONFIG_MTD_PARTITIONS
1154 #endif
1155
1156 +/*
1157 + * Kirkwood MMC
1158 + */
1159 +#if defined(CONFIG_KIRKWOOD) && defined(CONFIG_CMD_MMC)
1160 +#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
1161 +#endif /* defined(CONFIG_KIRKWOOD) && defined(CONFIG_CMD_MMC) */
1162 +
1163 +/*
1164 + * GPIO command for all Kirkwood boxes
1165 + */
1166 +#define CONFIG_CMD_GPIO
1167 +
1168 #endif /* _MV_COMMON_H */
1169 --- /dev/null
1170 +++ b/include/configs/pogoplugv4.h
1171 @@ -0,0 +1,132 @@
1172 +/*
1173 + * Copyright (C) 2014-2016 bodhi <mibodhi@gmail.com>
1174 + * Based on
1175 + *
1176 + * Copyright (C) 2012
1177 + * David Purdy <david.c.purdy@gmail.com>
1178 + *
1179 + * Based on Kirkwood support:
1180 + * (C) Copyright 2009
1181 + * Marvell Semiconductor <www.marvell.com>
1182 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
1183 + *
1184 + * See file CREDITS for list of people who contributed to this
1185 + * project.
1186 + *
1187 + * This program is free software; you can redistribute it and/or
1188 + * modify it under the terms of the GNU General Public License as
1189 + * published by the Free Software Foundation; either version 2 of
1190 + * the License, or (at your option) any later version.
1191 + *
1192 + * This program is distributed in the hope that it will be useful,
1193 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1194 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1195 + * GNU General Public License for more details.
1196 + *
1197 + * You should have received a copy of the GNU General Public License
1198 + * along with this program; If not, see <http://www.gnu.org/licenses/>.
1199 + */
1200 +
1201 +#ifndef _CONFIG_POGOPLUGV4_H
1202 +#define _CONFIG_POGOPLUGV4_H
1203 +
1204 +/*
1205 + * Machine type definition and ID
1206 + */
1207 +#define MACH_TYPE_POGOPLUGV4 3960
1208 +#define CONFIG_MACH_TYPE MACH_TYPE_POGOPLUGV4
1209 +
1210 +/*
1211 + * High Level Configuration Options (easy to change)
1212 + */
1213 +#define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */
1214 +#define CONFIG_KW88F6192 /* SOC Name */
1215 +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
1216 +
1217 +/*
1218 + * Commands configuration
1219 + */
1220 +
1221 +#define CONFIG_SYS_LONGHELP
1222 +#define CONFIG_PREBOOT
1223 +
1224 +/*
1225 + * mv-common.h should be defined after CMD configs since it used them
1226 + * to enable certain macros
1227 + */
1228 +#include "mv-common.h"
1229 +
1230 +/*
1231 + * Environment variables configurations
1232 + */
1233 +#ifdef CONFIG_CMD_NAND
1234 +
1235 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
1236 +
1237 +
1238 +#endif
1239 +
1240 +#define CONFIG_ENV_SIZE 0x20000 /* 128k */
1241 +#define CONFIG_ENV_ADDR 0x1c0000
1242 +#define CONFIG_ENV_OFFSET 0x1c0000 /* env starts here */
1243 +
1244 +/*
1245 + * Default environment variables
1246 + */
1247 +#define CONFIG_BOOTCOMMAND \
1248 + "usb reset ; " \
1249 + "fatload usb 0:1 0x2000000 initramfs.bin ; "\
1250 + "bootm 0x2000000 ; " \
1251 + "ubi part ubi; " \
1252 + "ubi read 0x800000 kernel; " \
1253 + "bootm 0x800000"
1254 +
1255 +#define CONFIG_MTDPARTS \
1256 + "mtdparts=orion_nand:" \
1257 + "0x1c0000(uboot)," \
1258 + "0x40000(uboot_env)," \
1259 + "0x7e00000(ubi)\0"
1260 +
1261 +#define CONFIG_EXTRA_ENV_SETTINGS \
1262 + "console=console=ttyS0,115200\0" \
1263 + "mtdids=nand0=orion_nand\0" \
1264 + "mtdparts="CONFIG_MTDPARTS \
1265 + "bootargs_root=\0"
1266 +
1267 +/*
1268 + * Ethernet Driver configuration
1269 + */
1270 +#ifdef CONFIG_CMD_NET
1271 +#define CONFIG_NETCONSOLE
1272 +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
1273 +#define CONFIG_PHY_BASE_ADR 0
1274 +#endif /* CONFIG_CMD_NET */
1275 +
1276 +/*
1277 + * File system
1278 + */
1279 +#define CONFIG_JFFS2_NAND
1280 +#define CONFIG_JFFS2_LZO
1281 +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
1282 +#define CONFIG_MTD_PARTITIONS
1283 +
1284 +/*
1285 + * SATA
1286 + */
1287 +#ifdef CONFIG_MVSATA_IDE
1288 +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
1289 +#endif
1290 +
1291 +/*
1292 + * Date Time
1293 + */
1294 +#ifdef CONFIG_CMD_DATE
1295 +#define CONFIG_RTC_MV
1296 +#endif /* CONFIG_CMD_DATE */
1297 +
1298 +/*
1299 + * Kirkwood GPIO
1300 + */
1301 +#define CONFIG_KIRKWOOD_GPIO
1302 +
1303 +#endif /* _CONFIG_POGOPLUGV4_H */
1304 --- /dev/null
1305 +++ b/include/kirkwood_mmc.h
1306 @@ -0,0 +1,268 @@
1307 +/*
1308 + * (C) Copyright 2014 <ebbes.ebbes@gmail.com>
1309 + *
1310 + * Based on
1311 + *
1312 + * (C) Copyright 2012
1313 + * Marvell Semiconductor <www.marvell.com>
1314 + * Written-by: Gérald Kerma <uboot at doukki.net>
1315 + * See file CREDITS for list of people who contributed to this
1316 + * project.
1317 + *
1318 + * This program is free software; you can redistribute it and/or
1319 + * modify it under the terms of the GNU General Public License as
1320 + * published by the Free Software Foundation; either version 2 of
1321 + * the License, or (at your option) any later version.
1322 + *
1323 + * This program is distributed in the hope that it will be useful,
1324 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1325 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1326 + * GNU General Public License for more details.
1327 + *
1328 + * You should have received a copy of the GNU General Public License
1329 + * along with this program; if not, write to the Free Software
1330 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1331 + * MA 02111-1307 USA
1332 + */
1333 +
1334 +#ifndef __KIRKWOOD_MMC_H__
1335 +#define __KIRKWOOD_MMC_H__
1336 +
1337 +/*
1338 + * Clock rates
1339 + */
1340 +
1341 +#define KW_MMC_CLOCKRATE_MAX 50000000
1342 +#define KW_MMC_BASE_DIV_MAX 0x7ff
1343 +#define KW_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK
1344 +#define KW_MMC_BASE_FAST_CLK_100 100000000
1345 +#define KW_MMC_BASE_FAST_CLK_200 200000000
1346 +
1347 +/*
1348 + * Macros
1349 + */
1350 +#define kwsd_write(offs, val) writel(val, CONFIG_SYS_MMC_BASE + (offs))
1351 +#define kwsd_read(offs) readl(CONFIG_SYS_MMC_BASE + (offs))
1352 +
1353 +#define KW_MMC_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
1354 +
1355 +/* SDIO register */
1356 +#define SDIO_SYS_ADDR_LOW 0x000
1357 +#define SDIO_SYS_ADDR_HI 0x004
1358 +#define SDIO_BLK_SIZE 0x008
1359 +#define SDIO_BLK_COUNT 0x00c
1360 +#define SDIO_ARG_LOW 0x010
1361 +#define SDIO_ARG_HI 0x014
1362 +#define SDIO_XFER_MODE 0x018
1363 +#define SDIO_CMD 0x01c
1364 +#define SDIO_RSP(i) (0x020 + ((i)<<2))
1365 +#define SDIO_RSP0 0x020
1366 +#define SDIO_RSP1 0x024
1367 +#define SDIO_RSP2 0x028
1368 +#define SDIO_RSP3 0x02c
1369 +#define SDIO_RSP4 0x030
1370 +#define SDIO_RSP5 0x034
1371 +#define SDIO_RSP6 0x038
1372 +#define SDIO_RSP7 0x03c
1373 +#define SDIO_BUF_DATA_PORT 0x040
1374 +#define SDIO_RSVED 0x044
1375 +#define SDIO_HW_STATE 0x048
1376 +#define SDIO_PRESENT_STATE0 0x048
1377 +#define SDIO_PRESENT_STATE1 0x04c
1378 +#define SDIO_HOST_CTRL 0x050
1379 +#define SDIO_BLK_GAP_CTRL 0x054
1380 +#define SDIO_CLK_CTRL 0x058
1381 +#define SDIO_SW_RESET 0x05c
1382 +#define SDIO_NOR_INTR_STATUS 0x060
1383 +#define SDIO_ERR_INTR_STATUS 0x064
1384 +#define SDIO_NOR_STATUS_EN 0x068
1385 +#define SDIO_ERR_STATUS_EN 0x06c
1386 +#define SDIO_NOR_INTR_EN 0x070
1387 +#define SDIO_ERR_INTR_EN 0x074
1388 +#define SDIO_AUTOCMD12_ERR_STATUS 0x078
1389 +#define SDIO_CURR_BYTE_LEFT 0x07c
1390 +#define SDIO_CURR_BLK_LEFT 0x080
1391 +#define SDIO_AUTOCMD12_ARG_LOW 0x084
1392 +#define SDIO_AUTOCMD12_ARG_HI 0x088
1393 +#define SDIO_AUTOCMD12_INDEX 0x08c
1394 +#define SDIO_AUTO_RSP(i) (0x090 + ((i)<<2))
1395 +#define SDIO_AUTO_RSP0 0x090
1396 +#define SDIO_AUTO_RSP1 0x094
1397 +#define SDIO_AUTO_RSP2 0x098
1398 +#define SDIO_CLK_DIV 0x128
1399 +
1400 +#define WINDOW_CTRL(i) (0x108 + ((i) << 3))
1401 +#define WINDOW_BASE(i) (0x10c + ((i) << 3))
1402 +
1403 +/* SDIO_PRESENT_STATE */
1404 +#define CARD_BUSY (1 << 1)
1405 +#define CMD_INHIBIT (1 << 0)
1406 +#define CMD_TXACTIVE (1 << 8)
1407 +#define CMD_RXACTIVE (1 << 9)
1408 +#define CMD_AUTOCMD12ACTIVE (1 << 14)
1409 +#define CMD_BUS_BUSY (CMD_AUTOCMD12ACTIVE | \
1410 + CMD_RXACTIVE | \
1411 + CMD_TXACTIVE | \
1412 + CMD_INHIBIT | \
1413 + CARD_BUSY)
1414 +
1415 +/*
1416 + * SDIO_CMD
1417 + */
1418 +
1419 +#define SDIO_CMD_RSP_NONE (0 << 0)
1420 +#define SDIO_CMD_RSP_136 (1 << 0)
1421 +#define SDIO_CMD_RSP_48 (2 << 0)
1422 +#define SDIO_CMD_RSP_48BUSY (3 << 0)
1423 +
1424 +#define SDIO_CMD_CHECK_DATACRC16 (1 << 2)
1425 +#define SDIO_CMD_CHECK_CMDCRC (1 << 3)
1426 +#define SDIO_CMD_INDX_CHECK (1 << 4)
1427 +#define SDIO_CMD_DATA_PRESENT (1 << 5)
1428 +#define SDIO_UNEXPECTED_RESP (1 << 7)
1429 +
1430 +#define SDIO_CMD_INDEX(x) ((x) << 8)
1431 +
1432 +/*
1433 + * SDIO_XFER_MODE
1434 + */
1435 +
1436 +#define SDIO_XFER_MODE_STOP_CLK (1 << 5)
1437 +#define SDIO_XFER_MODE_HW_WR_DATA_EN (1 << 1)
1438 +#define SDIO_XFER_MODE_AUTO_CMD12 (1 << 2)
1439 +#define SDIO_XFER_MODE_INT_CHK_EN (1 << 3)
1440 +#define SDIO_XFER_MODE_TO_HOST (1 << 4)
1441 +#define SDIO_XFER_MODE_DMA (0 << 6)
1442 +
1443 +/*
1444 + * SDIO_HOST_CTRL
1445 + */
1446 +
1447 +#define SDIO_HOST_CTRL_PUSH_PULL_EN (1 << 0)
1448 +
1449 +#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY (0 << 1)
1450 +#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY (1 << 1)
1451 +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2 << 1)
1452 +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC (3 << 1)
1453 +#define SDIO_HOST_CTRL_CARD_TYPE_MASK (3 << 1)
1454 +
1455 +#define SDIO_HOST_CTRL_BIG_ENDIAN (1 << 3)
1456 +#define SDIO_HOST_CTRL_LSB_FIRST (1 << 4)
1457 +#define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT (0 << 9)
1458 +#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS (1 << 9)
1459 +#define SDIO_HOST_CTRL_HI_SPEED_EN (1 << 10)
1460 +
1461 +#define SDIO_HOST_CTRL_TMOUT_MAX 0xf
1462 +#define SDIO_HOST_CTRL_TMOUT_MASK (0xf << 11)
1463 +#define SDIO_HOST_CTRL_TMOUT(x) ((x) << 11)
1464 +#define SDIO_HOST_CTRL_TMOUT_EN (1 << 15)
1465 +
1466 +/*
1467 + * SDIO_SW_RESET
1468 + */
1469 +
1470 +#define SDIO_SW_RESET_NOW (1 << 8)
1471 +
1472 +/*
1473 + * Normal interrupt status bits
1474 + */
1475 +
1476 +#define SDIO_NOR_ERROR (1 << 15)
1477 +#define SDIO_NOR_UNEXP_RSP (1 << 14)
1478 +#define SDIO_NOR_AUTOCMD12_DONE (1 << 13)
1479 +#define SDIO_NOR_SUSPEND_ON (1 << 12)
1480 +#define SDIO_NOR_LMB_FF_8W_AVAIL (1 << 11)
1481 +#define SDIO_NOR_LMB_FF_8W_FILLED (1 << 10)
1482 +#define SDIO_NOR_READ_WAIT_ON (1 << 9)
1483 +#define SDIO_NOR_CARD_INT (1 << 8)
1484 +#define SDIO_NOR_READ_READY (1 << 5)
1485 +#define SDIO_NOR_WRITE_READY (1 << 4)
1486 +#define SDIO_NOR_DMA_INI (1 << 3)
1487 +#define SDIO_NOR_BLK_GAP_EVT (1 << 2)
1488 +#define SDIO_NOR_XFER_DONE (1 << 1)
1489 +#define SDIO_NOR_CMD_DONE (1 << 0)
1490 +
1491 +/*
1492 + * Error status bits
1493 + */
1494 +
1495 +#define SDIO_ERR_CRC_STATUS (1 << 14)
1496 +#define SDIO_ERR_CRC_STARTBIT (1 << 13)
1497 +#define SDIO_ERR_CRC_ENDBIT (1 << 12)
1498 +#define SDIO_ERR_RESP_TBIT (1 << 11)
1499 +#define SDIO_ERR_XFER_SIZE (1 << 10)
1500 +#define SDIO_ERR_CMD_STARTBIT (1 << 9)
1501 +#define SDIO_ERR_AUTOCMD12 (1 << 8)
1502 +#define SDIO_ERR_DATA_ENDBIT (1 << 6)
1503 +#define SDIO_ERR_DATA_CRC (1 << 5)
1504 +#define SDIO_ERR_DATA_TIMEOUT (1 << 4)
1505 +#define SDIO_ERR_CMD_INDEX (1 << 3)
1506 +#define SDIO_ERR_CMD_ENDBIT (1 << 2)
1507 +#define SDIO_ERR_CMD_CRC (1 << 1)
1508 +#define SDIO_ERR_CMD_TIMEOUT (1 << 0)
1509 +#define SDIO_POLL_MASK 0xffff /* enable all for polling */
1510 +
1511 +#define MMC_BLOCK_SIZE 512
1512 +
1513 +/*
1514 + * CMD12 error status bits
1515 + */
1516 +
1517 +#define SDIO_AUTOCMD12_ERR_NOTEXE (1 << 0)
1518 +#define SDIO_AUTOCMD12_ERR_TIMEOUT (1 << 1)
1519 +#define SDIO_AUTOCMD12_ERR_CRC (1 << 2)
1520 +#define SDIO_AUTOCMD12_ERR_ENDBIT (1 << 3)
1521 +#define SDIO_AUTOCMD12_ERR_INDEX (1 << 4)
1522 +#define SDIO_AUTOCMD12_ERR_RESP_T_BIT (1 << 5)
1523 +#define SDIO_AUTOCMD12_ERR_RESP_STARTBIT (1 << 6)
1524 +
1525 +#define MMC_RSP_PRESENT (1 << 0)
1526 +#define MMC_RSP_136 (1 << 1) /* 136 bit response */
1527 +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
1528 +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
1529 +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
1530 +
1531 +#define MMC_BUSMODE_OPENDRAIN 1
1532 +#define MMC_BUSMODE_PUSHPULL 2
1533 +
1534 +#define MMC_BUS_WIDTH_1 0
1535 +#define MMC_BUS_WIDTH_4 2
1536 +#define MMC_BUS_WIDTH_8 3
1537 +
1538 +#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */
1539 +#define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */
1540 +#define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */
1541 +#define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */
1542 +#define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */
1543 +#define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */
1544 +#define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */
1545 +
1546 +#define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */
1547 +#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */
1548 +#define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */
1549 +#define MMC_CAP_1_8V_DDR (1 << 11) /* can support */
1550 + /* DDR mode at 1.8V */
1551 +#define MMC_CAP_1_2V_DDR (1 << 12) /* can support */
1552 + /* DDR mode at 1.2V */
1553 +#define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */
1554 +#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */
1555 +#define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */
1556 +#define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */
1557 +#define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */
1558 +#define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */
1559 +#define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */
1560 +#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */
1561 +#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */
1562 +#define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */
1563 +#define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */
1564 +#define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */
1565 +
1566 +/*
1567 + * Functions prototypes
1568 + *
1569 + * Original patch had static function declarations in this header file.
1570 + * Those should rather not be declared in the header as they only cause compiler warnings.
1571 + */
1572 +int kw_mmc_initialize(bd_t *bis);
1573 +
1574 +#endif /* __KIRKWOOD_MMC_H__ */
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