--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "ipq8074-512m.dtsi"
+#include "ipq8074-ac-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "ZTE MF269";
+ compatible = "zte,mf269", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ label-mac-device = &dp6_syn;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " root=/dev/ubiblock0_0";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&button_pins>;
+ pinctrl-names = "default";
+
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+ };
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_power: power {
+ label = "white:power";
+ gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&tlmm {
+ button_pins: button_pins {
+ mux {
+ pins = "gpio37", "gpio46";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ i2c_pins: i2c-pins {
+ pins = "gpio21", "gpio22";
+ function = "blsp4_i2c1";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ usb_pwr_pins: usb_pwr_pins {
+ mux {
+ pins = "gpio29";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ cs-select = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:sbl1";
+ reg = <0x0 0x50000>;
+ read-only;
+ };
+
+ partition@50000 {
+ label = "0:mibib";
+ reg = <0x50000 0x10000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "0:bootconfig";
+ reg = <0x60000 0x20000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "0:bootconfig1";
+ reg = <0x80000 0x20000>;
+ read-only;
+ };
+
+ partition@a0000 {
+ label = "0:qsee";
+ reg = <0xa0000 0x180000>;
+ read-only;
+ };
+
+ partition@220000 {
+ label = "0:qsee_1";
+ reg = <0x220000 0x180000>;
+ read-only;
+ };
+
+ partition@3a0000 {
+ label = "0:devcfg";
+ reg = <0x3a0000 0x10000>;
+ read-only;
+ };
+
+ partition@3b0000 {
+ label = "0:devcfg_1";
+ reg = <0x3b0000 0x10000>;
+ read-only;
+ };
+
+ partition@3c0000 {
+ label = "0:apdp";
+ reg = <0x3c0000 0x10000>;
+ read-only;
+ };
+
+ partition@3d0000 {
+ label = "0:apdp_1";
+ reg = <0x3d0000 0x10000>;
+ read-only;
+ };
+
+ partition@3e0000 {
+ label = "0:rpm";
+ reg = <0x3e0000 0x40000>;
+ read-only;
+ };
+
+ partition@420000 {
+ label = "0:rpm_1";
+ reg = <0x420000 0x40000>;
+ read-only;
+ };
+
+ partition@460000 {
+ label = "0:cdt";
+ reg = <0x460000 0x10000>;
+ read-only;
+ };
+
+ partition@470000 {
+ label = "0:cdt_1";
+ reg = <0x470000 0x10000>;
+ read-only;
+ };
+
+ partition@480000 {
+ label = "0:appsblenv";
+ reg = <0x480000 0x10000>;
+ };
+
+ partition@490000 {
+ label = "0:appsbl";
+ reg = <0x490000 0xc0000>;
+ read-only;
+ };
+
+ partition@550000 {
+ label = "0:appsbl_1";
+ reg = <0x550000 0xc0000>;
+ read-only;
+ };
+
+ partition@610000 {
+ label = "0:art";
+ reg = <0x610000 0x40000>;
+ read-only;
+ };
+
+ partition@650000 {
+ label = "0:ethphyfw";
+ reg = <0x650000 0x80000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&blsp1_i2c5 {
+ pinctrl-0 = <&i2c_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* No driver exists */
+ aw9106: gpio-expander@5b {
+ reg = <0x5b>;
+ reset-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ /*
+ * Bootloader will find the NAND DT node by the compatible and
+ * then "fixup" it by adding the partitions from the SMEM table
+ * using the legacy bindings thus making it impossible for us
+ * to change the partition table or utilize NVMEM for calibration.
+ * So add a dummy partitions node that bootloader will populate
+ * and set it as disabled so the kernel ignores it instead of
+ * printing warnings due to the broken way bootloader adds the
+ * partitions.
+ */
+ partitions {
+ status = "disabled";
+ };
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "fota-flag";
+ reg = <0x0000000 0x00a0000>;
+ read-only;
+ };
+
+ partition@a0000 {
+ label = "mac";
+ reg = <0x00a0000 0x0080000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_mac_0: macaddr@0 {
+ compatible = "mac-base";
+ reg = <0x0 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+
+ partition@120000 {
+ label = "cfg-param";
+ reg = <0x0120000 0x1400000>;
+ read-only;
+ };
+
+ partition@1520000 {
+ label = "log";
+ reg = <0x1520000 0x0600000>;
+ read-only;
+ };
+
+ partition@1b20000 {
+ label = "oops";
+ reg = <0x1b20000 0x00a0000>;
+ read-only;
+ };
+
+ partition@1bc0000 {
+ label = "web";
+ reg = <0x1bc0000 0x0800000>;
+ read-only;
+ };
+
+ partition@23c0000 {
+ label = "ubi_kernel";
+ reg = <0x23c0000 0x3400000>;
+ };
+
+ partition@57c0000 {
+ label = "0:wififw";
+ reg = <0x57c0000 0x0800000>;
+ read-only;
+ };
+
+ /* rootfs partition is the result of squashing
+ * consecutive stock partitions:
+ * - openwrt_data (25 MiB)
+ * - data (30 MiB)
+ * - fota (99 MiB)
+ */
+ partition@5fc0000 {
+ label = "rootfs";
+ reg = <0x5fc0000 0x9a00000>;
+ };
+ };
+ };
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&usb_0 {
+ pinctrl-0 = <&usb_pwr_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ qca8081_24: ethernet-phy@24 {
+ compatible = "ethernet-phy-id004d.d101";
+ reg = <24>;
+ reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
+ };
+
+ qca8081_28: ethernet-phy@28 {
+ compatible = "ethernet-phy-id004d.d101";
+ reg = <28>;
+ reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&switch {
+ status = "okay";
+
+ switch_lan_bmp = <ESS_PORT5>; /* lan port bitmap */
+ switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
+ switch_mac_mode1 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance1*/
+ switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance2*/
+
+ qcom,port_phyinfo {
+ port@5 {
+ port_id = <5>;
+ phy_address = <24>;
+ port_mac_sel = "QGMAC_PORT";
+ };
+ port@6 {
+ port_id = <6>;
+ phy_address = <28>;
+ port_mac_sel = "QGMAC_PORT";
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp5_syn {
+ status = "okay";
+ phy-handle = <&qca8081_24>;
+ label = "lan";
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_mac_0 1>;
+};
+
+&dp6_syn {
+ status = "okay";
+ phy-handle = <&qca8081_28>;
+ label = "wan";
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_mac_0 0>;
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "ZTE-MF269";
+ qcom,ath11k-fw-memory-mode = <1>;
+};
projects / openwrt / openwrt.git / commitdiff