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d00d11d0c823f9069ec888693ad0957e228f8837
[openwrt/openwrt.git] / target / linux / realtek / files-5.10 / drivers / net / ethernet / rtl838x_eth.h
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef _RTL838X_ETH_H
4 #define _RTL838X_ETH_H
5
6 /*
7 * Register definition
8 */
9
10 /* Per port MAC control */
11 #define RTL838X_MAC_PORT_CTRL (0xd560)
12 #define RTL839X_MAC_PORT_CTRL (0x8004)
13 #define RTL930X_MAC_L2_PORT_CTRL (0x3268)
14 #define RTL930X_MAC_PORT_CTRL (0x3260)
15 #define RTL931X_MAC_L2_PORT_CTRL (0x6000)
16 #define RTL931X_MAC_PORT_CTRL (0x6004)
17
18 /* DMA interrupt control and status registers */
19 #define RTL838X_DMA_IF_CTRL (0x9f58)
20 #define RTL838X_DMA_IF_INTR_STS (0x9f54)
21 #define RTL838X_DMA_IF_INTR_MSK (0x9f50)
22
23 #define RTL839X_DMA_IF_CTRL (0x786c)
24 #define RTL839X_DMA_IF_INTR_STS (0x7868)
25 #define RTL839X_DMA_IF_INTR_MSK (0x7864)
26
27 #define RTL930X_DMA_IF_CTRL (0xe028)
28 #define RTL930X_DMA_IF_INTR_RX_RUNOUT_STS (0xe01C)
29 #define RTL930X_DMA_IF_INTR_RX_DONE_STS (0xe020)
30 #define RTL930X_DMA_IF_INTR_TX_DONE_STS (0xe024)
31 #define RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK (0xe010)
32 #define RTL930X_DMA_IF_INTR_RX_DONE_MSK (0xe014)
33 #define RTL930X_DMA_IF_INTR_TX_DONE_MSK (0xe018)
34 #define RTL930X_L2_NTFY_IF_INTR_MSK (0xe04C)
35 #define RTL930X_L2_NTFY_IF_INTR_STS (0xe050)
36
37 /* TODO: RTL931X_DMA_IF_CTRL has different bits meanings */
38 #define RTL931X_DMA_IF_CTRL (0x0928)
39 #define RTL931X_DMA_IF_INTR_RX_RUNOUT_STS (0x091c)
40 #define RTL931X_DMA_IF_INTR_RX_DONE_STS (0x0920)
41 #define RTL931X_DMA_IF_INTR_TX_DONE_STS (0x0924)
42 #define RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK (0x0910)
43 #define RTL931X_DMA_IF_INTR_RX_DONE_MSK (0x0914)
44 #define RTL931X_DMA_IF_INTR_TX_DONE_MSK (0x0918)
45 #define RTL931X_L2_NTFY_IF_INTR_MSK (0x09E4)
46 #define RTL931X_L2_NTFY_IF_INTR_STS (0x09E8)
47
48 #define RTL838X_MAC_FORCE_MODE_CTRL (0xa104)
49 #define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc)
50 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
51 #define RTL931X_MAC_FORCE_MODE_CTRL (0x0ddc)
52
53 /* MAC address settings */
54 #define RTL838X_MAC (0xa9ec)
55 #define RTL839X_MAC (0x02b4)
56 #define RTL838X_MAC_ALE (0x6b04)
57 #define RTL838X_MAC2 (0xa320)
58 #define RTL930X_MAC_L2_ADDR_CTRL (0xC714)
59 #define RTL931X_MAC_L2_ADDR_CTRL (0x135c)
60
61 /* Ringbuffer setup */
62 #define RTL838X_DMA_RX_BASE (0x9f00)
63 #define RTL839X_DMA_RX_BASE (0x780c)
64 #define RTL930X_DMA_RX_BASE (0xdf00)
65 #define RTL931X_DMA_RX_BASE (0x0800)
66
67 #define RTL838X_DMA_TX_BASE (0x9f40)
68 #define RTL839X_DMA_TX_BASE (0x784c)
69 #define RTL930X_DMA_TX_BASE (0xe000)
70 #define RTL931X_DMA_TX_BASE (0x0900)
71
72 #define RTL838X_DMA_IF_RX_RING_SIZE (0xB7E4)
73 #define RTL839X_DMA_IF_RX_RING_SIZE (0x6038)
74 #define RTL930X_DMA_IF_RX_RING_SIZE (0x7C60)
75 #define RTL931X_DMA_IF_RX_RING_SIZE (0x2080)
76
77 #define RTL838X_DMA_IF_RX_RING_CNTR (0xB7E8)
78 #define RTL839X_DMA_IF_RX_RING_CNTR (0x603c)
79 #define RTL930X_DMA_IF_RX_RING_CNTR (0x7C8C)
80 #define RTL931X_DMA_IF_RX_RING_CNTR (0x20AC)
81
82 #define RTL838X_DMA_IF_RX_CUR (0x9F20)
83 #define RTL839X_DMA_IF_RX_CUR (0x782c)
84 #define RTL930X_DMA_IF_RX_CUR (0xdf80)
85 #define RTL931X_DMA_IF_RX_CUR (0x0880)
86
87 #define RTL838X_DMA_IF_TX_CUR_DESC_ADDR_CTRL (0x9F48)
88 #define RTL930X_DMA_IF_TX_CUR_DESC_ADDR_CTRL (0xE008)
89
90 #define RTL838X_DMY_REG31 (0x3b28)
91 #define RTL838X_SDS_MODE_SEL (0x0028)
92 #define RTL838X_SDS_CFG_REG (0x0034)
93 #define RTL838X_INT_MODE_CTRL (0x005c)
94 #define RTL838X_CHIP_INFO (0x00d8)
95 #define RTL838X_SDS4_REG28 (0xef80)
96 #define RTL838X_SDS4_DUMMY0 (0xef8c)
97 #define RTL838X_SDS5_EXT_REG6 (0xf18c)
98
99 /* L2 features */
100 #define RTL839X_TBL_ACCESS_L2_CTRL (0x1180)
101 #define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2))
102 #define RTL838X_TBL_ACCESS_CTRL_0 (0x6914)
103 #define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2))
104
105 /* MAC-side link state handling */
106 #define RTL838X_MAC_LINK_STS (0xa188)
107 #define RTL839X_MAC_LINK_STS (0x0390)
108 #define RTL930X_MAC_LINK_STS (0xCB10)
109 #define RTL931X_MAC_LINK_STS (0x0ec0)
110
111 #define RTL838X_MAC_LINK_SPD_STS (0xa190)
112 #define RTL839X_MAC_LINK_SPD_STS (0x03a0)
113 #define RTL930X_MAC_LINK_SPD_STS (0xCB18)
114 #define RTL931X_MAC_LINK_SPD_STS (0x0ed0)
115
116 #define RTL838X_MAC_LINK_DUP_STS (0xa19c)
117 #define RTL839X_MAC_LINK_DUP_STS (0x03b0)
118 #define RTL930X_MAC_LINK_DUP_STS (0xCB28)
119 #define RTL931X_MAC_LINK_DUP_STS (0x0ef0)
120
121 // TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ???
122
123 #define RTL838X_MAC_TX_PAUSE_STS (0xa1a0)
124 #define RTL839X_MAC_TX_PAUSE_STS (0x03b8)
125 #define RTL930X_MAC_TX_PAUSE_STS (0xCB2C)
126 #define RTL931X_MAC_TX_PAUSE_STS (0x0ef8)
127
128 #define RTL838X_MAC_RX_PAUSE_STS (0xa1a4)
129 #define RTL839X_MAC_RX_PAUSE_STS (0xCB30)
130 #define RTL930X_MAC_RX_PAUSE_STS (0xC2F8)
131 #define RTL931X_MAC_RX_PAUSE_STS (0x0f00)
132
133 #define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04)
134 #define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08)
135
136 #define RTL930X_L2_UNKN_UC_FLD_PMSK (0x9064)
137 #define RTL931X_L2_UNKN_UC_FLD_PMSK (0xC8F4)
138
139 #define RTL839X_MAC_GLB_CTRL (0x02a8)
140 #define RTL839X_SCHED_LB_TICK_TKN_CTRL (0x60f8)
141
142 #define RTL838X_L2_TBL_FLUSH_CTRL (0x3370)
143 #define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0)
144 #define RTL930X_L2_TBL_FLUSH_CTRL (0x9404)
145 #define RTL931X_L2_TBL_FLUSH_CTRL (0xCD9C)
146
147 #define RTL930X_L2_PORT_SABLK_CTRL (0x905c)
148 #define RTL930X_L2_PORT_DABLK_CTRL (0x9060)
149
150 /* MAC link state bits */
151 #define FORCE_EN (1 << 0)
152 #define FORCE_LINK_EN (1 << 1)
153 #define NWAY_EN (1 << 2)
154 #define DUPLX_MODE (1 << 3)
155 #define TX_PAUSE_EN (1 << 6)
156 #define RX_PAUSE_EN (1 << 7)
157
158 /* L2 Notification DMA interface */
159 #define RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL (0x785C)
160 #define RTL839X_L2_NOTIFICATION_CTRL (0x7808)
161 #define RTL931X_L2_NTFY_RING_BASE_ADDR (0x09DC)
162 #define RTL931X_L2_NTFY_RING_CUR_ADDR (0x09E0)
163 #define RTL839X_L2_NOTIFICATION_CTRL (0x7808)
164 #define RTL931X_L2_NTFY_CTRL (0xCDC8)
165 #define RTL838X_L2_CTRL_0 (0x3200)
166 #define RTL839X_L2_CTRL_0 (0x3800)
167 #define RTL930X_L2_CTRL (0x8FD8)
168 #define RTL931X_L2_CTRL (0xC800)
169
170 /* TRAPPING to CPU-PORT */
171 #define RTL838X_SPCL_TRAP_IGMP_CTRL (0x6984)
172 #define RTL838X_RMA_CTRL_0 (0x4300)
173 #define RTL838X_RMA_CTRL_1 (0x4304)
174 #define RTL839X_RMA_CTRL_0 (0x1200)
175
176 #define RTL839X_SPCL_TRAP_IGMP_CTRL (0x1058)
177 #define RTL839X_RMA_CTRL_1 (0x1204)
178 #define RTL839X_RMA_CTRL_2 (0x1208)
179 #define RTL839X_RMA_CTRL_3 (0x120C)
180
181 #define RTL930X_VLAN_APP_PKT_CTRL (0xA23C)
182 #define RTL930X_RMA_CTRL_0 (0x9E60)
183 #define RTL930X_RMA_CTRL_1 (0x9E64)
184 #define RTL930X_RMA_CTRL_2 (0x9E68)
185
186 #define RTL931X_VLAN_APP_PKT_CTRL (0x96b0)
187 #define RTL931X_RMA_CTRL_0 (0x8800)
188 #define RTL931X_RMA_CTRL_1 (0x8804)
189 #define RTL931X_RMA_CTRL_2 (0x8808)
190
191 /* Advanced SMI control for clause 45 PHYs */
192 #define RTL930X_SMI_MAC_TYPE_CTRL (0xCA04)
193 #define RTL930X_SMI_PORT24_27_ADDR_CTRL (0xCB90)
194 #define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08)
195 #define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C)
196
197 #define RTL930X_SMI_10GPHY_POLLING_REG0_CFG (0xCBB4)
198 #define RTL930X_SMI_10GPHY_POLLING_REG9_CFG (0xCBB8)
199 #define RTL930X_SMI_10GPHY_POLLING_REG10_CFG (0xCBBC)
200 #define RTL930X_SMI_PRVTE_POLLING_CTRL (0xCA10)
201
202 /* Registers of the internal Serdes of the 8390 */
203 #define RTL839X_SDS12_13_XSG0 (0xB800)
204
205 /* Chip configuration registers of the RTL9310 */
206 #define RTL931X_MEM_ENCAP_INIT (0x4854)
207 #define RTL931X_MEM_MIB_INIT (0x7E18)
208 #define RTL931X_MEM_ACL_INIT (0x40BC)
209 #define RTL931X_MEM_ALE_INIT_0 (0x83F0)
210 #define RTL931X_MEM_ALE_INIT_1 (0x83F4)
211 #define RTL931X_MEM_ALE_INIT_2 (0x82E4)
212 #define RTL931X_MDX_CTRL_RSVD (0x0fcc)
213 #define RTL931X_PS_SOC_CTRL (0x13f8)
214 #define RTL931X_SMI_10GPHY_POLLING_SEL2 (0xCF8)
215 #define RTL931X_SMI_10GPHY_POLLING_SEL3 (0xCFC)
216 #define RTL931X_SMI_10GPHY_POLLING_SEL4 (0xD00)
217
218 /* Registers of the internal Serdes of the 8380 */
219 #define RTL838X_SDS4_FIB_REG0 (0xF800)
220
221 inline int rtl838x_mac_port_ctrl(int p)
222 {
223 return RTL838X_MAC_PORT_CTRL + (p << 7);
224 }
225
226 inline int rtl839x_mac_port_ctrl(int p)
227 {
228 return RTL839X_MAC_PORT_CTRL + (p << 7);
229 }
230
231 /* On the RTL931XX, the functionality of the MAC port control register is split up
232 * into RTL931X_MAC_L2_PORT_CTRL and RTL931X_MAC_PORT_CTRL the functionality used
233 * by the Ethernet driver is in the same bits now in RTL931X_MAC_L2_PORT_CTRL
234 */
235
236 inline int rtl930x_mac_port_ctrl(int p)
237 {
238 return RTL930X_MAC_L2_PORT_CTRL + (p << 6);
239 }
240
241 inline int rtl931x_mac_port_ctrl(int p)
242 {
243 return RTL931X_MAC_L2_PORT_CTRL + (p << 7);
244 }
245
246 inline int rtl838x_dma_if_rx_ring_size(int i)
247 {
248 return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
249 }
250
251 inline int rtl839x_dma_if_rx_ring_size(int i)
252 {
253 return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
254 }
255
256 inline int rtl930x_dma_if_rx_ring_size(int i)
257 {
258 return RTL930X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2);
259 }
260
261 inline int rtl931x_dma_if_rx_ring_size(int i)
262 {
263 return RTL931X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2);
264 }
265
266 inline int rtl838x_dma_if_rx_ring_cntr(int i)
267 {
268 return RTL838X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
269 }
270
271 inline int rtl839x_dma_if_rx_ring_cntr(int i)
272 {
273 return RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
274 }
275
276 inline int rtl930x_dma_if_rx_ring_cntr(int i)
277 {
278 return RTL930X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2);
279 }
280
281 inline int rtl931x_dma_if_rx_ring_cntr(int i)
282 {
283 return RTL931X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2);
284 }
285
286 inline u32 rtl838x_get_mac_link_sts(int port)
287 {
288 return (sw_r32(RTL838X_MAC_LINK_STS) & BIT(port));
289 }
290
291 inline u32 rtl839x_get_mac_link_sts(int p)
292 {
293 return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32));
294 }
295
296 inline u32 rtl930x_get_mac_link_sts(int port)
297 {
298 u32 link = sw_r32(RTL930X_MAC_LINK_STS);
299
300 link = sw_r32(RTL930X_MAC_LINK_STS);
301 pr_info("%s link state is %08x\n", __func__, link);
302 return link & BIT(port);
303 }
304
305 inline u32 rtl931x_get_mac_link_sts(int p)
306 {
307 return (sw_r32(RTL931X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32));
308 }
309
310 inline u32 rtl838x_get_mac_link_dup_sts(int port)
311 {
312 return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & BIT(port));
313 }
314
315 inline u32 rtl839x_get_mac_link_dup_sts(int p)
316 {
317 return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32));
318 }
319
320 inline u32 rtl930x_get_mac_link_dup_sts(int port)
321 {
322 return (sw_r32(RTL930X_MAC_LINK_DUP_STS) & BIT(port));
323 }
324
325 inline u32 rtl931x_get_mac_link_dup_sts(int p)
326 {
327 return (sw_r32(RTL931X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32));
328 }
329
330 inline u32 rtl838x_get_mac_link_spd_sts(int port)
331 {
332 int r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
333 u32 speed = sw_r32(r);
334
335 speed >>= (port % 16) << 1;
336 return (speed & 0x3);
337 }
338
339 inline u32 rtl839x_get_mac_link_spd_sts(int port)
340 {
341 int r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
342 u32 speed = sw_r32(r);
343
344 speed >>= (port % 16) << 1;
345 return (speed & 0x3);
346 }
347
348
349 inline u32 rtl930x_get_mac_link_spd_sts(int port)
350 {
351 int r = RTL930X_MAC_LINK_SPD_STS + ((port >> 3) << 2);
352 u32 speed = sw_r32(r);
353
354 speed >>= (port % 8) << 2;
355 return (speed & 0xf);
356 }
357
358 inline u32 rtl931x_get_mac_link_spd_sts(int port)
359 {
360 int r = RTL931X_MAC_LINK_SPD_STS + ((port >> 3) << 2);
361 u32 speed = sw_r32(r);
362
363 speed >>= (port % 8) << 2;
364 return (speed & 0xf);
365 }
366
367 inline u32 rtl838x_get_mac_rx_pause_sts(int port)
368 {
369 return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port));
370 }
371
372 inline u32 rtl839x_get_mac_rx_pause_sts(int p)
373 {
374 return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
375 }
376
377 inline u32 rtl930x_get_mac_rx_pause_sts(int port)
378 {
379 return (sw_r32(RTL930X_MAC_RX_PAUSE_STS) & (1 << port));
380 }
381
382 inline u32 rtl931x_get_mac_rx_pause_sts(int p)
383 {
384 return (sw_r32(RTL931X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
385 }
386
387 inline u32 rtl838x_get_mac_tx_pause_sts(int port)
388 {
389 return (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port));
390 }
391
392 inline u32 rtl839x_get_mac_tx_pause_sts(int p)
393 {
394 return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
395 }
396
397 inline u32 rtl930x_get_mac_tx_pause_sts(int port)
398 {
399 return (sw_r32(RTL930X_MAC_TX_PAUSE_STS) & (1 << port));
400 }
401
402 inline u32 rtl931x_get_mac_tx_pause_sts(int p)
403 {
404 return (sw_r32(RTL931X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
405 }
406
407 struct p_hdr;
408 struct dsa_tag;
409
410 struct rtl838x_eth_reg {
411 irqreturn_t (*net_irq)(int irq, void *dev_id);
412 int (*mac_port_ctrl)(int port);
413 int dma_if_intr_sts;
414 int dma_if_intr_msk;
415 int dma_if_intr_rx_runout_sts;
416 int dma_if_intr_rx_done_sts;
417 int dma_if_intr_tx_done_sts;
418 int dma_if_intr_rx_runout_msk;
419 int dma_if_intr_rx_done_msk;
420 int dma_if_intr_tx_done_msk;
421 int l2_ntfy_if_intr_sts;
422 int l2_ntfy_if_intr_msk;
423 int dma_if_ctrl;
424 int mac_force_mode_ctrl;
425 int dma_rx_base;
426 int dma_tx_base;
427 int (*dma_if_rx_ring_size)(int ring);
428 int (*dma_if_rx_ring_cntr)(int ring);
429 int dma_if_rx_cur;
430 int rst_glb_ctrl;
431 u32 (*get_mac_link_sts)(int port);
432 u32 (*get_mac_link_dup_sts)(int port);
433 u32 (*get_mac_link_spd_sts)(int port);
434 u32 (*get_mac_rx_pause_sts)(int port);
435 u32 (*get_mac_tx_pause_sts)(int port);
436 int mac;
437 int l2_tbl_flush_ctrl;
438 void (*update_cntr)(int r, int work_done);
439 void (*create_tx_header)(struct p_hdr *h, unsigned int dest_port, int prio);
440 bool (*decode_tag)(struct p_hdr *h, struct dsa_tag *tag);
441 };
442
443 int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
444 int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
445 int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val);
446 int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val);
447 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
448 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
449 int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
450 int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
451 int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val);
452 int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
453 int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val);
454 int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
455 int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data);
456
457 #endif /* _RTL838X_ETH_H */
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