target/linux/realtek/files-5.10/drivers/clocksource/timer-rtl-otto.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <linux/clk.h>
   4 #include <linux/clockchips.h>
   5 #include <linux/cpu.h>
   6 #include <linux/cpuhotplug.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/sched_clock.h>
   9
  10 #include "timer-of.h"
  11
  12 #define RTTM_DATA               0x0
  13 #define RTTM_CNT                0x4
  14 #define RTTM_CTRL               0x8
  15 #define RTTM_INT                0xc
  16
  17 #define RTTM_CTRL_ENABLE        BIT(28)
  18 #define RTTM_INT_PENDING        BIT(16)
  19 #define RTTM_INT_ENABLE         BIT(20)
  20
  21 /*
  22  * The Otto platform provides multiple 28 bit timers/counters with the following
  23  * operating logic. If enabled the timer counts up. Per timer one can set a
  24  * maximum counter value as an end marker. If end marker is reached the timer
  25  * fires an interrupt. If the timer "overflows" by reaching the end marker or
  26  * by adding 1 to 0x0fffffff the counter is reset to 0. When this happens and
  27  * the timer is in operating mode COUNTER it stops. In mode TIMER it will
  28  * continue to count up.
  29  */
  30
  31 #define RTTM_CTRL_COUNTER       0
  32 #define RTTM_CTRL_TIMER         BIT(24)
  33
  34 #define RTTM_BIT_COUNT          28
  35 #define RTTM_MIN_DELTA          8
  36 #define RTTM_MAX_DELTA          CLOCKSOURCE_MASK(28)
  37
  38 /*
  39  * Timers are derived from the LXB clock frequency. Usually this is a fixed
  40  * multiple of the 25 MHz oscillator. The 930X SOC is an exception from that.
  41  * Its LXB clock has only dividers and uses the switch PLL of 2.45 GHz as its
  42  * base. The only meaningful frequencies we can achieve from that are 175.000
  43  * MHz and 153.125 MHz. The greatest common divisor of all explained possible
  44  * speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency.
  45  */
  46
  47 #define RTTM_TICKS_PER_SEC      3125000
  48
  49 struct rttm_cs {
  50         struct timer_of         to;
  51         struct clocksource      cs;
  52 };
  53
  54 /*
  55  * Simple internal register functions
  56  */
  57
  58 static inline void rttm_set_counter(void __iomem *base, unsigned int counter)
  59 {
  60         iowrite32(counter, base + RTTM_CNT);
  61 }
  62
  63 static inline unsigned int rttm_get_counter(void __iomem *base)
  64 {
  65         return ioread32(base + RTTM_CNT);
  66 }
  67
  68 static inline void rttm_set_period(void __iomem *base, unsigned int period)
  69 {
  70         iowrite32(period, base + RTTM_DATA);
  71 }
  72
  73 static inline void rttm_disable_timer(void __iomem *base)
  74 {
  75         iowrite32(0, base + RTTM_CTRL);
  76 }
  77
  78 static inline void rttm_enable_timer(void __iomem *base, u32 mode, u32 divisor)
  79 {
  80         iowrite32(RTTM_CTRL_ENABLE | mode | divisor, base + RTTM_CTRL);
  81 }
  82
  83 static inline void rttm_ack_irq(void __iomem *base)
  84 {
  85         iowrite32(ioread32(base + RTTM_INT) | RTTM_INT_PENDING, base + RTTM_INT);
  86 }
  87
  88 static inline void rttm_enable_irq(void __iomem *base)
  89 {
  90         iowrite32(RTTM_INT_ENABLE, base + RTTM_INT);
  91 }
  92
  93 static inline void rttm_disable_irq(void __iomem *base)
  94 {
  95         iowrite32(0, base + RTTM_INT);
  96 }
  97
  98 /*
  99  * Aggregated control functions for kernel clock framework
 100  */
 101
 102 #define RTTM_DEBUG(base)                                        \
 103         pr_debug("------------- %s %d %08x\n", __func__,        \
 104         smp_processor_id(), (u32)base)
 105
 106 static irqreturn_t rttm_timer_interrupt(int irq, void *dev_id)
 107 {
 108         struct clock_event_device *clkevt = dev_id;
 109         struct timer_of *to = to_timer_of(clkevt);
 110
 111         rttm_ack_irq(to->of_base.base);
 112         RTTM_DEBUG(to->of_base.base);
 113         clkevt->event_handler(clkevt);
 114
 115         return IRQ_HANDLED;
 116 }
 117
 118 static void rttm_stop_timer(void __iomem *base)
 119 {
 120         rttm_disable_timer(base);
 121         rttm_ack_irq(base);
 122 }
 123
 124 static void rttm_start_timer(struct timer_of *to, u32 mode)
 125 {
 126         rttm_set_counter(to->of_base.base, 0);
 127         rttm_enable_timer(to->of_base.base, mode, to->of_clk.rate / RTTM_TICKS_PER_SEC);
 128 }
 129
 130 static int rttm_next_event(unsigned long delta, struct clock_event_device *clkevt)
 131 {
 132         struct timer_of *to = to_timer_of(clkevt);
 133
 134         RTTM_DEBUG(to->of_base.base);
 135         rttm_stop_timer(to->of_base.base);
 136         rttm_set_period(to->of_base.base, delta);
 137         rttm_start_timer(to, RTTM_CTRL_COUNTER);
 138
 139         return 0;
 140 }
 141
 142 static int rttm_state_oneshot(struct clock_event_device *clkevt)
 143 {
 144         struct timer_of *to = to_timer_of(clkevt);
 145
 146         RTTM_DEBUG(to->of_base.base);
 147         rttm_stop_timer(to->of_base.base);
 148         rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ);
 149         rttm_start_timer(to, RTTM_CTRL_COUNTER);
 150
 151         return 0;
 152 }
 153
 154 static int rttm_state_periodic(struct clock_event_device *clkevt)
 155 {
 156         struct timer_of *to = to_timer_of(clkevt);
 157
 158         RTTM_DEBUG(to->of_base.base);
 159         rttm_stop_timer(to->of_base.base);
 160         rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ);
 161         rttm_start_timer(to, RTTM_CTRL_TIMER);
 162
 163         return 0;
 164 }
 165
 166 static int rttm_state_shutdown(struct clock_event_device *clkevt)
 167 {
 168         struct timer_of *to = to_timer_of(clkevt);
 169
 170         RTTM_DEBUG(to->of_base.base);
 171         rttm_stop_timer(to->of_base.base);
 172
 173         return 0;
 174 }
 175
 176 static void rttm_setup_timer(void __iomem *base)
 177 {
 178         RTTM_DEBUG(base);
 179         rttm_stop_timer(base);
 180         rttm_set_period(base, 0);
 181 }
 182
 183 static u64 rttm_read_clocksource(struct clocksource *cs)
 184 {
 185         struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs);
 186
 187         return (u64)rttm_get_counter(rcs->to.of_base.base);
 188 }
 189
 190 /*
 191  * Module initialization part.
 192  */
 193
 194 static DEFINE_PER_CPU(struct timer_of, rttm_to) = {
 195         .flags                          = TIMER_OF_BASE | TIMER_OF_CLOCK | TIMER_OF_IRQ,
 196         .of_irq = {
 197                 .flags                  = IRQF_PERCPU | IRQF_TIMER,
 198                 .handler                = rttm_timer_interrupt,
 199         },
 200         .clkevt = {
 201                 .rating                 = 400,
 202                 .features               = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 203                 .set_state_periodic     = rttm_state_periodic,
 204                 .set_state_shutdown     = rttm_state_shutdown,
 205                 .set_state_oneshot      = rttm_state_oneshot,
 206                 .set_next_event         = rttm_next_event
 207         },
 208 };
 209
 210 static int rttm_enable_clocksource(struct clocksource *cs)
 211 {
 212         struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs);
 213
 214         rttm_disable_irq(rcs->to.of_base.base);
 215         rttm_setup_timer(rcs->to.of_base.base);
 216         rttm_enable_timer(rcs->to.of_base.base, RTTM_CTRL_TIMER,
 217                           rcs->to.of_clk.rate / RTTM_TICKS_PER_SEC);
 218
 219         return 0;
 220 }
 221
 222 struct rttm_cs rttm_cs = {
 223         .to = {
 224                 .flags  = TIMER_OF_BASE | TIMER_OF_CLOCK,
 225         },
 226         .cs = {
 227                 .name   = "realtek_otto_timer",
 228                 .rating = 400,
 229                 .mask   = CLOCKSOURCE_MASK(RTTM_BIT_COUNT),
 230                 .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 231                 .read   = rttm_read_clocksource,
 232         }
 233 };
 234
 235 static u64 notrace rttm_read_clock(void)
 236 {
 237         return (u64)rttm_get_counter(rttm_cs.to.of_base.base);
 238 }
 239
 240 static int rttm_cpu_starting(unsigned int cpu)
 241 {
 242         struct timer_of *to = per_cpu_ptr(&rttm_to, cpu);
 243
 244         RTTM_DEBUG(to->of_base.base);
 245         to->clkevt.cpumask = cpumask_of(cpu);
 246         irq_force_affinity(to->of_irq.irq, to->clkevt.cpumask);
 247         clockevents_config_and_register(&to->clkevt, RTTM_TICKS_PER_SEC,
 248                                         RTTM_MIN_DELTA, RTTM_MAX_DELTA);
 249         rttm_enable_irq(to->of_base.base);
 250
 251         return 0;
 252 }
 253
 254 static int __init rttm_probe(struct device_node *np)
 255 {
 256         int cpu, cpu_rollback;
 257         struct timer_of *to;
 258         int clkidx = num_possible_cpus();
 259 /*
 260  * Use the first n timers as per CPU clock event generators
 261  */
 262         for_each_possible_cpu(cpu) {
 263                 to = per_cpu_ptr(&rttm_to, cpu);
 264                 to->of_irq.index = to->of_base.index = cpu;
 265                 if (timer_of_init(np, to)) {
 266                         pr_err("%s: setup of timer %d failed\n", __func__, cpu);
 267                         goto rollback;
 268                 }
 269                 rttm_setup_timer(to->of_base.base);
 270         }
 271 /*
 272  * Activate the n'th+1 timer as a stable CPU clocksource.
 273  */
 274         to = &rttm_cs.to;
 275         to->of_base.index = clkidx;
 276         timer_of_init(np, to);
 277         if (rttm_cs.to.of_base.base && rttm_cs.to.of_clk.rate) {
 278                 rttm_enable_clocksource(&rttm_cs.cs);
 279                 clocksource_register_hz(&rttm_cs.cs, RTTM_TICKS_PER_SEC);
 280                 sched_clock_register(rttm_read_clock, RTTM_BIT_COUNT, RTTM_TICKS_PER_SEC);
 281         } else
 282                 pr_err("%s: setup of timer %d as clocksoure failed", __func__, clkidx);
 283
 284         return cpuhp_setup_state(CPUHP_AP_REALTEK_TIMER_STARTING,
 285                                 "timer/realtek:online",
 286                                 rttm_cpu_starting, NULL);
 287 rollback:
 288         pr_err("%s: timer registration failed\n", __func__);
 289         for_each_possible_cpu(cpu_rollback) {
 290                 if (cpu_rollback == cpu)
 291                         break;
 292                 to = per_cpu_ptr(&rttm_to, cpu_rollback);
 293                 timer_of_cleanup(to);
 294         }
 295
 296         return -EINVAL;
 297 }
 298
 299 TIMER_OF_DECLARE(otto_timer, "realtek,otto-timer", rttm_probe);