target/linux/realtek/dts-5.10/rtl930x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 /dts-v1/;
   4
   5 / {
   6         #address-cells = <1>;
   7         #size-cells = <1>;
   8
   9         compatible = "realtek,rtl838x-soc";
  10
  11         cpus {
  12                 #address-cells = <1>;
  13                 #size-cells = <0>;
  14                 frequency = <800000000>;
  15
  16                 cpu@0 {
  17                         compatible = "mips,mips34Kc";
  18                         reg = <0>;
  19                 };
  20         };
  21
  22         memory@0 {
  23                 device_type = "memory";
  24                 reg = <0x0 0x8000000>;
  25         };
  26
  27         chosen {
  28                 bootargs = "console=ttyS0,115200";
  29         };
  30
  31         cpuintc: cpuintc {
  32                 compatible = "mti,cpu-interrupt-controller";
  33                 #address-cells = <0>;
  34                 #interrupt-cells = <1>;
  35                 interrupt-controller;
  36         };
  37
  38         lx_clk: lx_clk {
  39                 compatible = "fixed-clock";
  40                 #clock-cells = <0>;
  41                 clock-frequency  = <175000000>;
  42         };
  43
  44         soc: soc {
  45                 compatible = "simple-bus";
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 ranges = <0x0 0x18000000 0x10000>;
  49
  50                 intc: interrupt-controller@3000 {
  51                         compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
  52                         reg = <0x3000 0x18>, <0x3018 0x18>;
  53                         interrupt-controller;
  54                         #interrupt-cells = <2>;
  55
  56                         interrupt-parent = <&cpuintc>;
  57                         interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
  58                 };
  59
  60                 rtl9300clock: rtl9300clock@3200 {
  61                         compatible = "realtek,rtl9300clock";
  62                         reg = <0x3200 0x10>, <0x3210 0x10>;
  63
  64                         interrupt-parent = <&intc>;
  65                         interrupts = <7 5>, <8 5>;
  66                 };
  67
  68                 spi0: spi@1200 {
  69                         compatible = "realtek,rtl8380-spi";
  70                         reg = <0x1200 0x100>;
  71
  72                         #address-cells = <1>;
  73                         #size-cells = <0>;
  74                 };
  75
  76                 uart0: uart@2000 {
  77                         compatible = "ns16550a";
  78                         reg = <0x2000 0x100>;
  79
  80                         clocks = <&lx_clk>;
  81
  82                         interrupt-parent = <&intc>;
  83                         interrupts = <30 1>;
  84
  85                         reg-io-width = <1>;
  86                         reg-shift = <2>;
  87                         fifo-size = <1>;
  88                         no-loopback-test;
  89                 };
  90
  91                 uart1: uart@2100 {
  92                         compatible = "ns16550a";
  93                         reg = <0x2100 0x100>;
  94
  95                         clocks = <&lx_clk>;
  96
  97                         interrupt-parent = <&intc>;
  98                         interrupts = <31 0>;
  99
 100                         reg-io-width = <1>;
 101                         reg-shift = <2>;
 102                         fifo-size = <1>;
 103                         no-loopback-test;
 104
 105                         status = "disabled";
 106                 };
 107
 108                 watchdog0: watchdog@3260 {
 109                         compatible = "realtek,rtl9300-wdt";
 110                         reg = <0x3260 0xc>;
 111
 112                         realtek,reset-mode = "soc";
 113
 114                         clocks = <&lx_clk>;
 115                         timeout-sec = <30>;
 116
 117                         interrupt-parent = <&intc>;
 118                         interrupt-names = "phase1", "phase2";
 119                         interrupts = <5 4>, <6 4>;
 120                 };
 121
 122                 gpio0: gpio-controller@3300 {
 123                         compatible = "realtek,rtl9300-gpio", "realtek,otto-gpio";
 124                         reg = <0x3300 0x1c>, <0x3338 0x8>;
 125
 126                         gpio-controller;
 127                         #gpio-cells = <2>;
 128                         ngpios = <24>;
 129
 130                         interrupt-controller;
 131                         #interrupt-cells = <2>;
 132                         interrupt-parent = <&intc>;
 133                         interrupts = <13 1>;
 134                 };
 135
 136         };
 137
 138         pinmux_led: pinmux@1b00cc00 {
 139                 compatible = "pinctrl-single";
 140                 reg = <0x1b00cc00 0x4>;
 141
 142                 pinctrl-single,bit-per-mux;
 143                 pinctrl-single,register-width = <32>;
 144                 pinctrl-single,function-mask = <0x1>;
 145                 #pinctrl-cells = <2>;
 146
 147                 /* enable GPIO 0 */
 148                 pinmux_disable_sys_led: disable_sys_led {
 149                         pinctrl-single,bits = <0x0 0x0 0x1000>;
 150                 };
 151         };
 152
 153         ethernet0: ethernet@1b00a300 {
 154                 compatible = "realtek,rtl838x-eth";
 155                 reg = <0x1b00a300 0x100>;
 156
 157                 interrupt-parent = <&intc>;
 158                 interrupts = <24 3>;
 159
 160                 phy-mode = "internal";
 161
 162                 fixed-link {
 163                         speed = <1000>;
 164                         full-duplex;
 165                 };
 166         };
 167
 168         switch0: switch@1b000000 {
 169                 compatible = "realtek,rtl83xx-switch";
 170                 status = "okay";
 171
 172                 interrupt-parent = <&intc>;
 173                 interrupts = <23 2>;
 174         };
 175 };