target/linux/realtek/dts-5.10/rtl8382_hpe_1920-24g.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "rtl8382_hpe_1920.dtsi"
   4
   5 / {
   6         compatible = "hpe,1920-24g", "realtek,rtl838x-soc";
   7         model = "HPE 1920-24G (JG924A)";
   8 };
   9
  10 &mdio {
  11         EXTERNAL_PHY(0)
  12         EXTERNAL_PHY(1)
  13         EXTERNAL_PHY(2)
  14         EXTERNAL_PHY(3)
  15         EXTERNAL_PHY(4)
  16         EXTERNAL_PHY(5)
  17         EXTERNAL_PHY(6)
  18         EXTERNAL_PHY(7)
  19 };
  20
  21 &switch0 {
  22         ports {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 SWITCH_PORT(0, 1, qsgmii)
  27                 SWITCH_PORT(1, 2, qsgmii)
  28                 SWITCH_PORT(2, 3, qsgmii)
  29                 SWITCH_PORT(3, 4, qsgmii)
  30                 SWITCH_PORT(4, 5, qsgmii)
  31                 SWITCH_PORT(5, 6, qsgmii)
  32                 SWITCH_PORT(6, 7, qsgmii)
  33                 SWITCH_PORT(7, 8, qsgmii)
  34
  35                 SWITCH_PORT(8, 9, internal)
  36                 SWITCH_PORT(9, 10, internal)
  37                 SWITCH_PORT(10, 11, internal)
  38                 SWITCH_PORT(11, 12, internal)
  39                 SWITCH_PORT(12, 13, internal)
  40                 SWITCH_PORT(13, 14, internal)
  41                 SWITCH_PORT(14, 15, internal)
  42                 SWITCH_PORT(15, 16, internal)
  43
  44                 SWITCH_PORT(16, 17, qsgmii)
  45                 SWITCH_PORT(17, 18, qsgmii)
  46                 SWITCH_PORT(18, 19, qsgmii)
  47                 SWITCH_PORT(19, 20, qsgmii)
  48                 SWITCH_PORT(20, 21, qsgmii)
  49                 SWITCH_PORT(21, 22, qsgmii)
  50                 SWITCH_PORT(22, 23, qsgmii)
  51                 SWITCH_PORT(23, 24, qsgmii)
  52
  53                 SWITCH_PORT(24, 25, qsgmii)
  54                 SWITCH_PORT(25, 26, qsgmii)
  55                 SWITCH_PORT(26, 27, qsgmii)
  56                 SWITCH_PORT(27, 28, qsgmii)
  57
  58                 port@28 {
  59                         ethernet = <&ethernet0>;
  60                         reg = <28>;
  61                         phy-mode = "internal";
  62                         fixed-link {
  63                                 speed = <1000>;
  64                                 full-duplex;
  65                         };
  66                 };
  67         };
  68 };