target/linux/ramips/patches-4.3/0057-cm-use-core-other-locking-function.patch

   1 commit 4ede31617056b7424eef28dce59dd6dbe81729c3
   2 Author: Paul Burton <paul.burton@imgtec.com>
   3 Date:   Tue Sep 22 11:12:17 2015 -0700
   4
   5     MIPS: CM: make use of mips_cm_{lock,unlock}_other
   6
   7     Document that CPC core-other accesses must take place within the bounds
   8     of the CM lock, and begin using the CM lock functions where we access
   9     the GCRs of other cores. This is required because with CM3 the CPC began
  10     using GCR_CL_OTHER instead of CPC_CL_OTHER.
  11
  12     Signed-off-by: Paul Burton <paul.burton@imgtec.com>
  13     Cc: linux-mips@linux-mips.org
  14     Cc: Rusty Russell <rusty@rustcorp.com.au>
  15     Cc: Andrew Bresticker <abrestic@chromium.org>
  16     Cc: Bjorn Helgaas <bhelgaas@google.com>
  17     Cc: linux-kernel@vger.kernel.org
  18     Cc: Niklas Cassel <niklas.cassel@axis.com>
  19     Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
  20     Cc: Markos Chandras <markos.chandras@imgtec.com>
  21     Patchwork: https://patchwork.linux-mips.org/patch/11208/
  22     Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  23
  24 --- a/arch/mips/include/asm/mips-cpc.h
  25 +++ b/arch/mips/include/asm/mips-cpc.h
  26 @@ -149,7 +149,8 @@ BUILD_CPC_Cx_RW(other,              0x10)
  27   * core: the other core to be accessed
  28   *
  29   * Call before operating upon a core via the 'other' register region in
  30 - * order to prevent the region being moved during access. Must be followed
  31 + * order to prevent the region being moved during access. Must be called
  32 + * within the bounds of a mips_cm_{lock,unlock}_other pair, and followed
  33   * by a call to mips_cpc_unlock_other.
  34   */
  35  extern void mips_cpc_lock_other(unsigned int core);
  36 --- a/arch/mips/kernel/smp-cps.c
  37 +++ b/arch/mips/kernel/smp-cps.c
  38 @@ -37,8 +37,9 @@ static unsigned core_vpe_count(unsigned
  39         if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
  40                 return 1;
  41
  42 -       write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
  43 +       mips_cm_lock_other(core, 0);
  44         cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
  45 +       mips_cm_unlock_other();
  46         return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
  47  }
  48
  49 @@ -193,7 +194,7 @@ static void boot_core(unsigned core)
  50         u32 access;
  51
  52         /* Select the appropriate core */
  53 -       write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
  54 +       mips_cm_lock_other(core, 0);
  55
  56         /* Set its reset vector */
  57         write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
  58 @@ -216,6 +217,8 @@ static void boot_core(unsigned core)
  59                 write_gcr_co_reset_release(0);
  60         }
  61
  62 +       mips_cm_unlock_other();
  63 +
  64         /* The core is now powered up */
  65         bitmap_set(core_power, core, 1);
  66  }
  67 --- a/arch/mips/kernel/smp-gic.c
  68 +++ b/arch/mips/kernel/smp-gic.c
  69 @@ -46,9 +46,11 @@ void gic_send_ipi_single(int cpu, unsign
  70
  71         if (mips_cpc_present() && (core != current_cpu_data.core)) {
  72                 while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
  73 +                       mips_cm_lock_other(core, 0);
  74                         mips_cpc_lock_other(core);
  75                         write_cpc_co_cmd(CPC_Cx_CMD_PWRUP);
  76                         mips_cpc_unlock_other();
  77 +                       mips_cm_unlock_other();
  78                 }
  79         }
  80