target/linux/ramips/patches-4.3/0009-PCI-MIPS-adds-mt7620a-pcie-driver.patch

   1 From 41aa7fc236fdb1f4c9b8b10df9b71f0d248cb36b Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 7 Dec 2015 17:11:12 +0100
   4 Subject: [PATCH 09/53] PCI: MIPS: adds mt7620a pcie driver
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/include/asm/mach-ralink/mt7620.h |    1 +
   9  arch/mips/pci/Makefile                     |    1 +
  10  arch/mips/pci/pci-mt7620.c                 |  396 ++++++++++++++++++++++++++++
  11  arch/mips/ralink/Kconfig                   |    1 +
  12  4 files changed, 399 insertions(+)
  13  create mode 100644 arch/mips/pci/pci-mt7620.c
  14
  15 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
  16 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
  17 @@ -19,6 +19,7 @@ enum mt762x_soc_type {
  18         MT762X_SOC_MT7620N,
  19         MT762X_SOC_MT7628AN,
  20  };
  21 +extern enum mt762x_soc_type mt762x_soc;
  22
  23  #define MT7620_SYSC_BASE               0x10000000
  24
  25 --- a/arch/mips/pci/Makefile
  26 +++ b/arch/mips/pci/Makefile
  27 @@ -43,6 +43,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80)  += pci-bcm1
  28  obj-$(CONFIG_SNI_RM)           += fixup-sni.o ops-sni.o
  29  obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
  30  obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
  31 +obj-$(CONFIG_SOC_MT7620)       += pci-mt7620.o
  32  obj-$(CONFIG_SOC_MT7621)       += pci-mt7621.o
  33  obj-$(CONFIG_SOC_RT288X)       += pci-rt2880.o
  34  obj-$(CONFIG_SOC_RT3883)       += pci-rt3883.o
  35 --- /dev/null
  36 +++ b/arch/mips/pci/pci-mt7620.c
  37 @@ -0,0 +1,396 @@
  38 +/*
  39 + *  Ralink MT7620A SoC PCI support
  40 + *
  41 + *  Copyright (C) 2007-2013 Bruce Chang
  42 + *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  43 + *
  44 + *  This program is free software; you can redistribute it and/or modify it
  45 + *  under the terms of the GNU General Public License version 2 as published
  46 + *  by the Free Software Foundation.
  47 + */
  48 +
  49 +#include <linux/types.h>
  50 +#include <linux/pci.h>
  51 +#include <linux/io.h>
  52 +#include <linux/init.h>
  53 +#include <linux/delay.h>
  54 +#include <linux/interrupt.h>
  55 +#include <linux/module.h>
  56 +#include <linux/of.h>
  57 +#include <linux/of_irq.h>
  58 +#include <linux/of_pci.h>
  59 +#include <linux/reset.h>
  60 +#include <linux/platform_device.h>
  61 +
  62 +#include <asm/mach-ralink/ralink_regs.h>
  63 +#include <asm/mach-ralink/mt7620.h>
  64 +
  65 +#define RALINK_PCI_MM_MAP_BASE         0x20000000
  66 +#define RALINK_PCI_IO_MAP_BASE         0x10160000
  67 +
  68 +#define RALINK_INT_PCIE0               4
  69 +#define RALINK_SYSCFG1                 0x14
  70 +#define RALINK_CLKCFG1                 0x30
  71 +#define RALINK_GPIOMODE                        0x60
  72 +#define RALINK_PCIE_CLK_GEN            0x7c
  73 +#define RALINK_PCIE_CLK_GEN1           0x80
  74 +#define PCIEPHY0_CFG                   0x90
  75 +#define PPLL_CFG1                      0x9c
  76 +#define PPLL_DRV                       0xa0
  77 +#define PDRV_SW_SET                    (1<<31)
  78 +#define LC_CKDRVPD_                    (1<<19)
  79 +
  80 +#define RALINK_PCI_CONFIG_ADDR         0x20
  81 +#define RALINK_PCI_CONFIG_DATA_VIRT_REG        0x24
  82 +#define MEMORY_BASE                    0x0
  83 +#define RALINK_PCIE0_RST               (1<<26)
  84 +#define RALINK_PCI_BASE                        0xB0140000
  85 +#define RALINK_PCI_MEMBASE             0x28
  86 +#define RALINK_PCI_IOBASE              0x2C
  87 +
  88 +#define RT6855_PCIE0_OFFSET            0x2000
  89 +
  90 +#define RALINK_PCI_PCICFG_ADDR         0x00
  91 +#define RALINK_PCI0_BAR0SETUP_ADDR     0x10
  92 +#define RALINK_PCI0_IMBASEBAR0_ADDR    0x18
  93 +#define RALINK_PCI0_ID                 0x30
  94 +#define RALINK_PCI0_CLASS              0x34
  95 +#define RALINK_PCI0_SUBID              0x38
  96 +#define RALINK_PCI0_STATUS             0x50
  97 +#define RALINK_PCI_PCIMSK_ADDR         0x0C
  98 +
  99 +#define RALINK_PCIEPHY_P0_CTL_OFFSET   0x7498
 100 +#define RALINK_PCIE0_CLK_EN            (1 << 26)
 101 +
 102 +#define BUSY                           0x80000000
 103 +#define WAITRETRY_MAX                  10
 104 +#define WRITE_MODE                     (1UL << 23)
 105 +#define DATA_SHIFT                     0
 106 +#define ADDR_SHIFT                     8
 107 +
 108 +static void __iomem *bridge_base;
 109 +static void __iomem *pcie_base;
 110 +
 111 +static struct reset_control *rstpcie0;
 112 +
 113 +static inline void bridge_w32(u32 val, unsigned reg)
 114 +{
 115 +       iowrite32(val, bridge_base + reg);
 116 +}
 117 +
 118 +static inline u32 bridge_r32(unsigned reg)
 119 +{
 120 +       return ioread32(bridge_base + reg);
 121 +}
 122 +
 123 +static inline void pcie_w32(u32 val, unsigned reg)
 124 +{
 125 +       iowrite32(val, pcie_base + reg);
 126 +}
 127 +
 128 +static inline u32 pcie_r32(unsigned reg)
 129 +{
 130 +       return ioread32(pcie_base + reg);
 131 +}
 132 +
 133 +static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
 134 +{
 135 +       u32 val = pcie_r32(reg);
 136 +
 137 +       val &= ~clr;
 138 +       val |= set;
 139 +       pcie_w32(val, reg);
 140 +}
 141 +
 142 +static int wait_pciephy_busy(void)
 143 +{
 144 +       unsigned long reg_value = 0x0, retry = 0;
 145 +
 146 +       while (1) {
 147 +               reg_value = pcie_r32(PCIEPHY0_CFG);
 148 +
 149 +               if (reg_value & BUSY)
 150 +                       mdelay(100);
 151 +               else
 152 +                       break;
 153 +               if (retry++ > WAITRETRY_MAX){
 154 +                       printk("PCIE-PHY retry failed.\n");
 155 +                       return -1;
 156 +               }
 157 +       }
 158 +       return 0;
 159 +}
 160 +
 161 +static void pcie_phy(unsigned long addr, unsigned long val)
 162 +{
 163 +       wait_pciephy_busy();
 164 +       pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
 165 +       mdelay(1);
 166 +       wait_pciephy_busy();
 167 +}
 168 +
 169 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
 170 +{
 171 +       unsigned int slot = PCI_SLOT(devfn);
 172 +       u8 func = PCI_FUNC(devfn);
 173 +       u32 address;
 174 +       u32 data;
 175 +       u32 num = 0;
 176 +
 177 +       if (bus)
 178 +               num = bus->number;
 179 +
 180 +       address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 181 +       bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
 182 +       data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
 183 +
 184 +       switch (size) {
 185 +       case 1:
 186 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 187 +               break;
 188 +       case 2:
 189 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 190 +               break;
 191 +       case 4:
 192 +               *val = data;
 193 +               break;
 194 +       }
 195 +
 196 +       return PCIBIOS_SUCCESSFUL;
 197 +}
 198 +
 199 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 200 +{
 201 +       unsigned int slot = PCI_SLOT(devfn);
 202 +       u8 func = PCI_FUNC(devfn);
 203 +       u32 address;
 204 +       u32 data;
 205 +       u32 num = 0;
 206 +
 207 +       if (bus)
 208 +               num = bus->number;
 209 +
 210 +       address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 211 +       bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
 212 +       data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
 213 +
 214 +       switch (size) {
 215 +       case 1:
 216 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 217 +                       (val << ((where & 3) << 3));
 218 +               break;
 219 +       case 2:
 220 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 221 +                       (val << ((where & 3) << 3));
 222 +               break;
 223 +       case 4:
 224 +               data = val;
 225 +               break;
 226 +       }
 227 +
 228 +       bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
 229 +
 230 +       return PCIBIOS_SUCCESSFUL;
 231 +}
 232 +
 233 +struct pci_ops mt7620_pci_ops= {
 234 +       .read   = pci_config_read,
 235 +       .write  = pci_config_write,
 236 +};
 237 +
 238 +static struct resource mt7620_res_pci_mem1;
 239 +static struct resource mt7620_res_pci_io1;
 240 +struct pci_controller mt7620_controller = {
 241 +       .pci_ops        = &mt7620_pci_ops,
 242 +       .mem_resource   = &mt7620_res_pci_mem1,
 243 +       .mem_offset     = 0x00000000UL,
 244 +       .io_resource    = &mt7620_res_pci_io1,
 245 +       .io_offset      = 0x00000000UL,
 246 +       .io_map_base    = 0xa0000000,
 247 +};
 248 +
 249 +static int mt7620_pci_hw_init(struct platform_device *pdev) {
 250 +       /* PCIE: bypass PCIe DLL */
 251 +       pcie_phy(0x0, 0x80);
 252 +       pcie_phy(0x1, 0x04);
 253 +
 254 +       /* PCIE: Elastic buffer control */
 255 +       pcie_phy(0x68, 0xB4);
 256 +
 257 +       pcie_m32(0, BIT(1), RALINK_PCI_PCICFG_ADDR);
 258 +
 259 +       reset_control_assert(rstpcie0);
 260 +
 261 +       rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 262 +       rt_sysc_m32(BIT(19), BIT(31), PPLL_DRV);
 263 +
 264 +       reset_control_deassert(rstpcie0);
 265 +       rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
 266 +
 267 +       mdelay(100);
 268 +
 269 +       if (!(rt_sysc_r32(PPLL_CFG1) & BIT(23))) {
 270 +               dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
 271 +               reset_control_assert(rstpcie0);
 272 +               rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 273 +               return -1;
 274 +       }
 275 +       rt_sysc_m32(BIT(18) | BIT(17), BIT(19) | BIT(31), PPLL_DRV);
 276 +
 277 +       return 0;
 278 +}
 279 +
 280 +static int mt7628_pci_hw_init(struct platform_device *pdev) {
 281 +       u32 val = 0;
 282 +
 283 +       rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
 284 +       reset_control_deassert(rstpcie0);
 285 +       rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
 286 +       mdelay(100);
 287 +
 288 +       pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
 289 +
 290 +       pci_config_read(NULL, 0, 0x70c, 4, &val);
 291 +       val &= ~(0xff) << 8;
 292 +       val |= 0x50 << 8;
 293 +       pci_config_write(NULL, 0, 0x70c, 4, val);
 294 +
 295 +       pci_config_read(NULL, 0, 0x70c, 4, &val);
 296 +       dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
 297 +
 298 +       return 0;
 299 +}
 300 +
 301 +static int mt7620_pci_probe(struct platform_device *pdev)
 302 +{
 303 +       struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 304 +       struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 305 +       u32 val = 0;
 306 +
 307 +       rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
 308 +       if (IS_ERR(rstpcie0))
 309 +               return PTR_ERR(rstpcie0);
 310 +
 311 +       bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
 312 +        if (!bridge_base)
 313 +               return -ENOMEM;
 314 +
 315 +       pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
 316 +        if (!pcie_base)
 317 +               return -ENOMEM;
 318 +
 319 +       iomem_resource.start = 0;
 320 +       iomem_resource.end = ~0;
 321 +       ioport_resource.start = 0;
 322 +       ioport_resource.end = ~0;
 323 +
 324 +       /* bring up the pci core */
 325 +       switch (ralink_soc) {
 326 +       case MT762X_SOC_MT7620A:
 327 +               if (mt7620_pci_hw_init(pdev))
 328 +                       return -1;
 329 +               break;
 330 +
 331 +       case MT762X_SOC_MT7628AN:
 332 +               if (mt7628_pci_hw_init(pdev))
 333 +                       return -1;
 334 +               break;
 335 +
 336 +       default:
 337 +               dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
 338 +               return -1;
 339 +       }
 340 +       mdelay(50);
 341 +
 342 +       /* enable write access */
 343 +       pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
 344 +       mdelay(100);
 345 +
 346 +       /* check if there is a card present */
 347 +       if ((pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
 348 +               reset_control_assert(rstpcie0);
 349 +               rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 350 +               if (ralink_soc == MT762X_SOC_MT7620A)
 351 +                       rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
 352 +               dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
 353 +               return -1;
 354 +       }
 355 +
 356 +       /* setup ranges */
 357 +       bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
 358 +       bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
 359 +
 360 +       pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
 361 +       pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
 362 +       pcie_w32(0x06040001, RALINK_PCI0_CLASS);
 363 +
 364 +       /* enable interrupts */
 365 +       pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
 366 +
 367 +       /* voodoo from the SDK driver */
 368 +       pci_config_read(NULL, 0, 4, 4, &val);
 369 +       pci_config_write(NULL, 0, 4, 4, val | 0x7);
 370 +
 371 +       pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
 372 +       register_pci_controller(&mt7620_controller);
 373 +
 374 +       return 0;
 375 +}
 376 +
 377 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 378 +{
 379 +       u16 cmd;
 380 +       u32 val;
 381 +       int irq = 0;
 382 +
 383 +       if ((dev->bus->number == 0) && (slot == 0)) {
 384 +               pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
 385 +               pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
 386 +               pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
 387 +       } else if ((dev->bus->number == 1) && (slot == 0x0)) {
 388 +               irq = RALINK_INT_PCIE0;
 389 +       } else {
 390 +               dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
 391 +               return 0;
 392 +       }
 393 +       dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", dev->bus->number, slot, irq);
 394 +
 395 +       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
 396 +       pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
 397 +       pci_read_config_word(dev, PCI_COMMAND, &cmd);
 398 +
 399 +       // FIXME
 400 +       cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 401 +       pci_write_config_word(dev, PCI_COMMAND, cmd);
 402 +       pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 403 +       //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
 404 +
 405 +       return irq;
 406 +}
 407 +
 408 +int pcibios_plat_dev_init(struct pci_dev *dev)
 409 +{
 410 +       return 0;
 411 +}
 412 +
 413 +static const struct of_device_id mt7620_pci_ids[] = {
 414 +       { .compatible = "mediatek,mt7620-pci" },
 415 +       {},
 416 +};
 417 +MODULE_DEVICE_TABLE(of, mt7620_pci_ids);
 418 +
 419 +static struct platform_driver mt7620_pci_driver = {
 420 +       .probe = mt7620_pci_probe,
 421 +       .driver = {
 422 +               .name = "mt7620-pci",
 423 +               .owner = THIS_MODULE,
 424 +               .of_match_table = of_match_ptr(mt7620_pci_ids),
 425 +       },
 426 +};
 427 +
 428 +static int __init mt7620_pci_init(void)
 429 +{
 430 +       return platform_driver_register(&mt7620_pci_driver);
 431 +}
 432 +
 433 +arch_initcall(mt7620_pci_init);
 434 --- a/arch/mips/ralink/Kconfig
 435 +++ b/arch/mips/ralink/Kconfig
 436 @@ -43,6 +43,7 @@ choice
 437
 438         config SOC_MT7620
 439                 bool "MT7620/8"
 440 +               select HW_HAS_PCI
 441
 442         config SOC_MT7621
 443                 bool "MT7621"