target/linux/ramips/patches-3.8/0119-PCI-MIPS-adds-rt3883-pci-support.patch

   1 From f01830fcc57273bd9ec5f6733ab3d28adeb71955 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 21 Mar 2013 17:34:08 +0100
   4 Subject: [PATCH 119/121] PCI: MIPS: adds rt3883 pci support
   5
   6 Add support for the pcie found on the rt3883 SoC.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  arch/mips/pci/Makefile     |    1 +
  11  arch/mips/pci/pci-rt3883.c |  487 ++++++++++++++++++++++++++++++++++++++++++++
  12  arch/mips/ralink/Kconfig   |    1 +
  13  3 files changed, 489 insertions(+)
  14  create mode 100644 arch/mips/pci/pci-rt3883.c
  15
  16 --- a/arch/mips/pci/Makefile
  17 +++ b/arch/mips/pci/Makefile
  18 @@ -43,6 +43,7 @@ obj-$(CONFIG_SNI_RM)          += fixup-sni.o ops
  19  obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
  20  obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
  21  obj-$(CONFIG_SOC_RT2880)       += pci-rt2880.o
  22 +obj-$(CONFIG_SOC_RT3883)       += pci-rt3883.o
  23  obj-$(CONFIG_TANBAC_TB0219)    += fixup-tb0219.o
  24  obj-$(CONFIG_TANBAC_TB0226)    += fixup-tb0226.o
  25  obj-$(CONFIG_TANBAC_TB0287)    += fixup-tb0287.o
  26 --- /dev/null
  27 +++ b/arch/mips/pci/pci-rt3883.c
  28 @@ -0,0 +1,487 @@
  29 +/*
  30 + *  Ralink RT3883 SoC PCI support
  31 + *
  32 + *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  33 + *
  34 + *  Parts of this file are based on Ralink's 2.6.21 BSP
  35 + *
  36 + *  This program is free software; you can redistribute it and/or modify it
  37 + *  under the terms of the GNU General Public License version 2 as published
  38 + *  by the Free Software Foundation.
  39 + */
  40 +
  41 +#include <linux/types.h>
  42 +#include <linux/pci.h>
  43 +#include <linux/io.h>
  44 +#include <linux/init.h>
  45 +#include <linux/delay.h>
  46 +#include <linux/interrupt.h>
  47 +
  48 +#include <asm/mach-ralink/rt3883.h>
  49 +#include <asm/mach-ralink/rt3883_regs.h>
  50 +
  51 +#define RT3883_MEMORY_BASE             0x00000000
  52 +#define RT3883_MEMORY_SIZE             0x02000000
  53 +
  54 +#define RT3883_PCI_MEM_BASE            0x20000000
  55 +#define RT3883_PCI_MEM_SIZE            0x10000000
  56 +#define RT3883_PCI_IO_BASE             0x10160000
  57 +#define RT3883_PCI_IO_SIZE             0x00010000
  58 +
  59 +#define RT3883_PCI_REG_PCICFG_ADDR     0x00
  60 +#define RT3883_PCI_REG_PCIRAW_ADDR     0x04
  61 +#define RT3883_PCI_REG_PCIINT_ADDR     0x08
  62 +#define RT3883_PCI_REG_PCIMSK_ADDR     0x0c
  63 +#define   RT3833_PCI_PCIINT_PCIE       BIT(20)
  64 +#define   RT3833_PCI_PCIINT_PCI1       BIT(19)
  65 +#define   RT3833_PCI_PCIINT_PCI0       BIT(18)
  66 +
  67 +#define RT3883_PCI_REG_CONFIG_ADDR     0x20
  68 +#define RT3883_PCI_REG_CONFIG_DATA     0x24
  69 +#define RT3883_PCI_REG_MEMBASE         0x28
  70 +#define RT3883_PCI_REG_IOBASE          0x2c
  71 +#define RT3883_PCI_REG_ARBCTL          0x80
  72 +
  73 +#define RT3883_PCI_REG_BASE(_x)                (0x1000 + (_x) * 0x1000)
  74 +#define RT3883_PCI_REG_BAR0SETUP_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
  75 +#define RT3883_PCI_REG_IMBASEBAR0_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
  76 +#define RT3883_PCI_REG_ID(_x)          (RT3883_PCI_REG_BASE((_x)) + 0x30)
  77 +#define RT3883_PCI_REG_CLASS(_x)       (RT3883_PCI_REG_BASE((_x)) + 0x34)
  78 +#define RT3883_PCI_REG_SUBID(_x)       (RT3883_PCI_REG_BASE((_x)) + 0x38)
  79 +#define RT3883_PCI_REG_STATUS(_x)      (RT3883_PCI_REG_BASE((_x)) + 0x50)
  80 +
  81 +static int (*rt3883_pci_plat_dev_init)(struct pci_dev *dev);
  82 +static void __iomem *rt3883_pci_base;
  83 +static DEFINE_SPINLOCK(rt3883_pci_lock);
  84 +
  85 +static inline u32 rt3883_pci_rr(unsigned reg)
  86 +{
  87 +       return readl(rt3883_pci_base + reg);
  88 +}
  89 +
  90 +static inline void rt3883_pci_wr(u32 val, unsigned reg)
  91 +{
  92 +       writel(val, rt3883_pci_base + reg);
  93 +}
  94 +
  95 +static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
  96 +                                        unsigned int func, unsigned int where)
  97 +{
  98 +       return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
  99 +               0x80000000);
 100 +}
 101 +
 102 +static u32 rt3883_pci_read_u32(unsigned bus, unsigned slot,
 103 +                              unsigned func, unsigned reg)
 104 +{
 105 +       unsigned long flags;
 106 +       u32 address;
 107 +       u32 ret;
 108 +
 109 +       address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 110 +
 111 +       spin_lock_irqsave(&rt3883_pci_lock, flags);
 112 +       rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
 113 +       ret = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
 114 +       spin_unlock_irqrestore(&rt3883_pci_lock, flags);
 115 +
 116 +       return ret;
 117 +}
 118 +
 119 +static void rt3883_pci_write_u32(unsigned bus, unsigned slot,
 120 +                                unsigned func, unsigned reg, u32 val)
 121 +{
 122 +       unsigned long flags;
 123 +       u32 address;
 124 +
 125 +       address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 126 +
 127 +       spin_lock_irqsave(&rt3883_pci_lock, flags);
 128 +       rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
 129 +       rt3883_pci_wr(val, RT3883_PCI_REG_CONFIG_DATA);
 130 +       spin_unlock_irqrestore(&rt3883_pci_lock, flags);
 131 +}
 132 +
 133 +static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 134 +{
 135 +       u32 pending;
 136 +
 137 +       pending = rt3883_pci_rr(RT3883_PCI_REG_PCIINT_ADDR) &
 138 +                 rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
 139 +
 140 +       if (!pending) {
 141 +               spurious_interrupt();
 142 +               return;
 143 +       }
 144 +
 145 +       if (pending & RT3833_PCI_PCIINT_PCI0)
 146 +               generic_handle_irq(RT3883_PCI_IRQ_PCI0);
 147 +
 148 +       if (pending & RT3833_PCI_PCIINT_PCI1)
 149 +               generic_handle_irq(RT3883_PCI_IRQ_PCI1);
 150 +
 151 +       if (pending & RT3833_PCI_PCIINT_PCIE)
 152 +               generic_handle_irq(RT3883_PCI_IRQ_PCIE);
 153 +}
 154 +
 155 +static void rt3883_pci_irq_unmask(struct irq_data *d)
 156 +{
 157 +       int irq = d->irq;
 158 +       u32 mask;
 159 +       u32 t;
 160 +
 161 +       switch (irq) {
 162 +       case RT3883_PCI_IRQ_PCI0:
 163 +               mask = RT3833_PCI_PCIINT_PCI0;
 164 +               break;
 165 +       case RT3883_PCI_IRQ_PCI1:
 166 +               mask = RT3833_PCI_PCIINT_PCI1;
 167 +               break;
 168 +       case RT3883_PCI_IRQ_PCIE:
 169 +               mask = RT3833_PCI_PCIINT_PCIE;
 170 +               break;
 171 +       default:
 172 +               BUG();
 173 +       }
 174 +
 175 +       t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
 176 +       rt3883_pci_wr(t | mask, RT3883_PCI_REG_PCIMSK_ADDR);
 177 +       /* flush write */
 178 +       rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
 179 +}
 180 +
 181 +static void rt3883_pci_irq_mask(struct irq_data *d)
 182 +{
 183 +       int irq = d->irq;
 184 +       u32 mask;
 185 +       u32 t;
 186 +
 187 +       switch (irq) {
 188 +       case RT3883_PCI_IRQ_PCI0:
 189 +               mask = RT3833_PCI_PCIINT_PCI0;
 190 +               break;
 191 +       case RT3883_PCI_IRQ_PCI1:
 192 +               mask = RT3833_PCI_PCIINT_PCI1;
 193 +               break;
 194 +       case RT3883_PCI_IRQ_PCIE:
 195 +               mask = RT3833_PCI_PCIINT_PCIE;
 196 +               break;
 197 +       default:
 198 +               BUG();
 199 +       }
 200 +
 201 +       t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
 202 +       rt3883_pci_wr(t & ~mask, RT3883_PCI_REG_PCIMSK_ADDR);
 203 +       /* flush write */
 204 +       rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
 205 +}
 206 +
 207 +static struct irq_chip rt3883_pci_irq_chip = {
 208 +       .name           = "RT3883 PCI",
 209 +       .irq_mask       = rt3883_pci_irq_mask,
 210 +       .irq_unmask     = rt3883_pci_irq_unmask,
 211 +       .irq_mask_ack   = rt3883_pci_irq_mask,
 212 +};
 213 +
 214 +static void __init rt3883_pci_irq_init(void)
 215 +{
 216 +       int i;
 217 +
 218 +       /* disable all interrupts */
 219 +       rt3883_pci_wr(0, RT3883_PCI_REG_PCIMSK_ADDR);
 220 +
 221 +       for (i = RT3883_PCI_IRQ_BASE;
 222 +            i < RT3883_PCI_IRQ_BASE + RT3883_PCI_IRQ_COUNT; i++) {
 223 +               irq_set_chip_and_handler(i, &rt3883_pci_irq_chip,
 224 +                                        handle_level_irq);
 225 +       }
 226 +
 227 +       irq_set_chained_handler(RT3883_CPU_IRQ_PCI, rt3883_pci_irq_handler);
 228 +}
 229 +
 230 +static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
 231 +                                 int where, int size, u32 *val)
 232 +{
 233 +       unsigned long flags;
 234 +       u32 address;
 235 +       u32 data;
 236 +
 237 +       address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 238 +                                        PCI_FUNC(devfn), where);
 239 +
 240 +       spin_lock_irqsave(&rt3883_pci_lock, flags);
 241 +       rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
 242 +       data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
 243 +       spin_unlock_irqrestore(&rt3883_pci_lock, flags);
 244 +
 245 +       switch (size) {
 246 +       case 1:
 247 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 248 +               break;
 249 +       case 2:
 250 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 251 +               break;
 252 +       case 4:
 253 +               *val = data;
 254 +               break;
 255 +       }
 256 +
 257 +       return PCIBIOS_SUCCESSFUL;
 258 +}
 259 +
 260 +static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
 261 +                                  int where, int size, u32 val)
 262 +{
 263 +       unsigned long flags;
 264 +       u32 address;
 265 +       u32 data;
 266 +
 267 +       address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 268 +                                        PCI_FUNC(devfn), where);
 269 +
 270 +       spin_lock_irqsave(&rt3883_pci_lock, flags);
 271 +       rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
 272 +       data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
 273 +
 274 +       switch (size) {
 275 +       case 1:
 276 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 277 +                      (val << ((where & 3) << 3));
 278 +               break;
 279 +       case 2:
 280 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 281 +                      (val << ((where & 3) << 3));
 282 +               break;
 283 +       case 4:
 284 +               data = val;
 285 +               break;
 286 +       }
 287 +
 288 +       rt3883_pci_wr(data, RT3883_PCI_REG_CONFIG_DATA);
 289 +       spin_unlock_irqrestore(&rt3883_pci_lock, flags);
 290 +
 291 +       return PCIBIOS_SUCCESSFUL;
 292 +}
 293 +
 294 +static struct pci_ops rt3883_pci_ops = {
 295 +       .read   = rt3883_pci_config_read,
 296 +       .write  = rt3883_pci_config_write,
 297 +};
 298 +
 299 +static struct resource rt3883_pci_mem_resource = {
 300 +       .name   = "PCI MEM space",
 301 +       .start  = RT3883_PCI_MEM_BASE,
 302 +       .end    = RT3883_PCI_MEM_BASE + RT3883_PCI_MEM_SIZE - 1,
 303 +       .flags  = IORESOURCE_MEM,
 304 +};
 305 +
 306 +static struct resource rt3883_pci_io_resource = {
 307 +       .name   = "PCI IO space",
 308 +       .start  = RT3883_PCI_IO_BASE,
 309 +       .end    = RT3883_PCI_IO_BASE + RT3883_PCI_IO_SIZE - 1,
 310 +       .flags  = IORESOURCE_IO,
 311 +};
 312 +
 313 +static struct pci_controller rt3883_pci_controller = {
 314 +       .pci_ops        = &rt3883_pci_ops,
 315 +       .mem_resource   = &rt3883_pci_mem_resource,
 316 +       .io_resource    = &rt3883_pci_io_resource,
 317 +};
 318 +
 319 +static void rt3883_pci_preinit(unsigned mode)
 320 +{
 321 +       u32 syscfg1;
 322 +       u32 rstctrl;
 323 +       u32 clkcfg1;
 324 +
 325 +       if (mode & RT3883_PCI_MODE_PCIE) {
 326 +               u32 val;
 327 +
 328 +               val = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
 329 +               val &= ~(0x30);
 330 +               val |= (2 << 4);
 331 +               rt3883_sysc_wr(val, RT3883_SYSC_REG_SYSCFG1);
 332 +
 333 +               val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 334 +               val &= ~BIT(31);
 335 +               rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 336 +
 337 +               val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 338 +               val &= 0x80ffffff;
 339 +               rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 340 +
 341 +               val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 342 +               val |= 0xa << 24;
 343 +               rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 344 +
 345 +               val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 346 +               val |= BIT(31);
 347 +               rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 348 +
 349 +               msleep(50);
 350 +       }
 351 +
 352 +       syscfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
 353 +       syscfg1 &= ~(RT3883_SYSCFG1_PCIE_RC_MODE |
 354 +                    RT3883_SYSCFG1_PCI_HOST_MODE);
 355 +
 356 +       rstctrl = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL);
 357 +       rstctrl |= (RT3883_RSTCTRL_PCI | RT3883_RSTCTRL_PCIE);
 358 +
 359 +       clkcfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1);
 360 +       clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN |
 361 +                    RT3883_CLKCFG1_PCIE_CLK_EN);
 362 +
 363 +       if (mode & RT3883_PCI_MODE_PCI) {
 364 +               syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE;
 365 +               clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
 366 +               rstctrl &= ~RT3883_RSTCTRL_PCI;
 367 +       }
 368 +       if (mode & RT3883_PCI_MODE_PCIE) {
 369 +               syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE |
 370 +                          RT3883_SYSCFG1_PCIE_RC_MODE;
 371 +               clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
 372 +               rstctrl &= ~RT3883_RSTCTRL_PCIE;
 373 +       }
 374 +
 375 +       rt3883_sysc_wr(syscfg1, RT3883_SYSC_REG_SYSCFG1);
 376 +       rt3883_sysc_wr(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 377 +       rt3883_sysc_wr(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
 378 +
 379 +       msleep(500);
 380 +}
 381 +
 382 +static int rt3883_pcie_ready(void)
 383 +{
 384 +       u32 status;
 385 +
 386 +       msleep(500);
 387 +
 388 +       status = rt3883_pci_rr(RT3883_PCI_REG_STATUS(1));
 389 +       if (status & BIT(0))
 390 +               return 0;
 391 +
 392 +       /* TODO: reset PCIe and turn off PCIe clock */
 393 +
 394 +       return -ENODEV;
 395 +}
 396 +
 397 +void __init rt3883_pci_init(unsigned mode)
 398 +{
 399 +       u32 val;
 400 +       int err;
 401 +
 402 +       rt3883_pci_preinit(mode);
 403 +
 404 +       rt3883_pci_base = ioremap(RT3883_PCI_BASE, PAGE_SIZE);
 405 +       if (rt3883_pci_base == NULL) {
 406 +               pr_err("failed to ioremap PCI registers\n");
 407 +               return;
 408 +       }
 409 +
 410 +       rt3883_pci_wr(0, RT3883_PCI_REG_PCICFG_ADDR);
 411 +       if (mode & RT3883_PCI_MODE_PCI)
 412 +               rt3883_pci_wr(BIT(16), RT3883_PCI_REG_PCICFG_ADDR);
 413 +
 414 +       msleep(500);
 415 +
 416 +       if (mode & RT3883_PCI_MODE_PCIE) {
 417 +               err = rt3883_pcie_ready();
 418 +               if (err)
 419 +                       return;
 420 +       }
 421 +
 422 +       if (mode & RT3883_PCI_MODE_PCI)
 423 +               rt3883_pci_wr(0x79, RT3883_PCI_REG_ARBCTL);
 424 +
 425 +       rt3883_pci_wr(RT3883_PCI_MEM_BASE, RT3883_PCI_REG_MEMBASE);
 426 +       rt3883_pci_wr(RT3883_PCI_IO_BASE, RT3883_PCI_REG_IOBASE);
 427 +
 428 +       /* PCI */
 429 +       rt3883_pci_wr(0x03ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(0));
 430 +       rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(0));
 431 +       rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(0));
 432 +       rt3883_pci_wr(0x00800001, RT3883_PCI_REG_CLASS(0));
 433 +       rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(0));
 434 +
 435 +       /* PCIe */
 436 +       rt3883_pci_wr(0x01ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(1));
 437 +       rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(1));
 438 +       rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(1));
 439 +       rt3883_pci_wr(0x06040001, RT3883_PCI_REG_CLASS(1));
 440 +       rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(1));
 441 +
 442 +       rt3883_pci_irq_init();
 443 +
 444 +       /* PCIe */
 445 +       val = rt3883_pci_read_u32(0, 0x01, 0, PCI_COMMAND);
 446 +       val |= 0x7;
 447 +       rt3883_pci_write_u32(0, 0x01, 0, PCI_COMMAND, val);
 448 +
 449 +       /* PCI */
 450 +       val = rt3883_pci_read_u32(0, 0x00, 0, PCI_COMMAND);
 451 +       val |= 0x7;
 452 +       rt3883_pci_write_u32(0, 0x00, 0, PCI_COMMAND, val);
 453 +
 454 +       ioport_resource.start = rt3883_pci_io_resource.start;
 455 +       ioport_resource.end = rt3883_pci_io_resource.end;
 456 +
 457 +       register_pci_controller(&rt3883_pci_controller);
 458 +}
 459 +
 460 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 461 +{
 462 +       int irq = -1;
 463 +
 464 +       switch (dev->bus->number) {
 465 +       case 0:
 466 +               switch (PCI_SLOT(dev->devfn)) {
 467 +               case 0x00:
 468 +                       rt3883_pci_wr(0x03ff0001,
 469 +                                            RT3883_PCI_REG_BAR0SETUP_ADDR(0));
 470 +                       rt3883_pci_wr(0x03ff0001,
 471 +                                            RT3883_PCI_REG_BAR0SETUP_ADDR(1));
 472 +
 473 +                       rt3883_pci_write_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0,
 474 +                                            RT3883_MEMORY_BASE);
 475 +                       rt3883_pci_read_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0);
 476 +
 477 +                       irq = RT3883_CPU_IRQ_PCI;
 478 +                       break;
 479 +               case 0x01:
 480 +                       rt3883_pci_write_u32(0, 0x01, 0, PCI_IO_BASE,
 481 +                                            0x00000101);
 482 +                       break;
 483 +               case 0x11:
 484 +                       irq = RT3883_PCI_IRQ_PCI0;
 485 +                       break;
 486 +               case 0x12:
 487 +                       irq = RT3883_PCI_IRQ_PCI1;
 488 +                       break;
 489 +               }
 490 +               break;
 491 +
 492 +       case 1:
 493 +               irq = RT3883_PCI_IRQ_PCIE;
 494 +               break;
 495 +
 496 +       default:
 497 +               dev_err(&dev->dev, "no IRQ specified\n");
 498 +               return irq;
 499 +       }
 500 +
 501 +       return irq;
 502 +}
 503 +
 504 +void __init rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *dev))
 505 +{
 506 +       rt3883_pci_plat_dev_init = f;
 507 +}
 508 +
 509 +int pcibios_plat_dev_init(struct pci_dev *dev)
 510 +{
 511 +       if (rt3883_pci_plat_dev_init)
 512 +               return rt3883_pci_plat_dev_init(dev);
 513 +
 514 +       return 0;
 515 +}
 516 --- a/arch/mips/ralink/Kconfig
 517 +++ b/arch/mips/ralink/Kconfig
 518 @@ -20,6 +20,7 @@ choice
 519                 bool "RT3883"
 520                 select USB_ARCH_HAS_OHCI
 521                 select USB_ARCH_HAS_EHCI
 522 +               select HW_HAS_PCI
 523
 524         config SOC_MT7620
 525                 bool "MT7620"