target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c

   1 /*
   2  * Oxford Semiconductor OXNAS NAND driver
   3
   4  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
   5  * Heavily based on plat_nand.c :
   6  * Author: Vitaly Wool <vitalywool@gmail.com>
   7  * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
   8  * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  */
  15
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/slab.h>
  21 #include <linux/clk.h>
  22 #include <linux/reset.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/nand.h>
  25 #include <linux/mtd/partitions.h>
  26 #include <linux/of.h>
  27
  28 /* Nand commands */
  29 #define OXNAS_NAND_CMD_ALE              BIT(18)
  30 #define OXNAS_NAND_CMD_CLE              BIT(19)
  31
  32 #define OXNAS_NAND_MAX_CHIPS    1
  33
  34 struct oxnas_nand {
  35         struct nand_hw_control base;
  36         void __iomem *io_base;
  37         struct clk *clk;
  38         struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS];
  39         unsigned long ctrl;
  40         struct mtd_partition *partitions;
  41         int nr_partitions;
  42 };
  43
  44 static uint8_t oxnas_nand_read_byte(struct mtd_info *mtd)
  45 {
  46         struct nand_chip *chip = mtd_to_nand(mtd);
  47         struct oxnas_nand *oxnas = nand_get_controller_data(chip);
  48
  49         return readb(oxnas->io_base);
  50 }
  51
  52 static void oxnas_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  53 {
  54         struct nand_chip *chip = mtd_to_nand(mtd);
  55         struct oxnas_nand *oxnas = nand_get_controller_data(chip);
  56
  57         ioread8_rep(oxnas->io_base, buf, len);
  58 }
  59
  60 static void oxnas_nand_write_buf(struct mtd_info *mtd,
  61                                  const uint8_t *buf, int len)
  62 {
  63         struct nand_chip *chip = mtd_to_nand(mtd);
  64         struct oxnas_nand *oxnas = nand_get_controller_data(chip);
  65
  66         iowrite8_rep(oxnas->io_base + oxnas->ctrl, buf, len);
  67 }
  68
  69 /* Single CS command control */
  70 static void oxnas_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
  71                                 unsigned int ctrl)
  72 {
  73         struct nand_chip *chip = mtd_to_nand(mtd);
  74         struct oxnas_nand *oxnas = nand_get_controller_data(chip);
  75
  76         if (ctrl & NAND_CTRL_CHANGE) {
  77                 if (ctrl & NAND_CLE)
  78                         oxnas->ctrl = OXNAS_NAND_CMD_CLE;
  79                 else if (ctrl & NAND_ALE)
  80                         oxnas->ctrl = OXNAS_NAND_CMD_ALE;
  81                 else
  82                         oxnas->ctrl = 0;
  83         }
  84
  85         if (cmd != NAND_CMD_NONE)
  86                 writeb(cmd, oxnas->io_base + oxnas->ctrl);
  87 }
  88
  89 /*
  90  * Probe for the NAND device.
  91  */
  92 static int oxnas_nand_probe(struct platform_device *pdev)
  93 {
  94         struct device_node *np = pdev->dev.of_node;
  95         struct device_node *nand_np;
  96         struct oxnas_nand *oxnas;
  97         struct nand_chip *chip;
  98         struct mtd_info *mtd;
  99         struct resource *res;
 100         int nchips = 0;
 101         int count = 0;
 102         int err = 0;
 103
 104         /* Allocate memory for the device structure (and zero it) */
 105         oxnas = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
 106                             GFP_KERNEL);
 107         if (!oxnas)
 108                 return -ENOMEM;
 109
 110         nand_hw_control_init(&oxnas->base);
 111
 112         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 113         oxnas->io_base = devm_ioremap_resource(&pdev->dev, res);
 114         if (IS_ERR(oxnas->io_base))
 115                 return PTR_ERR(oxnas->io_base);
 116
 117         oxnas->clk = devm_clk_get(&pdev->dev, NULL);
 118         if (IS_ERR(oxnas->clk))
 119                 oxnas->clk = NULL;
 120
 121         /* Only a single chip node is supported */
 122         count = of_get_child_count(np);
 123         pr_info("########### count: %d\n", count);
 124         if (count > 1)
 125                 return -EINVAL;
 126
 127         clk_prepare_enable(oxnas->clk);
 128         device_reset_optional(&pdev->dev);
 129
 130         for_each_child_of_node(np, nand_np) {
 131                 chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
 132                                     GFP_KERNEL);
 133                 if (!chip)
 134                         return -ENOMEM;
 135
 136                 chip->controller = &oxnas->base;
 137
 138                 nand_set_flash_node(chip, nand_np);
 139                 nand_set_controller_data(chip, oxnas);
 140
 141                 mtd = nand_to_mtd(chip);
 142                 mtd->dev.parent = &pdev->dev;
 143                 mtd->priv = chip;
 144
 145                 chip->cmd_ctrl = oxnas_nand_cmd_ctrl;
 146                 chip->read_buf = oxnas_nand_read_buf;
 147                 chip->read_byte = oxnas_nand_read_byte;
 148                 chip->write_buf = oxnas_nand_write_buf;
 149                 chip->chip_delay = 30;
 150
 151                 /* Scan to find existence of the device */
 152                 err = nand_scan(mtd, 1);
 153                 pr_info("########### nand_scan err: %d\n", err);
 154                 if (err)
 155                         return err;
 156
 157                 err = mtd_device_register(mtd, NULL, 0);
 158                 pr_info("########### mtd_device_register err: %d\n", err);
 159                 if (err) {
 160                         nand_release(mtd);
 161                         return err;
 162                 }
 163
 164                 oxnas->chips[nchips] = chip;
 165                 ++nchips;
 166         }
 167
 168         pr_info("########### nchips: %d\n", nchips);
 169
 170         /* Exit if no chips found */
 171         if (!nchips)
 172                 return -ENODEV;
 173
 174         platform_set_drvdata(pdev, oxnas);
 175
 176         return 0;
 177 }
 178
 179 static int oxnas_nand_remove(struct platform_device *pdev)
 180 {
 181         struct oxnas_nand *oxnas = platform_get_drvdata(pdev);
 182
 183         if (oxnas->chips[0])
 184                 nand_release(nand_to_mtd(oxnas->chips[0]));
 185
 186         clk_disable_unprepare(oxnas->clk);
 187
 188         return 0;
 189 }
 190
 191 static const struct of_device_id oxnas_nand_match[] = {
 192         { .compatible = "oxsemi,ox820-nand" },
 193         {},
 194 };
 195 MODULE_DEVICE_TABLE(of, oxnas_nand_match);
 196
 197 static struct platform_driver oxnas_nand_driver = {
 198         .probe  = oxnas_nand_probe,
 199         .remove = oxnas_nand_remove,
 200         .driver = {
 201                 .name           = "oxnas_nand",
 202                 .of_match_table = oxnas_nand_match,
 203         },
 204 };
 205
 206 module_platform_driver(oxnas_nand_driver);
 207
 208 MODULE_LICENSE("GPL");
 209 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
 210 MODULE_DESCRIPTION("Oxnas NAND driver");
 211 MODULE_ALIAS("platform:oxnas_nand");