2 * Copyright (C) 2010 Broadcom
3 * Copyright (C) 2012 Stephen Warren
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/clk-provider.h>
19 #include <linux/clkdev.h>
20 #include <linux/clk-provider.h>
22 #include <linux/delay.h>
23 #include <linux/stringify.h>
24 #include <linux/reset.h>
26 #include <mach/hardware.h>
27 #include <mach/utils.h>
29 #define MHZ (1000 * 1000)
31 static unsigned long plla_clk_recalc_rate(struct clk_hw
*hw
,
32 unsigned long parent_rate
)
34 unsigned long fin
= parent_rate
;
36 unsigned long fbdiv
, refdiv
, outdiv
;
38 pll0
= readl_relaxed(SYS_CTRL_PLLA_CTRL0
);
39 refdiv
= (pll0
>> PLLA_REFDIV_SHIFT
) & PLLA_REFDIV_MASK
;
41 outdiv
= (pll0
>> PLLA_OUTDIV_SHIFT
) & PLLA_OUTDIV_MASK
;
43 fbdiv
= readl_relaxed(SYS_CTRL_PLLA_CTRL1
);
45 /* seems we will not be here when pll is bypassed, so ignore this
48 return fin
/ MHZ
* fbdiv
/ (refdiv
* outdiv
) / 32768 * MHZ
;
51 static const char *pll_clk_parents
[] = {
55 static struct clk_ops plla_ops
= {
56 .recalc_rate
= plla_clk_recalc_rate
,
59 static struct clk_init_data clk_plla_init
= {
62 .parent_names
= pll_clk_parents
,
63 .num_parents
= ARRAY_SIZE(pll_clk_parents
),
66 static struct clk_hw plla_hw
= {
67 .init
= &clk_plla_init
,
70 static struct device_node
*node_pllb
;
72 int pllb_clk_enable(struct clk_hw
*hw
)
74 struct reset_control
*rstc
;
76 rstc
= of_reset_control_get(node_pllb
, NULL
);
80 /* put PLL into bypass */
81 oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0
, BIT(PLLB_BYPASS
));
84 reset_control_assert(rstc
);
86 /* set PLL B control information */
87 writel((1 << PLLB_ENSAT
) | (1 << PLLB_OUTDIV
) | (2 << PLLB_REFDIV
),
89 reset_control_deassert(rstc
);
90 reset_control_put(rstc
);
92 oxnas_register_clear_mask(SEC_CTRL_PLLB_CTRL0
, BIT(PLLB_BYPASS
));
97 void pllb_clk_disable(struct clk_hw
*hw
)
99 struct reset_control
*rstc
;
101 /* put PLL into bypass */
102 oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0
, BIT(PLLB_BYPASS
));
106 rstc
= of_reset_control_get(node_pllb
, NULL
);
108 reset_control_assert(rstc
);
111 static struct clk_ops pllb_ops
= {
112 .enable
= pllb_clk_enable
,
113 .disable
= pllb_clk_disable
,
116 static struct clk_init_data clk_pllb_init
= {
119 .parent_names
= pll_clk_parents
,
120 .num_parents
= ARRAY_SIZE(pll_clk_parents
),
123 static struct clk_hw pllb_hw
= {
124 .init
= &clk_pllb_init
,
127 /* standard gate clock */
133 #define NUM_STD_CLKS 17
134 #define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
136 static int std_clk_is_enabled(struct clk_hw
*hw
)
138 struct clk_std
*std
= to_stdclk(hw
);
140 return readl_relaxed(SYSCTRL_CLK_STAT
) & BIT(std
->bit
);
143 static int std_clk_enable(struct clk_hw
*hw
)
145 struct clk_std
*std
= to_stdclk(hw
);
147 writel(BIT(std
->bit
), SYS_CTRL_CLK_SET_CTRL
);
151 static void std_clk_disable(struct clk_hw
*hw
)
153 struct clk_std
*std
= to_stdclk(hw
);
155 writel(BIT(std
->bit
), SYS_CTRL_CLK_CLR_CTRL
);
158 static struct clk_ops std_clk_ops
= {
159 .enable
= std_clk_enable
,
160 .disable
= std_clk_disable
,
161 .is_enabled
= std_clk_is_enabled
,
164 static const char *std_clk_parents
[] = {
168 static const char *eth_parents
[] = {
172 #define DECLARE_STD_CLKP(__clk, __bit, __parent) \
173 static struct clk_init_data clk_##__clk##_init = { \
174 .name = __stringify(__clk), \
175 .ops = &std_clk_ops, \
176 .parent_names = __parent, \
177 .num_parents = ARRAY_SIZE(__parent), \
180 static struct clk_std clk_##__clk = { \
183 .init = &clk_##__clk##_init, \
187 #define DECLARE_STD_CLK(__clk, __bit) DECLARE_STD_CLKP(__clk, __bit, \
190 DECLARE_STD_CLK(leon
, 0);
191 DECLARE_STD_CLK(dma_sgdma
, 1);
192 DECLARE_STD_CLK(cipher
, 2);
193 DECLARE_STD_CLK(sd
, 3);
194 DECLARE_STD_CLK(sata
, 4);
195 DECLARE_STD_CLK(audio
, 5);
196 DECLARE_STD_CLK(usbmph
, 6);
197 DECLARE_STD_CLKP(etha
, 7, eth_parents
);
198 DECLARE_STD_CLK(pciea
, 8);
199 DECLARE_STD_CLK(static, 9);
200 DECLARE_STD_CLK(ethb
, 10);
201 DECLARE_STD_CLK(pcieb
, 11);
202 DECLARE_STD_CLK(ref600
, 12);
203 DECLARE_STD_CLK(usbdev
, 13);
205 struct clk_hw
*std_clk_hw_tbl
[] = {
222 struct clk
*std_clk_tbl
[ARRAY_SIZE(std_clk_hw_tbl
)];
224 static struct clk_onecell_data std_clk_data
;
226 void __init
oxnas_init_stdclk(struct device_node
*np
)
230 for (i
= 0; i
< ARRAY_SIZE(std_clk_hw_tbl
); i
++) {
231 std_clk_tbl
[i
] = clk_register(NULL
, std_clk_hw_tbl
[i
]);
232 BUG_ON(IS_ERR(std_clk_tbl
[i
]));
234 std_clk_data
.clks
= std_clk_tbl
;
235 std_clk_data
.clk_num
= ARRAY_SIZE(std_clk_tbl
);
236 of_clk_add_provider(np
, of_clk_src_onecell_get
, &std_clk_data
);
238 CLK_OF_DECLARE(oxnas_pllstd
, "plxtech,nas782x-stdclk", oxnas_init_stdclk
);
240 void __init
oxnas_init_plla(struct device_node
*np
)
244 clk
= clk_register(NULL
, &plla_hw
);
246 /* mark it as enabled */
247 clk_prepare_enable(clk
);
248 of_clk_add_provider(np
, of_clk_src_simple_get
, clk
);
250 CLK_OF_DECLARE(oxnas_plla
, "plxtech,nas782x-plla", oxnas_init_plla
);
252 void __init
oxnas_init_pllb(struct device_node
*np
)
258 clk
= clk_register(NULL
, &pllb_hw
);
260 of_clk_add_provider(np
, of_clk_src_simple_get
, clk
);
262 CLK_OF_DECLARE(oxnas_pllb
, "plxtech,nas782x-pllb", oxnas_init_pllb
);