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octeon: add support for the octeon mips64 SoC
[openwrt/openwrt.git] / target / linux / octeon / files / drivers / staging / octeon-usb / cvmx-usbnx-defs.h
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40
41 /**
42 * cvmx-usbnx-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon usbnx.
46 *
47 */
48 #ifndef __CVMX_USBNX_TYPEDEFS_H__
49 #define __CVMX_USBNX_TYPEDEFS_H__
50
51 #define CVMX_USBNXBID1(bid) (((bid) & 1) * 0x10000000ull)
52 #define CVMX_USBNXBID2(bid) (((bid) & 1) * 0x100000000000ull)
53
54 #define CVMX_USBNXREG1(reg, bid) \
55 (CVMX_ADD_IO_SEG(0x0001180068000000ull | reg) + CVMX_USBNXBID1(bid))
56 #define CVMX_USBNXREG2(reg, bid) \
57 (CVMX_ADD_IO_SEG(0x00016F0000000000ull | reg) + CVMX_USBNXBID2(bid))
58
59 #define CVMX_USBNX_CLK_CTL(bid) CVMX_USBNXREG1(0x10, bid)
60 #define CVMX_USBNX_DMA0_INB_CHN0(bid) CVMX_USBNXREG2(0x818, bid)
61 #define CVMX_USBNX_DMA0_OUTB_CHN0(bid) CVMX_USBNXREG2(0x858, bid)
62 #define CVMX_USBNX_USBP_CTL_STATUS(bid) CVMX_USBNXREG1(0x18, bid)
63
64 /**
65 * cvmx_usbn#_clk_ctl
66 *
67 * USBN_CLK_CTL = USBN's Clock Control
68 *
69 * This register is used to control the frequency of the hclk and the
70 * hreset and phy_rst signals.
71 */
72 union cvmx_usbnx_clk_ctl {
73 uint64_t u64;
74 /**
75 * struct cvmx_usbnx_clk_ctl_s
76 * @divide2: The 'hclk' used by the USB subsystem is derived
77 * from the eclk.
78 * Also see the field DIVIDE. DIVIDE2<1> must currently
79 * be zero because it is not implemented, so the maximum
80 * ratio of eclk/hclk is currently 16.
81 * The actual divide number for hclk is:
82 * (DIVIDE2 + 1) * (DIVIDE + 1)
83 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to
84 * generate the hclk in the USB Subsystem is held
85 * in reset. This bit must be set to '0' before
86 * changing the value os DIVIDE in this register.
87 * The reset to the HCLK_DIVIDERis also asserted
88 * when core reset is asserted.
89 * @p_x_on: Force USB-PHY on during suspend.
90 * '1' USB-PHY XO block is powered-down during
91 * suspend.
92 * '0' USB-PHY XO block is powered-up during
93 * suspend.
94 * The value of this field must be set while POR is
95 * active.
96 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to
97 * remain powered in Suspend Mode.
98 * '1' The USB-PHY XO Bias, Bandgap and PLL are
99 * powered down in suspend mode.
100 * The value of this field must be set while POR is
101 * active.
102 * @p_c_sel: Phy clock speed select.
103 * Selects the reference clock / crystal frequency.
104 * '11': Reserved
105 * '10': 48 MHz (reserved when a crystal is used)
106 * '01': 24 MHz (reserved when a crystal is used)
107 * '00': 12 MHz
108 * The value of this field must be set while POR is
109 * active.
110 * NOTE: if a crystal is used as a reference clock,
111 * this field must be set to 12 MHz.
112 * @cdiv_byp: Used to enable the bypass input to the USB_CLK_DIV.
113 * @sd_mode: Scaledown mode for the USBC. Control timing events
114 * in the USBC, for normal operation this must be '0'.
115 * @s_bist: Starts bist on the hclk memories, during the '0'
116 * to '1' transition.
117 * @por: Power On Reset for the PHY.
118 * Resets all the PHYS registers and state machines.
119 * @enable: When '1' allows the generation of the hclk. When
120 * '0' the hclk will not be generated. SEE DIVIDE
121 * field of this register.
122 * @prst: When this field is '0' the reset associated with
123 * the phy_clk functionality in the USB Subsystem is
124 * help in reset. This bit should not be set to '1'
125 * until the time it takes 6 clocks (hclk or phy_clk,
126 * whichever is slower) has passed. Under normal
127 * operation once this bit is set to '1' it should not
128 * be set to '0'.
129 * @hrst: When this field is '0' the reset associated with
130 * the hclk functioanlity in the USB Subsystem is
131 * held in reset.This bit should not be set to '1'
132 * until 12ms after phy_clk is stable. Under normal
133 * operation, once this bit is set to '1' it should
134 * not be set to '0'.
135 * @divide: The frequency of 'hclk' used by the USB subsystem
136 * is the eclk frequency divided by the value of
137 * (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
138 * DIVIDE2 of this register.
139 * The hclk frequency should be less than 125Mhz.
140 * After writing a value to this field the SW should
141 * read the field for the value written.
142 * The ENABLE field of this register should not be set
143 * until AFTER this field is set and then read.
144 */
145 struct cvmx_usbnx_clk_ctl_s {
146 uint64_t reserved_20_63 : 44;
147 uint64_t divide2 : 2;
148 uint64_t hclk_rst : 1;
149 uint64_t p_x_on : 1;
150 uint64_t reserved_14_15 : 2;
151 uint64_t p_com_on : 1;
152 uint64_t p_c_sel : 2;
153 uint64_t cdiv_byp : 1;
154 uint64_t sd_mode : 2;
155 uint64_t s_bist : 1;
156 uint64_t por : 1;
157 uint64_t enable : 1;
158 uint64_t prst : 1;
159 uint64_t hrst : 1;
160 uint64_t divide : 3;
161 } s;
162 /**
163 * struct cvmx_usbnx_clk_ctl_cn30xx
164 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to
165 * generate the hclk in the USB Subsystem is held
166 * in reset. This bit must be set to '0' before
167 * changing the value os DIVIDE in this register.
168 * The reset to the HCLK_DIVIDERis also asserted
169 * when core reset is asserted.
170 * @p_x_on: Force USB-PHY on during suspend.
171 * '1' USB-PHY XO block is powered-down during
172 * suspend.
173 * '0' USB-PHY XO block is powered-up during
174 * suspend.
175 * The value of this field must be set while POR is
176 * active.
177 * @p_rclk: Phy refrence clock enable.
178 * '1' The PHY PLL uses the XO block output as a
179 * reference.
180 * '0' Reserved.
181 * @p_xenbn: Phy external clock enable.
182 * '1' The XO block uses the clock from a crystal.
183 * '0' The XO block uses an external clock supplied
184 * on the XO pin. USB_XI should be tied to
185 * ground for this usage.
186 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to
187 * remain powered in Suspend Mode.
188 * '1' The USB-PHY XO Bias, Bandgap and PLL are
189 * powered down in suspend mode.
190 * The value of this field must be set while POR is
191 * active.
192 * @p_c_sel: Phy clock speed select.
193 * Selects the reference clock / crystal frequency.
194 * '11': Reserved
195 * '10': 48 MHz
196 * '01': 24 MHz
197 * '00': 12 MHz
198 * The value of this field must be set while POR is
199 * active.
200 * @cdiv_byp: Used to enable the bypass input to the USB_CLK_DIV.
201 * @sd_mode: Scaledown mode for the USBC. Control timing events
202 * in the USBC, for normal operation this must be '0'.
203 * @s_bist: Starts bist on the hclk memories, during the '0'
204 * to '1' transition.
205 * @por: Power On Reset for the PHY.
206 * Resets all the PHYS registers and state machines.
207 * @enable: When '1' allows the generation of the hclk. When
208 * '0' the hclk will not be generated.
209 * @prst: When this field is '0' the reset associated with
210 * the phy_clk functionality in the USB Subsystem is
211 * help in reset. This bit should not be set to '1'
212 * until the time it takes 6 clocks (hclk or phy_clk,
213 * whichever is slower) has passed. Under normal
214 * operation once this bit is set to '1' it should not
215 * be set to '0'.
216 * @hrst: When this field is '0' the reset associated with
217 * the hclk functioanlity in the USB Subsystem is
218 * held in reset.This bit should not be set to '1'
219 * until 12ms after phy_clk is stable. Under normal
220 * operation, once this bit is set to '1' it should
221 * not be set to '0'.
222 * @divide: The 'hclk' used by the USB subsystem is derived
223 * from the eclk. The eclk will be divided by the
224 * value of this field +1 to determine the hclk
225 * frequency. (Also see HRST of this register).
226 * The hclk frequency must be less than 125 MHz.
227 */
228 struct cvmx_usbnx_clk_ctl_cn30xx {
229 uint64_t reserved_18_63 : 46;
230 uint64_t hclk_rst : 1;
231 uint64_t p_x_on : 1;
232 uint64_t p_rclk : 1;
233 uint64_t p_xenbn : 1;
234 uint64_t p_com_on : 1;
235 uint64_t p_c_sel : 2;
236 uint64_t cdiv_byp : 1;
237 uint64_t sd_mode : 2;
238 uint64_t s_bist : 1;
239 uint64_t por : 1;
240 uint64_t enable : 1;
241 uint64_t prst : 1;
242 uint64_t hrst : 1;
243 uint64_t divide : 3;
244 } cn30xx;
245 struct cvmx_usbnx_clk_ctl_cn30xx cn31xx;
246 /**
247 * struct cvmx_usbnx_clk_ctl_cn50xx
248 * @divide2: The 'hclk' used by the USB subsystem is derived
249 * from the eclk.
250 * Also see the field DIVIDE. DIVIDE2<1> must currently
251 * be zero because it is not implemented, so the maximum
252 * ratio of eclk/hclk is currently 16.
253 * The actual divide number for hclk is:
254 * (DIVIDE2 + 1) * (DIVIDE + 1)
255 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to
256 * generate the hclk in the USB Subsystem is held
257 * in reset. This bit must be set to '0' before
258 * changing the value os DIVIDE in this register.
259 * The reset to the HCLK_DIVIDERis also asserted
260 * when core reset is asserted.
261 * @p_rtype: PHY reference clock type
262 * '0' The USB-PHY uses a 12MHz crystal as a clock
263 * source at the USB_XO and USB_XI pins
264 * '1' Reserved
265 * '2' The USB_PHY uses 12/24/48MHz 2.5V board clock
266 * at the USB_XO pin. USB_XI should be tied to
267 * ground in this case.
268 * '3' Reserved
269 * (bit 14 was P_XENBN on 3xxx)
270 * (bit 15 was P_RCLK on 3xxx)
271 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to
272 * remain powered in Suspend Mode.
273 * '1' The USB-PHY XO Bias, Bandgap and PLL are
274 * powered down in suspend mode.
275 * The value of this field must be set while POR is
276 * active.
277 * @p_c_sel: Phy clock speed select.
278 * Selects the reference clock / crystal frequency.
279 * '11': Reserved
280 * '10': 48 MHz (reserved when a crystal is used)
281 * '01': 24 MHz (reserved when a crystal is used)
282 * '00': 12 MHz
283 * The value of this field must be set while POR is
284 * active.
285 * NOTE: if a crystal is used as a reference clock,
286 * this field must be set to 12 MHz.
287 * @cdiv_byp: Used to enable the bypass input to the USB_CLK_DIV.
288 * @sd_mode: Scaledown mode for the USBC. Control timing events
289 * in the USBC, for normal operation this must be '0'.
290 * @s_bist: Starts bist on the hclk memories, during the '0'
291 * to '1' transition.
292 * @por: Power On Reset for the PHY.
293 * Resets all the PHYS registers and state machines.
294 * @enable: When '1' allows the generation of the hclk. When
295 * '0' the hclk will not be generated. SEE DIVIDE
296 * field of this register.
297 * @prst: When this field is '0' the reset associated with
298 * the phy_clk functionality in the USB Subsystem is
299 * help in reset. This bit should not be set to '1'
300 * until the time it takes 6 clocks (hclk or phy_clk,
301 * whichever is slower) has passed. Under normal
302 * operation once this bit is set to '1' it should not
303 * be set to '0'.
304 * @hrst: When this field is '0' the reset associated with
305 * the hclk functioanlity in the USB Subsystem is
306 * held in reset.This bit should not be set to '1'
307 * until 12ms after phy_clk is stable. Under normal
308 * operation, once this bit is set to '1' it should
309 * not be set to '0'.
310 * @divide: The frequency of 'hclk' used by the USB subsystem
311 * is the eclk frequency divided by the value of
312 * (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
313 * DIVIDE2 of this register.
314 * The hclk frequency should be less than 125Mhz.
315 * After writing a value to this field the SW should
316 * read the field for the value written.
317 * The ENABLE field of this register should not be set
318 * until AFTER this field is set and then read.
319 */
320 struct cvmx_usbnx_clk_ctl_cn50xx {
321 uint64_t reserved_20_63 : 44;
322 uint64_t divide2 : 2;
323 uint64_t hclk_rst : 1;
324 uint64_t reserved_16_16 : 1;
325 uint64_t p_rtype : 2;
326 uint64_t p_com_on : 1;
327 uint64_t p_c_sel : 2;
328 uint64_t cdiv_byp : 1;
329 uint64_t sd_mode : 2;
330 uint64_t s_bist : 1;
331 uint64_t por : 1;
332 uint64_t enable : 1;
333 uint64_t prst : 1;
334 uint64_t hrst : 1;
335 uint64_t divide : 3;
336 } cn50xx;
337 struct cvmx_usbnx_clk_ctl_cn50xx cn52xx;
338 struct cvmx_usbnx_clk_ctl_cn50xx cn56xx;
339 };
340 typedef union cvmx_usbnx_clk_ctl cvmx_usbnx_clk_ctl_t;
341
342 /**
343 * cvmx_usbn#_usbp_ctl_status
344 *
345 * USBN_USBP_CTL_STATUS = USBP Control And Status Register
346 *
347 * Contains general control and status information for the USBN block.
348 */
349 union cvmx_usbnx_usbp_ctl_status {
350 uint64_t u64;
351 /**
352 * struct cvmx_usbnx_usbp_ctl_status_s
353 * @txrisetune: HS Transmitter Rise/Fall Time Adjustment
354 * @txvreftune: HS DC Voltage Level Adjustment
355 * @txfslstune: FS/LS Source Impedence Adjustment
356 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment
357 * @sqrxtune: Squelch Threshold Adjustment
358 * @compdistune: Disconnect Threshold Adjustment
359 * @otgtune: VBUS Valid Threshold Adjustment
360 * @otgdisable: OTG Block Disable
361 * @portreset: Per_Port Reset
362 * @drvvbus: Drive VBUS
363 * @lsbist: Low-Speed BIST Enable.
364 * @fsbist: Full-Speed BIST Enable.
365 * @hsbist: High-Speed BIST Enable.
366 * @bist_done: PHY Bist Done.
367 * Asserted at the end of the PHY BIST sequence.
368 * @bist_err: PHY Bist Error.
369 * Indicates an internal error was detected during
370 * the BIST sequence.
371 * @tdata_out: PHY Test Data Out.
372 * Presents either internaly generated signals or
373 * test register contents, based upon the value of
374 * test_data_out_sel.
375 * @siddq: Drives the USBP (USB-PHY) SIDDQ input.
376 * Normally should be set to zero.
377 * When customers have no intent to use USB PHY
378 * interface, they should:
379 * - still provide 3.3V to USB_VDD33, and
380 * - tie USB_REXT to 3.3V supply, and
381 * - set USBN*_USBP_CTL_STATUS[SIDDQ]=1
382 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
383 * @dma_bmode: When set to 1 the L2C DMA address will be updated
384 * with byte-counts between packets. When set to 0
385 * the L2C DMA address is incremented to the next
386 * 4-byte aligned address after adding byte-count.
387 * @usbc_end: Bigendian input to the USB Core. This should be
388 * set to '0' for operation.
389 * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP.
390 * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP.
391 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
392 * This signal enables the pull-down resistance on
393 * the D+ line. '1' pull down-resistance is connected
394 * to D+/ '0' pull down resistance is not connected
395 * to D+. When an A/B device is acting as a host
396 * (downstream-facing port), dp_pulldown and
397 * dm_pulldown are enabled. This must not toggle
398 * during normal opeartion.
399 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
400 * This signal enables the pull-down resistance on
401 * the D- line. '1' pull down-resistance is connected
402 * to D-. '0' pull down resistance is not connected
403 * to D-. When an A/B device is acting as a host
404 * (downstream-facing port), dp_pulldown and
405 * dm_pulldown are enabled. This must not toggle
406 * during normal opeartion.
407 * @hst_mode: When '0' the USB is acting as HOST, when '1'
408 * USB is acting as device. This field needs to be
409 * set while the USB is in reset.
410 * @tuning: Transmitter Tuning for High-Speed Operation.
411 * Tunes the current supply and rise/fall output
412 * times for high-speed operation.
413 * [20:19] == 11: Current supply increased
414 * approximately 9%
415 * [20:19] == 10: Current supply increased
416 * approximately 4.5%
417 * [20:19] == 01: Design default.
418 * [20:19] == 00: Current supply decreased
419 * approximately 4.5%
420 * [22:21] == 11: Rise and fall times are increased.
421 * [22:21] == 10: Design default.
422 * [22:21] == 01: Rise and fall times are decreased.
423 * [22:21] == 00: Rise and fall times are decreased
424 * further as compared to the 01 setting.
425 * @tx_bs_enh: Transmit Bit Stuffing on [15:8].
426 * Enables or disables bit stuffing on data[15:8]
427 * when bit-stuffing is enabled.
428 * @tx_bs_en: Transmit Bit Stuffing on [7:0].
429 * Enables or disables bit stuffing on data[7:0]
430 * when bit-stuffing is enabled.
431 * @loop_enb: PHY Loopback Test Enable.
432 * '1': During data transmission the receive is
433 * enabled.
434 * '0': During data transmission the receive is
435 * disabled.
436 * Must be '0' for normal operation.
437 * @vtest_enb: Analog Test Pin Enable.
438 * '1' The PHY's analog_test pin is enabled for the
439 * input and output of applicable analog test signals.
440 * '0' THe analog_test pin is disabled.
441 * @bist_enb: Built-In Self Test Enable.
442 * Used to activate BIST in the PHY.
443 * @tdata_sel: Test Data Out Select.
444 * '1' test_data_out[3:0] (PHY) register contents
445 * are output. '0' internaly generated signals are
446 * output.
447 * @taddr_in: Mode Address for Test Interface.
448 * Specifies the register address for writing to or
449 * reading from the PHY test interface register.
450 * @tdata_in: Internal Testing Register Input Data and Select
451 * This is a test bus. Data is present on [3:0],
452 * and its corresponding select (enable) is present
453 * on bits [7:4].
454 * @ate_reset: Reset input from automatic test equipment.
455 * This is a test signal. When the USB Core is
456 * powered up (not in Susned Mode), an automatic
457 * tester can use this to disable phy_clock and
458 * free_clk, then re-eanable them with an aligned
459 * phase.
460 * '1': The phy_clk and free_clk outputs are
461 * disabled. "0": The phy_clock and free_clk outputs
462 * are available within a specific period after the
463 * de-assertion.
464 */
465 struct cvmx_usbnx_usbp_ctl_status_s {
466 uint64_t txrisetune : 1;
467 uint64_t txvreftune : 4;
468 uint64_t txfslstune : 4;
469 uint64_t txhsxvtune : 2;
470 uint64_t sqrxtune : 3;
471 uint64_t compdistune : 3;
472 uint64_t otgtune : 3;
473 uint64_t otgdisable : 1;
474 uint64_t portreset : 1;
475 uint64_t drvvbus : 1;
476 uint64_t lsbist : 1;
477 uint64_t fsbist : 1;
478 uint64_t hsbist : 1;
479 uint64_t bist_done : 1;
480 uint64_t bist_err : 1;
481 uint64_t tdata_out : 4;
482 uint64_t siddq : 1;
483 uint64_t txpreemphasistune : 1;
484 uint64_t dma_bmode : 1;
485 uint64_t usbc_end : 1;
486 uint64_t usbp_bist : 1;
487 uint64_t tclk : 1;
488 uint64_t dp_pulld : 1;
489 uint64_t dm_pulld : 1;
490 uint64_t hst_mode : 1;
491 uint64_t tuning : 4;
492 uint64_t tx_bs_enh : 1;
493 uint64_t tx_bs_en : 1;
494 uint64_t loop_enb : 1;
495 uint64_t vtest_enb : 1;
496 uint64_t bist_enb : 1;
497 uint64_t tdata_sel : 1;
498 uint64_t taddr_in : 4;
499 uint64_t tdata_in : 8;
500 uint64_t ate_reset : 1;
501 } s;
502 /**
503 * struct cvmx_usbnx_usbp_ctl_status_cn30xx
504 * @bist_done: PHY Bist Done.
505 * Asserted at the end of the PHY BIST sequence.
506 * @bist_err: PHY Bist Error.
507 * Indicates an internal error was detected during
508 * the BIST sequence.
509 * @tdata_out: PHY Test Data Out.
510 * Presents either internaly generated signals or
511 * test register contents, based upon the value of
512 * test_data_out_sel.
513 * @dma_bmode: When set to 1 the L2C DMA address will be updated
514 * with byte-counts between packets. When set to 0
515 * the L2C DMA address is incremented to the next
516 * 4-byte aligned address after adding byte-count.
517 * @usbc_end: Bigendian input to the USB Core. This should be
518 * set to '0' for operation.
519 * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP.
520 * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP.
521 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
522 * This signal enables the pull-down resistance on
523 * the D+ line. '1' pull down-resistance is connected
524 * to D+/ '0' pull down resistance is not connected
525 * to D+. When an A/B device is acting as a host
526 * (downstream-facing port), dp_pulldown and
527 * dm_pulldown are enabled. This must not toggle
528 * during normal opeartion.
529 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
530 * This signal enables the pull-down resistance on
531 * the D- line. '1' pull down-resistance is connected
532 * to D-. '0' pull down resistance is not connected
533 * to D-. When an A/B device is acting as a host
534 * (downstream-facing port), dp_pulldown and
535 * dm_pulldown are enabled. This must not toggle
536 * during normal opeartion.
537 * @hst_mode: When '0' the USB is acting as HOST, when '1'
538 * USB is acting as device. This field needs to be
539 * set while the USB is in reset.
540 * @tuning: Transmitter Tuning for High-Speed Operation.
541 * Tunes the current supply and rise/fall output
542 * times for high-speed operation.
543 * [20:19] == 11: Current supply increased
544 * approximately 9%
545 * [20:19] == 10: Current supply increased
546 * approximately 4.5%
547 * [20:19] == 01: Design default.
548 * [20:19] == 00: Current supply decreased
549 * approximately 4.5%
550 * [22:21] == 11: Rise and fall times are increased.
551 * [22:21] == 10: Design default.
552 * [22:21] == 01: Rise and fall times are decreased.
553 * [22:21] == 00: Rise and fall times are decreased
554 * further as compared to the 01 setting.
555 * @tx_bs_enh: Transmit Bit Stuffing on [15:8].
556 * Enables or disables bit stuffing on data[15:8]
557 * when bit-stuffing is enabled.
558 * @tx_bs_en: Transmit Bit Stuffing on [7:0].
559 * Enables or disables bit stuffing on data[7:0]
560 * when bit-stuffing is enabled.
561 * @loop_enb: PHY Loopback Test Enable.
562 * '1': During data transmission the receive is
563 * enabled.
564 * '0': During data transmission the receive is
565 * disabled.
566 * Must be '0' for normal operation.
567 * @vtest_enb: Analog Test Pin Enable.
568 * '1' The PHY's analog_test pin is enabled for the
569 * input and output of applicable analog test signals.
570 * '0' THe analog_test pin is disabled.
571 * @bist_enb: Built-In Self Test Enable.
572 * Used to activate BIST in the PHY.
573 * @tdata_sel: Test Data Out Select.
574 * '1' test_data_out[3:0] (PHY) register contents
575 * are output. '0' internaly generated signals are
576 * output.
577 * @taddr_in: Mode Address for Test Interface.
578 * Specifies the register address for writing to or
579 * reading from the PHY test interface register.
580 * @tdata_in: Internal Testing Register Input Data and Select
581 * This is a test bus. Data is present on [3:0],
582 * and its corresponding select (enable) is present
583 * on bits [7:4].
584 * @ate_reset: Reset input from automatic test equipment.
585 * This is a test signal. When the USB Core is
586 * powered up (not in Susned Mode), an automatic
587 * tester can use this to disable phy_clock and
588 * free_clk, then re-eanable them with an aligned
589 * phase.
590 * '1': The phy_clk and free_clk outputs are
591 * disabled. "0": The phy_clock and free_clk outputs
592 * are available within a specific period after the
593 * de-assertion.
594 */
595 struct cvmx_usbnx_usbp_ctl_status_cn30xx {
596 uint64_t reserved_38_63 : 26;
597 uint64_t bist_done : 1;
598 uint64_t bist_err : 1;
599 uint64_t tdata_out : 4;
600 uint64_t reserved_30_31 : 2;
601 uint64_t dma_bmode : 1;
602 uint64_t usbc_end : 1;
603 uint64_t usbp_bist : 1;
604 uint64_t tclk : 1;
605 uint64_t dp_pulld : 1;
606 uint64_t dm_pulld : 1;
607 uint64_t hst_mode : 1;
608 uint64_t tuning : 4;
609 uint64_t tx_bs_enh : 1;
610 uint64_t tx_bs_en : 1;
611 uint64_t loop_enb : 1;
612 uint64_t vtest_enb : 1;
613 uint64_t bist_enb : 1;
614 uint64_t tdata_sel : 1;
615 uint64_t taddr_in : 4;
616 uint64_t tdata_in : 8;
617 uint64_t ate_reset : 1;
618 } cn30xx;
619 /**
620 * struct cvmx_usbnx_usbp_ctl_status_cn50xx
621 * @txrisetune: HS Transmitter Rise/Fall Time Adjustment
622 * @txvreftune: HS DC Voltage Level Adjustment
623 * @txfslstune: FS/LS Source Impedence Adjustment
624 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment
625 * @sqrxtune: Squelch Threshold Adjustment
626 * @compdistune: Disconnect Threshold Adjustment
627 * @otgtune: VBUS Valid Threshold Adjustment
628 * @otgdisable: OTG Block Disable
629 * @portreset: Per_Port Reset
630 * @drvvbus: Drive VBUS
631 * @lsbist: Low-Speed BIST Enable.
632 * @fsbist: Full-Speed BIST Enable.
633 * @hsbist: High-Speed BIST Enable.
634 * @bist_done: PHY Bist Done.
635 * Asserted at the end of the PHY BIST sequence.
636 * @bist_err: PHY Bist Error.
637 * Indicates an internal error was detected during
638 * the BIST sequence.
639 * @tdata_out: PHY Test Data Out.
640 * Presents either internaly generated signals or
641 * test register contents, based upon the value of
642 * test_data_out_sel.
643 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
644 * @dma_bmode: When set to 1 the L2C DMA address will be updated
645 * with byte-counts between packets. When set to 0
646 * the L2C DMA address is incremented to the next
647 * 4-byte aligned address after adding byte-count.
648 * @usbc_end: Bigendian input to the USB Core. This should be
649 * set to '0' for operation.
650 * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP.
651 * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP.
652 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
653 * This signal enables the pull-down resistance on
654 * the D+ line. '1' pull down-resistance is connected
655 * to D+/ '0' pull down resistance is not connected
656 * to D+. When an A/B device is acting as a host
657 * (downstream-facing port), dp_pulldown and
658 * dm_pulldown are enabled. This must not toggle
659 * during normal opeartion.
660 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
661 * This signal enables the pull-down resistance on
662 * the D- line. '1' pull down-resistance is connected
663 * to D-. '0' pull down resistance is not connected
664 * to D-. When an A/B device is acting as a host
665 * (downstream-facing port), dp_pulldown and
666 * dm_pulldown are enabled. This must not toggle
667 * during normal opeartion.
668 * @hst_mode: When '0' the USB is acting as HOST, when '1'
669 * USB is acting as device. This field needs to be
670 * set while the USB is in reset.
671 * @tx_bs_enh: Transmit Bit Stuffing on [15:8].
672 * Enables or disables bit stuffing on data[15:8]
673 * when bit-stuffing is enabled.
674 * @tx_bs_en: Transmit Bit Stuffing on [7:0].
675 * Enables or disables bit stuffing on data[7:0]
676 * when bit-stuffing is enabled.
677 * @loop_enb: PHY Loopback Test Enable.
678 * '1': During data transmission the receive is
679 * enabled.
680 * '0': During data transmission the receive is
681 * disabled.
682 * Must be '0' for normal operation.
683 * @vtest_enb: Analog Test Pin Enable.
684 * '1' The PHY's analog_test pin is enabled for the
685 * input and output of applicable analog test signals.
686 * '0' THe analog_test pin is disabled.
687 * @bist_enb: Built-In Self Test Enable.
688 * Used to activate BIST in the PHY.
689 * @tdata_sel: Test Data Out Select.
690 * '1' test_data_out[3:0] (PHY) register contents
691 * are output. '0' internaly generated signals are
692 * output.
693 * @taddr_in: Mode Address for Test Interface.
694 * Specifies the register address for writing to or
695 * reading from the PHY test interface register.
696 * @tdata_in: Internal Testing Register Input Data and Select
697 * This is a test bus. Data is present on [3:0],
698 * and its corresponding select (enable) is present
699 * on bits [7:4].
700 * @ate_reset: Reset input from automatic test equipment.
701 * This is a test signal. When the USB Core is
702 * powered up (not in Susned Mode), an automatic
703 * tester can use this to disable phy_clock and
704 * free_clk, then re-eanable them with an aligned
705 * phase.
706 * '1': The phy_clk and free_clk outputs are
707 * disabled. "0": The phy_clock and free_clk outputs
708 * are available within a specific period after the
709 * de-assertion.
710 */
711 struct cvmx_usbnx_usbp_ctl_status_cn50xx {
712 uint64_t txrisetune : 1;
713 uint64_t txvreftune : 4;
714 uint64_t txfslstune : 4;
715 uint64_t txhsxvtune : 2;
716 uint64_t sqrxtune : 3;
717 uint64_t compdistune : 3;
718 uint64_t otgtune : 3;
719 uint64_t otgdisable : 1;
720 uint64_t portreset : 1;
721 uint64_t drvvbus : 1;
722 uint64_t lsbist : 1;
723 uint64_t fsbist : 1;
724 uint64_t hsbist : 1;
725 uint64_t bist_done : 1;
726 uint64_t bist_err : 1;
727 uint64_t tdata_out : 4;
728 uint64_t reserved_31_31 : 1;
729 uint64_t txpreemphasistune : 1;
730 uint64_t dma_bmode : 1;
731 uint64_t usbc_end : 1;
732 uint64_t usbp_bist : 1;
733 uint64_t tclk : 1;
734 uint64_t dp_pulld : 1;
735 uint64_t dm_pulld : 1;
736 uint64_t hst_mode : 1;
737 uint64_t reserved_19_22 : 4;
738 uint64_t tx_bs_enh : 1;
739 uint64_t tx_bs_en : 1;
740 uint64_t loop_enb : 1;
741 uint64_t vtest_enb : 1;
742 uint64_t bist_enb : 1;
743 uint64_t tdata_sel : 1;
744 uint64_t taddr_in : 4;
745 uint64_t tdata_in : 8;
746 uint64_t ate_reset : 1;
747 } cn50xx;
748 /**
749 * struct cvmx_usbnx_usbp_ctl_status_cn52xx
750 * @txrisetune: HS Transmitter Rise/Fall Time Adjustment
751 * @txvreftune: HS DC Voltage Level Adjustment
752 * @txfslstune: FS/LS Source Impedence Adjustment
753 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment
754 * @sqrxtune: Squelch Threshold Adjustment
755 * @compdistune: Disconnect Threshold Adjustment
756 * @otgtune: VBUS Valid Threshold Adjustment
757 * @otgdisable: OTG Block Disable
758 * @portreset: Per_Port Reset
759 * @drvvbus: Drive VBUS
760 * @lsbist: Low-Speed BIST Enable.
761 * @fsbist: Full-Speed BIST Enable.
762 * @hsbist: High-Speed BIST Enable.
763 * @bist_done: PHY Bist Done.
764 * Asserted at the end of the PHY BIST sequence.
765 * @bist_err: PHY Bist Error.
766 * Indicates an internal error was detected during
767 * the BIST sequence.
768 * @tdata_out: PHY Test Data Out.
769 * Presents either internaly generated signals or
770 * test register contents, based upon the value of
771 * test_data_out_sel.
772 * @siddq: Drives the USBP (USB-PHY) SIDDQ input.
773 * Normally should be set to zero.
774 * When customers have no intent to use USB PHY
775 * interface, they should:
776 * - still provide 3.3V to USB_VDD33, and
777 * - tie USB_REXT to 3.3V supply, and
778 * - set USBN*_USBP_CTL_STATUS[SIDDQ]=1
779 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
780 * @dma_bmode: When set to 1 the L2C DMA address will be updated
781 * with byte-counts between packets. When set to 0
782 * the L2C DMA address is incremented to the next
783 * 4-byte aligned address after adding byte-count.
784 * @usbc_end: Bigendian input to the USB Core. This should be
785 * set to '0' for operation.
786 * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP.
787 * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP.
788 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
789 * This signal enables the pull-down resistance on
790 * the D+ line. '1' pull down-resistance is connected
791 * to D+/ '0' pull down resistance is not connected
792 * to D+. When an A/B device is acting as a host
793 * (downstream-facing port), dp_pulldown and
794 * dm_pulldown are enabled. This must not toggle
795 * during normal opeartion.
796 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
797 * This signal enables the pull-down resistance on
798 * the D- line. '1' pull down-resistance is connected
799 * to D-. '0' pull down resistance is not connected
800 * to D-. When an A/B device is acting as a host
801 * (downstream-facing port), dp_pulldown and
802 * dm_pulldown are enabled. This must not toggle
803 * during normal opeartion.
804 * @hst_mode: When '0' the USB is acting as HOST, when '1'
805 * USB is acting as device. This field needs to be
806 * set while the USB is in reset.
807 * @tx_bs_enh: Transmit Bit Stuffing on [15:8].
808 * Enables or disables bit stuffing on data[15:8]
809 * when bit-stuffing is enabled.
810 * @tx_bs_en: Transmit Bit Stuffing on [7:0].
811 * Enables or disables bit stuffing on data[7:0]
812 * when bit-stuffing is enabled.
813 * @loop_enb: PHY Loopback Test Enable.
814 * '1': During data transmission the receive is
815 * enabled.
816 * '0': During data transmission the receive is
817 * disabled.
818 * Must be '0' for normal operation.
819 * @vtest_enb: Analog Test Pin Enable.
820 * '1' The PHY's analog_test pin is enabled for the
821 * input and output of applicable analog test signals.
822 * '0' THe analog_test pin is disabled.
823 * @bist_enb: Built-In Self Test Enable.
824 * Used to activate BIST in the PHY.
825 * @tdata_sel: Test Data Out Select.
826 * '1' test_data_out[3:0] (PHY) register contents
827 * are output. '0' internaly generated signals are
828 * output.
829 * @taddr_in: Mode Address for Test Interface.
830 * Specifies the register address for writing to or
831 * reading from the PHY test interface register.
832 * @tdata_in: Internal Testing Register Input Data and Select
833 * This is a test bus. Data is present on [3:0],
834 * and its corresponding select (enable) is present
835 * on bits [7:4].
836 * @ate_reset: Reset input from automatic test equipment.
837 * This is a test signal. When the USB Core is
838 * powered up (not in Susned Mode), an automatic
839 * tester can use this to disable phy_clock and
840 * free_clk, then re-eanable them with an aligned
841 * phase.
842 * '1': The phy_clk and free_clk outputs are
843 * disabled. "0": The phy_clock and free_clk outputs
844 * are available within a specific period after the
845 * de-assertion.
846 */
847 struct cvmx_usbnx_usbp_ctl_status_cn52xx {
848 uint64_t txrisetune : 1;
849 uint64_t txvreftune : 4;
850 uint64_t txfslstune : 4;
851 uint64_t txhsxvtune : 2;
852 uint64_t sqrxtune : 3;
853 uint64_t compdistune : 3;
854 uint64_t otgtune : 3;
855 uint64_t otgdisable : 1;
856 uint64_t portreset : 1;
857 uint64_t drvvbus : 1;
858 uint64_t lsbist : 1;
859 uint64_t fsbist : 1;
860 uint64_t hsbist : 1;
861 uint64_t bist_done : 1;
862 uint64_t bist_err : 1;
863 uint64_t tdata_out : 4;
864 uint64_t siddq : 1;
865 uint64_t txpreemphasistune : 1;
866 uint64_t dma_bmode : 1;
867 uint64_t usbc_end : 1;
868 uint64_t usbp_bist : 1;
869 uint64_t tclk : 1;
870 uint64_t dp_pulld : 1;
871 uint64_t dm_pulld : 1;
872 uint64_t hst_mode : 1;
873 uint64_t reserved_19_22 : 4;
874 uint64_t tx_bs_enh : 1;
875 uint64_t tx_bs_en : 1;
876 uint64_t loop_enb : 1;
877 uint64_t vtest_enb : 1;
878 uint64_t bist_enb : 1;
879 uint64_t tdata_sel : 1;
880 uint64_t taddr_in : 4;
881 uint64_t tdata_in : 8;
882 uint64_t ate_reset : 1;
883 } cn52xx;
884 };
885 typedef union cvmx_usbnx_usbp_ctl_status cvmx_usbnx_usbp_ctl_status_t;
886
887 #endif
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