target/linux/octeon/files/drivers/staging/octeon-usb/cvmx-usbcx-defs.h

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  40
  41 /**
  42  * cvmx-usbcx-defs.h
  43  *
  44  * Configuration and status register (CSR) type definitions for
  45  * Octeon usbcx.
  46  *
  47  */
  48 #ifndef __CVMX_USBCX_TYPEDEFS_H__
  49 #define __CVMX_USBCX_TYPEDEFS_H__
  50
  51 #define CVMX_USBCXBASE 0x00016F0010000000ull
  52 #define CVMX_USBCXREG1(reg, bid) \
  53         (CVMX_ADD_IO_SEG(CVMX_USBCXBASE | reg) + \
  54          ((bid) & 1) * 0x100000000000ull)
  55 #define CVMX_USBCXREG2(reg, bid, off) \
  56         (CVMX_ADD_IO_SEG(CVMX_USBCXBASE | reg) + \
  57          (((off) & 7) + ((bid) & 1) * 0x8000000000ull) * 32)
  58
  59 #define CVMX_USBCX_GAHBCFG(bid)         CVMX_USBCXREG1(0x008, bid)
  60 #define CVMX_USBCX_GHWCFG3(bid)         CVMX_USBCXREG1(0x04c, bid)
  61 #define CVMX_USBCX_GINTMSK(bid)         CVMX_USBCXREG1(0x018, bid)
  62 #define CVMX_USBCX_GINTSTS(bid)         CVMX_USBCXREG1(0x014, bid)
  63 #define CVMX_USBCX_GNPTXFSIZ(bid)       CVMX_USBCXREG1(0x028, bid)
  64 #define CVMX_USBCX_GNPTXSTS(bid)        CVMX_USBCXREG1(0x02c, bid)
  65 #define CVMX_USBCX_GOTGCTL(bid)         CVMX_USBCXREG1(0x000, bid)
  66 #define CVMX_USBCX_GRSTCTL(bid)         CVMX_USBCXREG1(0x010, bid)
  67 #define CVMX_USBCX_GRXFSIZ(bid)         CVMX_USBCXREG1(0x024, bid)
  68 #define CVMX_USBCX_GRXSTSPH(bid)        CVMX_USBCXREG1(0x020, bid)
  69 #define CVMX_USBCX_GUSBCFG(bid)         CVMX_USBCXREG1(0x00c, bid)
  70 #define CVMX_USBCX_HAINT(bid)           CVMX_USBCXREG1(0x414, bid)
  71 #define CVMX_USBCX_HAINTMSK(bid)        CVMX_USBCXREG1(0x418, bid)
  72 #define CVMX_USBCX_HCCHARX(off, bid)    CVMX_USBCXREG2(0x500, bid, off)
  73 #define CVMX_USBCX_HCFG(bid)            CVMX_USBCXREG1(0x400, bid)
  74 #define CVMX_USBCX_HCINTMSKX(off, bid)  CVMX_USBCXREG2(0x50c, bid, off)
  75 #define CVMX_USBCX_HCINTX(off, bid)     CVMX_USBCXREG2(0x508, bid, off)
  76 #define CVMX_USBCX_HCSPLTX(off, bid)    CVMX_USBCXREG2(0x504, bid, off)
  77 #define CVMX_USBCX_HCTSIZX(off, bid)    CVMX_USBCXREG2(0x510, bid, off)
  78 #define CVMX_USBCX_HFIR(bid)            CVMX_USBCXREG1(0x404, bid)
  79 #define CVMX_USBCX_HFNUM(bid)           CVMX_USBCXREG1(0x408, bid)
  80 #define CVMX_USBCX_HPRT(bid)            CVMX_USBCXREG1(0x440, bid)
  81 #define CVMX_USBCX_HPTXFSIZ(bid)        CVMX_USBCXREG1(0x100, bid)
  82 #define CVMX_USBCX_HPTXSTS(bid)         CVMX_USBCXREG1(0x410, bid)
  83
  84 /**
  85  * cvmx_usbc#_gahbcfg
  86  *
  87  * Core AHB Configuration Register (GAHBCFG)
  88  *
  89  * This register can be used to configure the core after power-on or a change in
  90  * mode of operation. This register mainly contains AHB system-related
  91  * configuration parameters. The AHB is the processor interface to the O2P USB
  92  * core. In general, software need not know about this interface except to
  93  * program the values as specified.
  94  *
  95  * The application must program this register as part of the O2P USB core
  96  * initialization. Do not change this register after the initial programming.
  97  */
  98 union cvmx_usbcx_gahbcfg {
  99         uint32_t u32;
 100         /**
 101          * struct cvmx_usbcx_gahbcfg_s
 102          * @ptxfemplvl: Periodic TxFIFO Empty Level (PTxFEmpLvl)
 103          *      Software should set this bit to 0x1.
 104          *      Indicates when the Periodic TxFIFO Empty Interrupt bit in the
 105          *      Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This
 106          *      bit is used only in Slave mode.
 107          *      * 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic
 108          *      TxFIFO is half empty
 109          *      * 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic
 110          *      TxFIFO is completely empty
 111          * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
 112          *      Software should set this bit to 0x1.
 113          *      Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
 114          *      the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered.
 115          *      This bit is used only in Slave mode.
 116          *      * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
 117          *      Periodic TxFIFO is half empty
 118          *      * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
 119          *      Periodic TxFIFO is completely empty
 120          * @dmaen: DMA Enable (DMAEn)
 121          *      * 1'b0: Core operates in Slave mode
 122          *      * 1'b1: Core operates in a DMA mode
 123          * @hbstlen: Burst Length/Type (HBstLen)
 124          *      This field has not effect and should be left as 0x0.
 125          * @glblintrmsk: Global Interrupt Mask (GlblIntrMsk)
 126          *      Software should set this field to 0x1.
 127          *      The application uses this bit to mask or unmask the interrupt
 128          *      line assertion to itself. Irrespective of this bit's setting,
 129          *      the interrupt status registers are updated by the core.
 130          *      * 1'b0: Mask the interrupt assertion to the application.
 131          *      * 1'b1: Unmask the interrupt assertion to the application.
 132          */
 133         struct cvmx_usbcx_gahbcfg_s {
 134                 uint32_t reserved_9_31  : 23;
 135                 uint32_t ptxfemplvl     : 1;
 136                 uint32_t nptxfemplvl    : 1;
 137                 uint32_t reserved_6_6   : 1;
 138                 uint32_t dmaen          : 1;
 139                 uint32_t hbstlen        : 4;
 140                 uint32_t glblintrmsk    : 1;
 141         } s;
 142 };
 143 typedef union cvmx_usbcx_gahbcfg cvmx_usbcx_gahbcfg_t;
 144
 145 /**
 146  * cvmx_usbc#_ghwcfg3
 147  *
 148  * User HW Config3 Register (GHWCFG3)
 149  *
 150  * This register contains the configuration options of the O2P USB core.
 151  */
 152 union cvmx_usbcx_ghwcfg3 {
 153         uint32_t u32;
 154         /**
 155          * struct cvmx_usbcx_ghwcfg3_s
 156          * @dfifodepth: DFIFO Depth (DfifoDepth)
 157          *      This value is in terms of 32-bit words.
 158          *      * Minimum value is 32
 159          *      * Maximum value is 32768
 160          * @ahbphysync: AHB and PHY Synchronous (AhbPhySync)
 161          *      Indicates whether AHB and PHY clocks are synchronous to
 162          *      each other.
 163          *      * 1'b0: No
 164          *      * 1'b1: Yes
 165          *      This bit is tied to 1.
 166          * @rsttype: Reset Style for Clocked always Blocks in RTL (RstType)
 167          *      * 1'b0: Asynchronous reset is used in the core
 168          *      * 1'b1: Synchronous reset is used in the core
 169          * @optfeature: Optional Features Removed (OptFeature)
 170          *      Indicates whether the User ID register, GPIO interface ports,
 171          *      and SOF toggle and counter ports were removed for gate count
 172          *      optimization.
 173          * @vendor_control_interface_support: Vendor Control Interface Support
 174          *      * 1'b0: Vendor Control Interface is not available on the core.
 175          *      * 1'b1: Vendor Control Interface is available.
 176          * @i2c_selection: I2C Selection
 177          *      * 1'b0: I2C Interface is not available on the core.
 178          *      * 1'b1: I2C Interface is available on the core.
 179          * @otgen: OTG Function Enabled (OtgEn)
 180          *      The application uses this bit to indicate the O2P USB core's
 181          *      OTG capabilities.
 182          *      * 1'b0: Not OTG capable
 183          *      * 1'b1: OTG Capable
 184          * @pktsizewidth: Width of Packet Size Counters (PktSizeWidth)
 185          *      * 3'b000: 4 bits
 186          *      * 3'b001: 5 bits
 187          *      * 3'b010: 6 bits
 188          *      * 3'b011: 7 bits
 189          *      * 3'b100: 8 bits
 190          *      * 3'b101: 9 bits
 191          *      * 3'b110: 10 bits
 192          *      * Others: Reserved
 193          * @xfersizewidth: Width of Transfer Size Counters (XferSizeWidth)
 194          *      * 4'b0000: 11 bits
 195          *      * 4'b0001: 12 bits
 196          *      - ...
 197          *      * 4'b1000: 19 bits
 198          *      * Others: Reserved
 199          */
 200         struct cvmx_usbcx_ghwcfg3_s {
 201                 uint32_t dfifodepth                             : 16;
 202                 uint32_t reserved_13_15                         : 3;
 203                 uint32_t ahbphysync                             : 1;
 204                 uint32_t rsttype                                : 1;
 205                 uint32_t optfeature                             : 1;
 206                 uint32_t vendor_control_interface_support       : 1;
 207                 uint32_t i2c_selection                          : 1;
 208                 uint32_t otgen                                  : 1;
 209                 uint32_t pktsizewidth                           : 3;
 210                 uint32_t xfersizewidth                          : 4;
 211         } s;
 212 };
 213 typedef union cvmx_usbcx_ghwcfg3 cvmx_usbcx_ghwcfg3_t;
 214
 215 /**
 216  * cvmx_usbc#_gintmsk
 217  *
 218  * Core Interrupt Mask Register (GINTMSK)
 219  *
 220  * This register works with the Core Interrupt register to interrupt the
 221  * application. When an interrupt bit is masked, the interrupt associated with
 222  * that bit will not be generated. However, the Core Interrupt (GINTSTS)
 223  * register bit corresponding to that interrupt will still be set.
 224  * Mask interrupt: 1'b0, Unmask interrupt: 1'b1
 225  */
 226 union cvmx_usbcx_gintmsk {
 227         uint32_t u32;
 228         /**
 229          * struct cvmx_usbcx_gintmsk_s
 230          * @wkupintmsk: Resume/Remote Wakeup Detected Interrupt Mask
 231          *      (WkUpIntMsk)
 232          * @sessreqintmsk: Session Request/New Session Detected Interrupt Mask
 233          *      (SessReqIntMsk)
 234          * @disconnintmsk: Disconnect Detected Interrupt Mask (DisconnIntMsk)
 235          * @conidstschngmsk: Connector ID Status Change Mask (ConIDStsChngMsk)
 236          * @ptxfempmsk: Periodic TxFIFO Empty Mask (PTxFEmpMsk)
 237          * @hchintmsk: Host Channels Interrupt Mask (HChIntMsk)
 238          * @prtintmsk: Host Port Interrupt Mask (PrtIntMsk)
 239          * @fetsuspmsk: Data Fetch Suspended Mask (FetSuspMsk)
 240          * @incomplpmsk: Incomplete Periodic Transfer Mask (incomplPMsk)
 241          *      Incomplete Isochronous OUT Transfer Mask
 242          *      (incompISOOUTMsk)
 243          * @incompisoinmsk: Incomplete Isochronous IN Transfer Mask
 244          *                  (incompISOINMsk)
 245          * @oepintmsk: OUT Endpoints Interrupt Mask (OEPIntMsk)
 246          * @inepintmsk: IN Endpoints Interrupt Mask (INEPIntMsk)
 247          * @epmismsk: Endpoint Mismatch Interrupt Mask (EPMisMsk)
 248          * @eopfmsk: End of Periodic Frame Interrupt Mask (EOPFMsk)
 249          * @isooutdropmsk: Isochronous OUT Packet Dropped Interrupt Mask
 250          *      (ISOOutDropMsk)
 251          * @enumdonemsk: Enumeration Done Mask (EnumDoneMsk)
 252          * @usbrstmsk: USB Reset Mask (USBRstMsk)
 253          * @usbsuspmsk: USB Suspend Mask (USBSuspMsk)
 254          * @erlysuspmsk: Early Suspend Mask (ErlySuspMsk)
 255          * @i2cint: I2C Interrupt Mask (I2CINT)
 256          * @ulpickintmsk: ULPI Carkit Interrupt Mask (ULPICKINTMsk)
 257          *      I2C Carkit Interrupt Mask (I2CCKINTMsk)
 258          * @goutnakeffmsk: Global OUT NAK Effective Mask (GOUTNakEffMsk)
 259          * @ginnakeffmsk: Global Non-Periodic IN NAK Effective Mask
 260          *                (GINNakEffMsk)
 261          * @nptxfempmsk: Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk)
 262          * @rxflvlmsk: Receive FIFO Non-Empty Mask (RxFLvlMsk)
 263          * @sofmsk: Start of (micro)Frame Mask (SofMsk)
 264          * @otgintmsk: OTG Interrupt Mask (OTGIntMsk)
 265          * @modemismsk: Mode Mismatch Interrupt Mask (ModeMisMsk)
 266          */
 267         struct cvmx_usbcx_gintmsk_s {
 268                 uint32_t wkupintmsk             : 1;
 269                 uint32_t sessreqintmsk          : 1;
 270                 uint32_t disconnintmsk          : 1;
 271                 uint32_t conidstschngmsk        : 1;
 272                 uint32_t reserved_27_27         : 1;
 273                 uint32_t ptxfempmsk             : 1;
 274                 uint32_t hchintmsk              : 1;
 275                 uint32_t prtintmsk              : 1;
 276                 uint32_t reserved_23_23         : 1;
 277                 uint32_t fetsuspmsk             : 1;
 278                 uint32_t incomplpmsk            : 1;
 279                 uint32_t incompisoinmsk         : 1;
 280                 uint32_t oepintmsk              : 1;
 281                 uint32_t inepintmsk             : 1;
 282                 uint32_t epmismsk               : 1;
 283                 uint32_t reserved_16_16         : 1;
 284                 uint32_t eopfmsk                : 1;
 285                 uint32_t isooutdropmsk          : 1;
 286                 uint32_t enumdonemsk            : 1;
 287                 uint32_t usbrstmsk              : 1;
 288                 uint32_t usbsuspmsk             : 1;
 289                 uint32_t erlysuspmsk            : 1;
 290                 uint32_t i2cint                 : 1;
 291                 uint32_t ulpickintmsk           : 1;
 292                 uint32_t goutnakeffmsk          : 1;
 293                 uint32_t ginnakeffmsk           : 1;
 294                 uint32_t nptxfempmsk            : 1;
 295                 uint32_t rxflvlmsk              : 1;
 296                 uint32_t sofmsk                 : 1;
 297                 uint32_t otgintmsk              : 1;
 298                 uint32_t modemismsk             : 1;
 299                 uint32_t reserved_0_0           : 1;
 300         } s;
 301 };
 302 typedef union cvmx_usbcx_gintmsk cvmx_usbcx_gintmsk_t;
 303
 304 /**
 305  * cvmx_usbc#_gintsts
 306  *
 307  * Core Interrupt Register (GINTSTS)
 308  *
 309  * This register interrupts the application for system-level events in the
 310  * current mode of operation (Device mode or Host mode). It is shown in
 311  * Interrupt. Some of the bits in this register are valid only in Host mode,
 312  * while others are valid in Device mode only. This register also indicates the
 313  * current mode of operation. In order to clear the interrupt status bits of
 314  * type R_SS_WC, the application must write 1'b1 into the bit. The FIFO status
 315  * interrupts are read only; once software reads from or writes to the FIFO
 316  * while servicing these interrupts, FIFO interrupt conditions are cleared
 317  * automatically.
 318  */
 319 union cvmx_usbcx_gintsts {
 320         uint32_t u32;
 321         /**
 322          * struct cvmx_usbcx_gintsts_s
 323          * @wkupint: Resume/Remote Wakeup Detected Interrupt (WkUpInt)
 324          *      In Device mode, this interrupt is asserted when a resume is
 325          *      detected on the USB. In Host mode, this interrupt is asserted
 326          *      when a remote wakeup is detected on the USB.
 327          *      For more information on how to use this interrupt, see "Partial
 328          *      Power-Down and Clock Gating Programming Model" on
 329          *      page 353.
 330          * @sessreqint: Session Request/New Session Detected Interrupt
 331          *              (SessReqInt)
 332          *      In Host mode, this interrupt is asserted when a session request
 333          *      is detected from the device. In Device mode, this interrupt is
 334          *      asserted when the utmiotg_bvalid signal goes high.
 335          *      For more information on how to use this interrupt, see "Partial
 336          *      Power-Down and Clock Gating Programming Model" on
 337          *      page 353.
 338          * @disconnint: Disconnect Detected Interrupt (DisconnInt)
 339          *      Asserted when a device disconnect is detected.
 340          * @conidstschng: Connector ID Status Change (ConIDStsChng)
 341          *      The core sets this bit when there is a change in connector ID
 342          *      status.
 343          * @ptxfemp: Periodic TxFIFO Empty (PTxFEmp)
 344          *      Asserted when the Periodic Transmit FIFO is either half or
 345          *      completely empty and there is space for at least one entry to be
 346          *      written in the Periodic Request Queue. The half or completely
 347          *      empty status is determined by the Periodic TxFIFO Empty Level
 348          *      bit in the Core AHB Configuration register
 349          *      (GAHBCFG.PTxFEmpLvl).
 350          * @hchint: Host Channels Interrupt (HChInt)
 351          *      The core sets this bit to indicate that an interrupt is pending
 352          *      on one of the channels of the core (in Host mode). The
 353          *      application must read the Host All Channels Interrupt (HAINT)
 354          *      register to determine the exact number of the channel on which
 355          *      the interrupt occurred, and then read the corresponding Host
 356          *      Channel-n Interrupt (HCINTn) register to determine the exact
 357          *      cause of the interrupt. The application must clear the
 358          *      appropriate status bit in the HCINTn register to clear this bit.
 359          * @prtint: Host Port Interrupt (PrtInt)
 360          *      The core sets this bit to indicate a change in port status of
 361          *      one of the O2P USB core ports in Host mode. The application must
 362          *      read the Host Port Control and Status (HPRT) register to
 363          *      determine the exact event that caused this interrupt. The
 364          *      application must clear the appropriate status bit in the Host
 365          *      Port Control and Status register to clear this bit.
 366          * @fetsusp: Data Fetch Suspended (FetSusp)
 367          *      This interrupt is valid only in DMA mode. This interrupt
 368          *      indicates that the core has stopped fetching data for IN
 369          *      endpoints due to the unavailability of TxFIFO space or Request
 370          *      Queue space. This interrupt is used by the application for an
 371          *      endpoint mismatch algorithm.
 372          * @incomplp: Incomplete Periodic Transfer (incomplP)
 373          *      In Host mode, the core sets this interrupt bit when there are
 374          *      incomplete periodic transactions still pending which are
 375          *      scheduled for the current microframe.
 376          *      Incomplete Isochronous OUT Transfer (incompISOOUT)
 377          *      The Device mode, the core sets this interrupt to indicate that
 378          *      there is at least one isochronous OUT endpoint on which the
 379          *      transfer is not completed in the current microframe. This
 380          *      interrupt is asserted along with the End of Periodic Frame
 381          *      Interrupt (EOPF) bit in this register.
 382          * @incompisoin: Incomplete Isochronous IN Transfer (incompISOIN)
 383          *      The core sets this interrupt to indicate that there is at least
 384          *      one isochronous IN endpoint on which the transfer is not
 385          *      completed in the current microframe. This interrupt is asserted
 386          *      along with the End of Periodic Frame Interrupt (EOPF) bit in
 387          *      this register.
 388          * @oepint: OUT Endpoints Interrupt (OEPInt)
 389          *      The core sets this bit to indicate that an interrupt is pending
 390          *      on one of the OUT endpoints of the core (in Device mode). The
 391          *      application must read the Device All Endpoints Interrupt
 392          *      (DAINT) register to determine the exact number of the OUT
 393          *      endpoint on which the interrupt occurred, and then read the
 394          *      corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
 395          *      register to determine the exact cause of the interrupt. The
 396          *      application must clear the appropriate status bit in the
 397          *      corresponding DOEPINTn register to clear this bit.
 398          * @iepint: IN Endpoints Interrupt (IEPInt)
 399          *      The core sets this bit to indicate that an interrupt is pending
 400          *      on one of the IN endpoints of the core (in Device mode). The
 401          *      application must read the Device All Endpoints Interrupt
 402          *      (DAINT) register to determine the exact number of the IN
 403          *      endpoint on which the interrupt occurred, and then read the
 404          *      corresponding Device IN Endpoint-n Interrupt (DIEPINTn)
 405          *      register to determine the exact cause of the interrupt. The
 406          *      application must clear the appropriate status bit in the
 407          *      corresponding DIEPINTn register to clear this bit.
 408          * @epmis: Endpoint Mismatch Interrupt (EPMis)
 409          *      Indicates that an IN token has been received for a non-periodic
 410          *      endpoint, but the data for another endpoint is present in the
 411          *      top of the Non-Periodic Transmit FIFO and the IN endpoint
 412          *      mismatch count programmed by the application has expired.
 413          * @eopf: End of Periodic Frame Interrupt (EOPF)
 414          *      Indicates that the period specified in the Periodic Frame
 415          *      Interval field of the Device Configuration register
 416          *      (DCFG.PerFrInt) has been reached in the current microframe.
 417          * @isooutdrop: Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
 418          *      The core sets this bit when it fails to write an isochronous OUT
 419          *      packet into the RxFIFO because the RxFIFO doesn't have
 420          *      enough space to accommodate a maximum packet size packet
 421          *      for the isochronous OUT endpoint.
 422          * @enumdone: Enumeration Done (EnumDone)
 423          *      The core sets this bit to indicate that speed enumeration is
 424          *      complete. The application must read the Device Status (DSTS)
 425          *      register to obtain the enumerated speed.
 426          * @usbrst: USB Reset (USBRst)
 427          *      The core sets this bit to indicate that a reset is detected on
 428          *      the USB.
 429          * @usbsusp: USB Suspend (USBSusp)
 430          *      The core sets this bit to indicate that a suspend was detected
 431          *      on the USB. The core enters the Suspended state when there
 432          *      is no activity on the phy_line_state_i signal for an extended
 433          *      period of time.
 434          * @erlysusp: Early Suspend (ErlySusp)
 435          *      The core sets this bit to indicate that an Idle state has been
 436          *      detected on the USB for 3 ms.
 437          * @i2cint: I2C Interrupt (I2CINT)
 438          *      This bit is always 0x0.
 439          * @ulpickint: ULPI Carkit Interrupt (ULPICKINT)
 440          *      This bit is always 0x0.
 441          * @goutnakeff: Global OUT NAK Effective (GOUTNakEff)
 442          *      Indicates that the Set Global OUT NAK bit in the Device Control
 443          *      register (DCTL.SGOUTNak), set by the application, has taken
 444          *      effect in the core. This bit can be cleared by writing the Clear
 445          *      Global OUT NAK bit in the Device Control register
 446          *      (DCTL.CGOUTNak).
 447          * @ginnakeff: Global IN Non-Periodic NAK Effective (GINNakEff)
 448          *      Indicates that the Set Global Non-Periodic IN NAK bit in the
 449          *      Device Control register (DCTL.SGNPInNak), set by the
 450          *      application, has taken effect in the core. That is, the core has
 451          *      sampled the Global IN NAK bit set by the application. This bit
 452          *      can be cleared by clearing the Clear Global Non-Periodic IN
 453          *      NAK bit in the Device Control register (DCTL.CGNPInNak).
 454          *      This interrupt does not necessarily mean that a NAK handshake
 455          *      is sent out on the USB. The STALL bit takes precedence over
 456          *      the NAK bit.
 457          * @nptxfemp: Non-Periodic TxFIFO Empty (NPTxFEmp)
 458          *      This interrupt is asserted when the Non-Periodic TxFIFO is
 459          *      either half or completely empty, and there is space for at least
 460          *      one entry to be written to the Non-Periodic Transmit Request
 461          *      Queue. The half or completely empty status is determined by
 462          *      the Non-Periodic TxFIFO Empty Level bit in the Core AHB
 463          *      Configuration register (GAHBCFG.NPTxFEmpLvl).
 464          * @rxflvl: RxFIFO Non-Empty (RxFLvl)
 465          *      Indicates that there is at least one packet pending to be read
 466          *      from the RxFIFO.
 467          * @sof: Start of (micro)Frame (Sof)
 468          *      In Host mode, the core sets this bit to indicate that an SOF
 469          *      (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the
 470          *      USB. The application must write a 1 to this bit to clear the
 471          *      interrupt.
 472          *      In Device mode, in the core sets this bit to indicate that an
 473          *      SOF token has been received on the USB. The application can read
 474          *      the Device Status register to get the current (micro)frame
 475          *      number. This interrupt is seen only when the core is operating
 476          *      at either HS or FS.
 477          * @otgint: OTG Interrupt (OTGInt)
 478          *      The core sets this bit to indicate an OTG protocol event. The
 479          *      application must read the OTG Interrupt Status (GOTGINT)
 480          *      register to determine the exact event that caused this
 481          *      interrupt. The application must clear the appropriate status bit
 482          *      in the GOTGINT register to clear this bit.
 483          * @modemis: Mode Mismatch Interrupt (ModeMis)
 484          *      The core sets this bit when the application is trying to access:
 485          *      * A Host mode register, when the core is operating in Device
 486          *      mode
 487          *      * A Device mode register, when the core is operating in Host
 488          *      mode
 489          *      The register access is completed on the AHB with an OKAY
 490          *      response, but is ignored by the core internally and doesn't
 491          *      affect the operation of the core.
 492          * @curmod: Current Mode of Operation (CurMod)
 493          *      Indicates the current mode of operation.
 494          *      * 1'b0: Device mode
 495          *      * 1'b1: Host mode
 496          */
 497         struct cvmx_usbcx_gintsts_s {
 498                 uint32_t wkupint        : 1;
 499                 uint32_t sessreqint     : 1;
 500                 uint32_t disconnint     : 1;
 501                 uint32_t conidstschng   : 1;
 502                 uint32_t reserved_27_27 : 1;
 503                 uint32_t ptxfemp        : 1;
 504                 uint32_t hchint         : 1;
 505                 uint32_t prtint         : 1;
 506                 uint32_t reserved_23_23 : 1;
 507                 uint32_t fetsusp        : 1;
 508                 uint32_t incomplp       : 1;
 509                 uint32_t incompisoin    : 1;
 510                 uint32_t oepint         : 1;
 511                 uint32_t iepint         : 1;
 512                 uint32_t epmis          : 1;
 513                 uint32_t reserved_16_16 : 1;
 514                 uint32_t eopf           : 1;
 515                 uint32_t isooutdrop     : 1;
 516                 uint32_t enumdone       : 1;
 517                 uint32_t usbrst         : 1;
 518                 uint32_t usbsusp        : 1;
 519                 uint32_t erlysusp       : 1;
 520                 uint32_t i2cint         : 1;
 521                 uint32_t ulpickint      : 1;
 522                 uint32_t goutnakeff     : 1;
 523                 uint32_t ginnakeff      : 1;
 524                 uint32_t nptxfemp       : 1;
 525                 uint32_t rxflvl         : 1;
 526                 uint32_t sof            : 1;
 527                 uint32_t otgint         : 1;
 528                 uint32_t modemis        : 1;
 529                 uint32_t curmod         : 1;
 530         } s;
 531 };
 532 typedef union cvmx_usbcx_gintsts cvmx_usbcx_gintsts_t;
 533
 534 /**
 535  * cvmx_usbc#_gnptxfsiz
 536  *
 537  * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ)
 538  *
 539  * The application can program the RAM size and the memory start address for the
 540  * Non-Periodic TxFIFO.
 541  */
 542 union cvmx_usbcx_gnptxfsiz {
 543         uint32_t u32;
 544         /**
 545          * struct cvmx_usbcx_gnptxfsiz_s
 546          * @nptxfdep: Non-Periodic TxFIFO Depth (NPTxFDep)
 547          *      This value is in terms of 32-bit words.
 548          *      Minimum value is 16
 549          *      Maximum value is 32768
 550          * @nptxfstaddr: Non-Periodic Transmit RAM Start Address (NPTxFStAddr)
 551          *      This field contains the memory start address for Non-Periodic
 552          *      Transmit FIFO RAM.
 553          */
 554         struct cvmx_usbcx_gnptxfsiz_s {
 555                 uint32_t nptxfdep       : 16;
 556                 uint32_t nptxfstaddr    : 16;
 557         } s;
 558 };
 559 typedef union cvmx_usbcx_gnptxfsiz cvmx_usbcx_gnptxfsiz_t;
 560
 561 /**
 562  * cvmx_usbc#_gnptxsts
 563  *
 564  * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
 565  *
 566  * This read-only register contains the free space information for the
 567  * Non-Periodic TxFIFO and the Non-Periodic Transmit Request Queue.
 568  */
 569 union cvmx_usbcx_gnptxsts {
 570         uint32_t u32;
 571         /**
 572          * struct cvmx_usbcx_gnptxsts_s
 573          * @nptxqtop: Top of the Non-Periodic Transmit Request Queue (NPTxQTop)
 574          *      Entry in the Non-Periodic Tx Request Queue that is currently
 575          *      being processed by the MAC.
 576          *      * Bits [30:27]: Channel/endpoint number
 577          *      * Bits [26:25]:
 578          *      - 2'b00: IN/OUT token
 579          *      - 2'b01: Zero-length transmit packet (device IN/host OUT)
 580          *      - 2'b10: PING/CSPLIT token
 581          *      - 2'b11: Channel halt command
 582          *      * Bit [24]: Terminate (last entry for selected channel/endpoint)
 583          * @nptxqspcavail: Non-Periodic Transmit Request Queue Space Available
 584          *      (NPTxQSpcAvail)
 585          *      Indicates the amount of free space available in the Non-
 586          *      Periodic Transmit Request Queue. This queue holds both IN
 587          *      and OUT requests in Host mode. Device mode has only IN
 588          *      requests.
 589          *      * 8'h0: Non-Periodic Transmit Request Queue is full
 590          *      * 8'h1: 1 location available
 591          *      * 8'h2: 2 locations available
 592          *      * n: n locations available (0..8)
 593          *      * Others: Reserved
 594          * @nptxfspcavail: Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail)
 595          *      Indicates the amount of free space available in the Non-
 596          *      Periodic TxFIFO.
 597          *      Values are in terms of 32-bit words.
 598          *      * 16'h0: Non-Periodic TxFIFO is full
 599          *      * 16'h1: 1 word available
 600          *      * 16'h2: 2 words available
 601          *      * 16'hn: n words available (where 0..32768)
 602          *      * 16'h8000: 32768 words available
 603          *      * Others: Reserved
 604          */
 605         struct cvmx_usbcx_gnptxsts_s {
 606                 uint32_t reserved_31_31 : 1;
 607                 uint32_t nptxqtop       : 7;
 608                 uint32_t nptxqspcavail  : 8;
 609                 uint32_t nptxfspcavail  : 16;
 610         } s;
 611 };
 612 typedef union cvmx_usbcx_gnptxsts cvmx_usbcx_gnptxsts_t;
 613
 614 /**
 615  * cvmx_usbc#_grstctl
 616  *
 617  * Core Reset Register (GRSTCTL)
 618  *
 619  * The application uses this register to reset various hardware features inside
 620  * the core.
 621  */
 622 union cvmx_usbcx_grstctl {
 623         uint32_t u32;
 624         /**
 625          * struct cvmx_usbcx_grstctl_s
 626          * @ahbidle: AHB Master Idle (AHBIdle)
 627          *      Indicates that the AHB Master State Machine is in the IDLE
 628          *      condition.
 629          * @dmareq: DMA Request Signal (DMAReq)
 630          *      Indicates that the DMA request is in progress. Used for debug.
 631          * @txfnum: TxFIFO Number (TxFNum)
 632          *      This is the FIFO number that must be flushed using the TxFIFO
 633          *      Flush bit. This field must not be changed until the core clears
 634          *      the TxFIFO Flush bit.
 635          *      * 5'h0: Non-Periodic TxFIFO flush
 636          *      * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic
 637          *      TxFIFO flush in Host mode
 638          *      * 5'h2: Periodic TxFIFO 2 flush in Device mode
 639          *      - ...
 640          *      * 5'hF: Periodic TxFIFO 15 flush in Device mode
 641          *      * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the
 642          *      core
 643          * @txfflsh: TxFIFO Flush (TxFFlsh)
 644          *      This bit selectively flushes a single or all transmit FIFOs, but
 645          *      cannot do so if the core is in the midst of a transaction.
 646          *      The application must only write this bit after checking that the
 647          *      core is neither writing to the TxFIFO nor reading from the
 648          *      TxFIFO.
 649          *      The application must wait until the core clears this bit before
 650          *      performing any operations. This bit takes 8 clocks (of phy_clk
 651          *      or hclk, whichever is slower) to clear.
 652          * @rxfflsh: RxFIFO Flush (RxFFlsh)
 653          *      The application can flush the entire RxFIFO using this bit, but
 654          *      must first ensure that the core is not in the middle of a
 655          *      transaction.
 656          *      The application must only write to this bit after checking that
 657          *      the core is neither reading from the RxFIFO nor writing to the
 658          *      RxFIFO.
 659          *      The application must wait until the bit is cleared before
 660          *      performing any other operations. This bit will take 8 clocks
 661          *      (slowest of PHY or AHB clock) to clear.
 662          * @intknqflsh: IN Token Sequence Learning Queue Flush (INTknQFlsh)
 663          *      The application writes this bit to flush the IN Token Sequence
 664          *      Learning Queue.
 665          * @frmcntrrst: Host Frame Counter Reset (FrmCntrRst)
 666          *      The application writes this bit to reset the (micro)frame number
 667          *      counter inside the core. When the (micro)frame counter is reset,
 668          *      the subsequent SOF sent out by the core will have a
 669          *      (micro)frame number of 0.
 670          * @hsftrst: HClk Soft Reset (HSftRst)
 671          *      The application uses this bit to flush the control logic in the
 672          *      AHB Clock domain. Only AHB Clock Domain pipelines are reset.
 673          *      * FIFOs are not flushed with this bit.
 674          *      * All state machines in the AHB clock domain are reset to the
 675          *      Idle state after terminating the transactions on the AHB,
 676          *      following the protocol.
 677          *      * CSR control bits used by the AHB clock domain state
 678          *      machines are cleared.
 679          *      * To clear this interrupt, status mask bits that control the
 680          *      interrupt status and are generated by the AHB clock domain
 681          *      state machine are cleared.
 682          *      * Because interrupt status bits are not cleared, the application
 683          *      can get the status of any core events that occurred after it set
 684          *      this bit.
 685          *      This is a self-clearing bit that the core clears after all
 686          *      necessary logic is reset in the core. This may take several
 687          *      clocks, depending on the core's current state.
 688          * @csftrst: Core Soft Reset (CSftRst)
 689          *      Resets the hclk and phy_clock domains as follows:
 690          *      * Clears the interrupts and all the CSR registers except the
 691          *      following register bits:
 692          *      - PCGCCTL.RstPdwnModule
 693          *      - PCGCCTL.GateHclk
 694          *      - PCGCCTL.PwrClmp
 695          *      - PCGCCTL.StopPPhyLPwrClkSelclk
 696          *      - GUSBCFG.PhyLPwrClkSel
 697          *      - GUSBCFG.DDRSel
 698          *      - GUSBCFG.PHYSel
 699          *      - GUSBCFG.FSIntf
 700          *      - GUSBCFG.ULPI_UTMI_Sel
 701          *      - GUSBCFG.PHYIf
 702          *      - HCFG.FSLSPclkSel
 703          *      - DCFG.DevSpd
 704          *      * All module state machines (except the AHB Slave Unit) are
 705          *      reset to the IDLE state, and all the transmit FIFOs and the
 706          *      receive FIFO are flushed.
 707          *      * Any transactions on the AHB Master are terminated as soon
 708          *      as possible, after gracefully completing the last data phase of
 709          *      an AHB transfer. Any transactions on the USB are terminated
 710          *      immediately.
 711          *      The application can write to this bit any time it wants to reset
 712          *      the core. This is a self-clearing bit and the core clears this
 713          *      bit after all the necessary logic is reset in the core, which
 714          *      may take several clocks, depending on the current state of the
 715          *      core. Once this bit is cleared software should wait at least 3
 716          *      PHY clocks before doing any access to the PHY domain
 717          *      (synchronization delay). Software should also should check that
 718          *      bit 31 of this register is 1 (AHB Master is IDLE) before
 719          *      starting any operation.
 720          *      Typically software reset is used during software development
 721          *      and also when you dynamically change the PHY selection bits
 722          *      in the USB configuration registers listed above. When you
 723          *      change the PHY, the corresponding clock for the PHY is
 724          *      selected and used in the PHY domain. Once a new clock is
 725          *      selected, the PHY domain has to be reset for proper operation.
 726          */
 727         struct cvmx_usbcx_grstctl_s {
 728                 uint32_t ahbidle        : 1;
 729                 uint32_t dmareq         : 1;
 730                 uint32_t reserved_11_29 : 19;
 731                 uint32_t txfnum         : 5;
 732                 uint32_t txfflsh        : 1;
 733                 uint32_t rxfflsh        : 1;
 734                 uint32_t intknqflsh     : 1;
 735                 uint32_t frmcntrrst     : 1;
 736                 uint32_t hsftrst        : 1;
 737                 uint32_t csftrst        : 1;
 738         } s;
 739 };
 740 typedef union cvmx_usbcx_grstctl cvmx_usbcx_grstctl_t;
 741
 742 /**
 743  * cvmx_usbc#_grxfsiz
 744  *
 745  * Receive FIFO Size Register (GRXFSIZ)
 746  *
 747  * The application can program the RAM size that must be allocated to the
 748  * RxFIFO.
 749  */
 750 union cvmx_usbcx_grxfsiz {
 751         uint32_t u32;
 752         /**
 753          * struct cvmx_usbcx_grxfsiz_s
 754          * @rxfdep: RxFIFO Depth (RxFDep)
 755          *      This value is in terms of 32-bit words.
 756          *      * Minimum value is 16
 757          *      * Maximum value is 32768
 758          */
 759         struct cvmx_usbcx_grxfsiz_s {
 760                 uint32_t reserved_16_31 : 16;
 761                 uint32_t rxfdep         : 16;
 762         } s;
 763 };
 764 typedef union cvmx_usbcx_grxfsiz cvmx_usbcx_grxfsiz_t;
 765
 766 /**
 767  * cvmx_usbc#_grxstsph
 768  *
 769  * Receive Status Read and Pop Register, Host Mode (GRXSTSPH)
 770  *
 771  * A read to the Receive Status Read and Pop register returns and additionally
 772  * pops the top data entry out of the RxFIFO.
 773  * This Description is only valid when the core is in Host Mode. For Device Mode
 774  * use USBC_GRXSTSPD instead.
 775  * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the
 776  *       same offset in the O2P USB core. The offset difference shown in this
 777  *       document is for software clarity and is actually ignored by the
 778  *       hardware.
 779  */
 780 union cvmx_usbcx_grxstsph {
 781         uint32_t u32;
 782         /**
 783          * struct cvmx_usbcx_grxstsph_s
 784          * @pktsts: Packet Status (PktSts)
 785          *      Indicates the status of the received packet
 786          *      * 4'b0010: IN data packet received
 787          *      * 4'b0011: IN transfer completed (triggers an interrupt)
 788          *      * 4'b0101: Data toggle error (triggers an interrupt)
 789          *      * 4'b0111: Channel halted (triggers an interrupt)
 790          *      * Others: Reserved
 791          * @dpid: Data PID (DPID)
 792          *      * 2'b00: DATA0
 793          *      * 2'b10: DATA1
 794          *      * 2'b01: DATA2
 795          *      * 2'b11: MDATA
 796          * @bcnt: Byte Count (BCnt)
 797          *      Indicates the byte count of the received IN data packet
 798          * @chnum: Channel Number (ChNum)
 799          *      Indicates the channel number to which the current received
 800          *      packet belongs.
 801          */
 802         struct cvmx_usbcx_grxstsph_s {
 803                 uint32_t reserved_21_31 : 11;
 804                 uint32_t pktsts         : 4;
 805                 uint32_t dpid           : 2;
 806                 uint32_t bcnt           : 11;
 807                 uint32_t chnum          : 4;
 808         } s;
 809 };
 810 typedef union cvmx_usbcx_grxstsph cvmx_usbcx_grxstsph_t;
 811
 812 /**
 813  * cvmx_usbc#_gusbcfg
 814  *
 815  * Core USB Configuration Register (GUSBCFG)
 816  *
 817  * This register can be used to configure the core after power-on or a changing
 818  * to Host mode or Device mode. It contains USB and USB-PHY related
 819  * configuration parameters. The application must program this register before
 820  * starting any transactions on either the AHB or the USB. Do not make changes
 821  * to this register after the initial programming.
 822  */
 823 union cvmx_usbcx_gusbcfg {
 824         uint32_t u32;
 825         /**
 826          * struct cvmx_usbcx_gusbcfg_s
 827          * @otgi2csel: UTMIFS or I2C Interface Select (OtgI2CSel)
 828          *      This bit is always 0x0.
 829          * @phylpwrclksel: PHY Low-Power Clock Select (PhyLPwrClkSel)
 830          *      Software should set this bit to 0x0.
 831          *      Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
 832          *      FS and LS modes, the PHY can usually operate on a 48-MHz
 833          *      clock to save power.
 834          *      * 1'b0: 480-MHz Internal PLL clock
 835          *      * 1'b1: 48-MHz External Clock
 836          *      In 480 MHz mode, the UTMI interface operates at either 60 or
 837          *      30-MHz, depending upon whether 8- or 16-bit data width is
 838          *      selected. In 48-MHz mode, the UTMI interface operates at 48
 839          *      MHz in FS mode and at either 48 or 6 MHz in LS mode
 840          *      (depending on the PHY vendor).
 841          *      This bit drives the utmi_fsls_low_power core output signal, and
 842          *      is valid only for UTMI+ PHYs.
 843          * @usbtrdtim: USB Turnaround Time (USBTrdTim)
 844          *      Sets the turnaround time in PHY clocks.
 845          *      Specifies the response time for a MAC request to the Packet
 846          *      FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM).
 847          *      This must be programmed to 0x5.
 848          * @hnpcap: HNP-Capable (HNPCap)
 849          *      This bit is always 0x0.
 850          * @srpcap: SRP-Capable (SRPCap)
 851          *      This bit is always 0x0.
 852          * @ddrsel: ULPI DDR Select (DDRSel)
 853          *      Software should set this bit to 0x0.
 854          * @physel: USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
 855          *      Software should set this bit to 0x0.
 856          * @fsintf: Full-Speed Serial Interface Select (FSIntf)
 857          *      Software should set this bit to 0x0.
 858          * @ulpi_utmi_sel: ULPI or UTMI+ Select (ULPI_UTMI_Sel)
 859          *      This bit is always 0x0.
 860          * @phyif: PHY Interface (PHYIf)
 861          *      This bit is always 0x1.
 862          * @toutcal: HS/FS Timeout Calibration (TOutCal)
 863          *      The number of PHY clocks that the application programs in this
 864          *      field is added to the high-speed/full-speed interpacket timeout
 865          *      duration in the core to account for any additional delays
 866          *      introduced by the PHY. This may be required, since the delay
 867          *      introduced by the PHY in generating the linestate condition may
 868          *      vary from one PHY to another.
 869          *      The USB standard timeout value for high-speed operation is
 870          *      736 to 816 (inclusive) bit times. The USB standard timeout
 871          *      value for full-speed operation is 16 to 18 (inclusive) bit
 872          *      times. The application must program this field based on the
 873          *      speed of enumeration. The number of bit times added per PHY
 874          *      clock are:
 875          *      High-speed operation:
 876          *      * One 30-MHz PHY clock = 16 bit times
 877          *      * One 60-MHz PHY clock = 8 bit times
 878          *      Full-speed operation:
 879          *      * One 30-MHz PHY clock = 0.4 bit times
 880          *      * One 60-MHz PHY clock = 0.2 bit times
 881          *      * One 48-MHz PHY clock = 0.25 bit times
 882          */
 883         struct cvmx_usbcx_gusbcfg_s {
 884                 uint32_t reserved_17_31 : 15;
 885                 uint32_t otgi2csel      : 1;
 886                 uint32_t phylpwrclksel  : 1;
 887                 uint32_t reserved_14_14 : 1;
 888                 uint32_t usbtrdtim      : 4;
 889                 uint32_t hnpcap         : 1;
 890                 uint32_t srpcap         : 1;
 891                 uint32_t ddrsel         : 1;
 892                 uint32_t physel         : 1;
 893                 uint32_t fsintf         : 1;
 894                 uint32_t ulpi_utmi_sel  : 1;
 895                 uint32_t phyif          : 1;
 896                 uint32_t toutcal        : 3;
 897         } s;
 898 };
 899 typedef union cvmx_usbcx_gusbcfg cvmx_usbcx_gusbcfg_t;
 900
 901 /**
 902  * cvmx_usbc#_haint
 903  *
 904  * Host All Channels Interrupt Register (HAINT)
 905  *
 906  * When a significant event occurs on a channel, the Host All Channels Interrupt
 907  * register interrupts the application using the Host Channels Interrupt bit of
 908  * the Core Interrupt register (GINTSTS.HChInt). This is shown in Interrupt.
 909  * There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in
 910  * this register are set and cleared when the application sets and clears bits
 911  * in the corresponding Host Channel-n Interrupt register.
 912  */
 913 union cvmx_usbcx_haint {
 914         uint32_t u32;
 915         /**
 916          * struct cvmx_usbcx_haint_s
 917          * @haint: Channel Interrupts (HAINT)
 918          *      One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15
 919          */
 920         struct cvmx_usbcx_haint_s {
 921                 uint32_t reserved_16_31 : 16;
 922                 uint32_t haint          : 16;
 923         } s;
 924 };
 925 typedef union cvmx_usbcx_haint cvmx_usbcx_haint_t;
 926
 927 /**
 928  * cvmx_usbc#_haintmsk
 929  *
 930  * Host All Channels Interrupt Mask Register (HAINTMSK)
 931  *
 932  * The Host All Channel Interrupt Mask register works with the Host All Channel
 933  * Interrupt register to interrupt the application when an event occurs on a
 934  * channel. There is one interrupt mask bit per channel, up to a maximum of 16
 935  * bits.
 936  * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
 937  */
 938 union cvmx_usbcx_haintmsk {
 939         uint32_t u32;
 940         /**
 941          * struct cvmx_usbcx_haintmsk_s
 942          * @haintmsk: Channel Interrupt Mask (HAINTMsk)
 943          *      One bit per channel: Bit 0 for channel 0, bit 15 for channel 15
 944          */
 945         struct cvmx_usbcx_haintmsk_s {
 946                 uint32_t reserved_16_31 : 16;
 947                 uint32_t haintmsk       : 16;
 948         } s;
 949 };
 950 typedef union cvmx_usbcx_haintmsk cvmx_usbcx_haintmsk_t;
 951
 952 /**
 953  * cvmx_usbc#_hcchar#
 954  *
 955  * Host Channel-n Characteristics Register (HCCHAR)
 956  *
 957  */
 958 union cvmx_usbcx_hccharx {
 959         uint32_t u32;
 960         /**
 961          * struct cvmx_usbcx_hccharx_s
 962          * @chena: Channel Enable (ChEna)
 963          *      This field is set by the application and cleared by the OTG
 964          *      host.
 965          *      * 1'b0: Channel disabled
 966          *      * 1'b1: Channel enabled
 967          * @chdis: Channel Disable (ChDis)
 968          *      The application sets this bit to stop transmitting/receiving
 969          *      data on a channel, even before the transfer for that channel is
 970          *      complete. The application must wait for the Channel Disabled
 971          *      interrupt before treating the channel as disabled.
 972          * @oddfrm: Odd Frame (OddFrm)
 973          *      This field is set (reset) by the application to indicate that
 974          *      the OTG host must perform a transfer in an odd (micro)frame.
 975          *      This field is applicable for only periodic (isochronous and
 976          *      interrupt) transactions.
 977          *      * 1'b0: Even (micro)frame
 978          *      * 1'b1: Odd (micro)frame
 979          * @devaddr: Device Address (DevAddr)
 980          *      This field selects the specific device serving as the data
 981          *      source or sink.
 982          * @ec: Multi Count (MC) / Error Count (EC)
 983          *      When the Split Enable bit of the Host Channel-n Split Control
 984          *      register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates
 985          *      to the host the number of transactions that should be executed
 986          *      per microframe for this endpoint.
 987          *      * 2'b00: Reserved. This field yields undefined results.
 988          *      * 2'b01: 1 transaction
 989          *      * 2'b10: 2 transactions to be issued for this endpoint per
 990          *      microframe
 991          *      * 2'b11: 3 transactions to be issued for this endpoint per
 992          *      microframe
 993          *      When HCSPLTn.SpltEna is set (1'b1), this field indicates the
 994          *      number of immediate retries to be performed for a periodic split
 995          *      transactions on transaction errors. This field must be set to at
 996          *      least 2'b01.
 997          * @eptype: Endpoint Type (EPType)
 998          *      Indicates the transfer type selected.
 999          *      * 2'b00: Control
1000          *      * 2'b01: Isochronous
1001          *      * 2'b10: Bulk
1002          *      * 2'b11: Interrupt
1003          * @lspddev: Low-Speed Device (LSpdDev)
1004          *      This field is set by the application to indicate that this
1005          *      channel is communicating to a low-speed device.
1006          * @epdir: Endpoint Direction (EPDir)
1007          *      Indicates whether the transaction is IN or OUT.
1008          *      * 1'b0: OUT
1009          *      * 1'b1: IN
1010          * @epnum: Endpoint Number (EPNum)
1011          *      Indicates the endpoint number on the device serving as the
1012          *      data source or sink.
1013          * @mps: Maximum Packet Size (MPS)
1014          *      Indicates the maximum packet size of the associated endpoint.
1015          */
1016         struct cvmx_usbcx_hccharx_s {
1017                 uint32_t chena          : 1;
1018                 uint32_t chdis          : 1;
1019                 uint32_t oddfrm         : 1;
1020                 uint32_t devaddr        : 7;
1021                 uint32_t ec             : 2;
1022                 uint32_t eptype         : 2;
1023                 uint32_t lspddev        : 1;
1024                 uint32_t reserved_16_16 : 1;
1025                 uint32_t epdir          : 1;
1026                 uint32_t epnum          : 4;
1027                 uint32_t mps            : 11;
1028         } s;
1029 };
1030 typedef union cvmx_usbcx_hccharx cvmx_usbcx_hccharx_t;
1031
1032 /**
1033  * cvmx_usbc#_hcfg
1034  *
1035  * Host Configuration Register (HCFG)
1036  *
1037  * This register configures the core after power-on. Do not make changes to this
1038  * register after initializing the host.
1039  */
1040 union cvmx_usbcx_hcfg {
1041         uint32_t u32;
1042         /**
1043          * struct cvmx_usbcx_hcfg_s
1044          * @fslssupp: FS- and LS-Only Support (FSLSSupp)
1045          *      The application uses this bit to control the core's enumeration
1046          *      speed. Using this bit, the application can make the core
1047          *      enumerate as a FS host, even if the connected device supports
1048          *      HS traffic. Do not make changes to this field after initial
1049          *      programming.
1050          *      * 1'b0: HS/FS/LS, based on the maximum speed supported by
1051          *      the connected device
1052          *      * 1'b1: FS/LS-only, even if the connected device can support HS
1053          * @fslspclksel: FS/LS PHY Clock Select (FSLSPclkSel)
1054          *      When the core is in FS Host mode
1055          *      * 2'b00: PHY clock is running at 30/60 MHz
1056          *      * 2'b01: PHY clock is running at 48 MHz
1057          *      * Others: Reserved
1058          *      When the core is in LS Host mode
1059          *      * 2'b00: PHY clock is running at 30/60 MHz. When the
1060          *      UTMI+/ULPI PHY Low Power mode is not selected, use
1061          *      30/60 MHz.
1062          *      * 2'b01: PHY clock is running at 48 MHz. When the UTMI+
1063          *      PHY Low Power mode is selected, use 48MHz if the PHY
1064          *      supplies a 48 MHz clock during LS mode.
1065          *      * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode,
1066          *      use 6 MHz when the UTMI+ PHY Low Power mode is
1067          *      selected and the PHY supplies a 6 MHz clock during LS
1068          *      mode. If you select a 6 MHz clock during LS mode, you must
1069          *      do a soft reset.
1070          *      * 2'b11: Reserved
1071          */
1072         struct cvmx_usbcx_hcfg_s {
1073                 uint32_t reserved_3_31  : 29;
1074                 uint32_t fslssupp       : 1;
1075                 uint32_t fslspclksel    : 2;
1076         } s;
1077 };
1078 typedef union cvmx_usbcx_hcfg cvmx_usbcx_hcfg_t;
1079
1080 /**
1081  * cvmx_usbc#_hcint#
1082  *
1083  * Host Channel-n Interrupt Register (HCINT)
1084  *
1085  * This register indicates the status of a channel with respect to USB- and
1086  * AHB-related events. The application must read this register when the Host
1087  * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is
1088  * set. Before the application can read this register, it must first read
1089  * the Host All Channels Interrupt (HAINT) register to get the exact channel
1090  * number for the Host Channel-n Interrupt register. The application must clear
1091  * the appropriate bit in this register to clear the corresponding bits in the
1092  * HAINT and GINTSTS registers.
1093  */
1094 union cvmx_usbcx_hcintx {
1095         uint32_t u32;
1096         /**
1097          * struct cvmx_usbcx_hcintx_s
1098          * @datatglerr: Data Toggle Error (DataTglErr)
1099          * @frmovrun: Frame Overrun (FrmOvrun)
1100          * @bblerr: Babble Error (BblErr)
1101          * @xacterr: Transaction Error (XactErr)
1102          * @nyet: NYET Response Received Interrupt (NYET)
1103          * @ack: ACK Response Received Interrupt (ACK)
1104          * @nak: NAK Response Received Interrupt (NAK)
1105          * @stall: STALL Response Received Interrupt (STALL)
1106          * @ahberr: This bit is always 0x0.
1107          * @chhltd: Channel Halted (ChHltd)
1108          *      Indicates the transfer completed abnormally either because of
1109          *      any USB transaction error or in response to disable request by
1110          *      the application.
1111          * @xfercompl: Transfer Completed (XferCompl)
1112          *      Transfer completed normally without any errors.
1113          */
1114         struct cvmx_usbcx_hcintx_s {
1115                 uint32_t reserved_11_31 : 21;
1116                 uint32_t datatglerr     : 1;
1117                 uint32_t frmovrun       : 1;
1118                 uint32_t bblerr         : 1;
1119                 uint32_t xacterr        : 1;
1120                 uint32_t nyet           : 1;
1121                 uint32_t ack            : 1;
1122                 uint32_t nak            : 1;
1123                 uint32_t stall          : 1;
1124                 uint32_t ahberr         : 1;
1125                 uint32_t chhltd         : 1;
1126                 uint32_t xfercompl      : 1;
1127         } s;
1128 };
1129 typedef union cvmx_usbcx_hcintx cvmx_usbcx_hcintx_t;
1130
1131 /**
1132  * cvmx_usbc#_hcintmsk#
1133  *
1134  * Host Channel-n Interrupt Mask Register (HCINTMSKn)
1135  *
1136  * This register reflects the mask for each channel status described in the
1137  * previous section.
1138  * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
1139  */
1140 union cvmx_usbcx_hcintmskx {
1141         uint32_t u32;
1142         /**
1143          * struct cvmx_usbcx_hcintmskx_s
1144          * @datatglerrmsk: Data Toggle Error Mask (DataTglErrMsk)
1145          * @frmovrunmsk: Frame Overrun Mask (FrmOvrunMsk)
1146          * @bblerrmsk: Babble Error Mask (BblErrMsk)
1147          * @xacterrmsk: Transaction Error Mask (XactErrMsk)
1148          * @nyetmsk: NYET Response Received Interrupt Mask (NyetMsk)
1149          * @ackmsk: ACK Response Received Interrupt Mask (AckMsk)
1150          * @nakmsk: NAK Response Received Interrupt Mask (NakMsk)
1151          * @stallmsk: STALL Response Received Interrupt Mask (StallMsk)
1152          * @ahberrmsk: AHB Error Mask (AHBErrMsk)
1153          * @chhltdmsk: Channel Halted Mask (ChHltdMsk)
1154          * @xfercomplmsk: Transfer Completed Mask (XferComplMsk)
1155          */
1156         struct cvmx_usbcx_hcintmskx_s {
1157                 uint32_t reserved_11_31 : 21;
1158                 uint32_t datatglerrmsk  : 1;
1159                 uint32_t frmovrunmsk    : 1;
1160                 uint32_t bblerrmsk      : 1;
1161                 uint32_t xacterrmsk     : 1;
1162                 uint32_t nyetmsk        : 1;
1163                 uint32_t ackmsk         : 1;
1164                 uint32_t nakmsk         : 1;
1165                 uint32_t stallmsk       : 1;
1166                 uint32_t ahberrmsk      : 1;
1167                 uint32_t chhltdmsk      : 1;
1168                 uint32_t xfercomplmsk   : 1;
1169         } s;
1170 };
1171 typedef union cvmx_usbcx_hcintmskx cvmx_usbcx_hcintmskx_t;
1172
1173 /**
1174  * cvmx_usbc#_hcsplt#
1175  *
1176  * Host Channel-n Split Control Register (HCSPLT)
1177  *
1178  */
1179 union cvmx_usbcx_hcspltx {
1180         uint32_t u32;
1181         /**
1182          * struct cvmx_usbcx_hcspltx_s
1183          * @spltena: Split Enable (SpltEna)
1184          *      The application sets this field to indicate that this channel is
1185          *      enabled to perform split transactions.
1186          * @compsplt: Do Complete Split (CompSplt)
1187          *      The application sets this field to request the OTG host to
1188          *      perform a complete split transaction.
1189          * @xactpos: Transaction Position (XactPos)
1190          *      This field is used to determine whether to send all, first,
1191          *      middle, or last payloads with each OUT transaction.
1192          *      * 2'b11: All. This is the entire data payload is of this
1193          *      transaction (which is less than or equal to 188 bytes).
1194          *      * 2'b10: Begin. This is the first data payload of this
1195          *      transaction (which is larger than 188 bytes).
1196          *      * 2'b00: Mid. This is the middle payload of this transaction
1197          *      (which is larger than 188 bytes).
1198          *      * 2'b01: End. This is the last payload of this transaction
1199          *      (which is larger than 188 bytes).
1200          * @hubaddr: Hub Address (HubAddr)
1201          *      This field holds the device address of the transaction
1202          *      translator's hub.
1203          * @prtaddr: Port Address (PrtAddr)
1204          *      This field is the port number of the recipient transaction
1205          *      translator.
1206          */
1207         struct cvmx_usbcx_hcspltx_s {
1208                 uint32_t spltena        : 1;
1209                 uint32_t reserved_17_30 : 14;
1210                 uint32_t compsplt       : 1;
1211                 uint32_t xactpos        : 2;
1212                 uint32_t hubaddr        : 7;
1213                 uint32_t prtaddr        : 7;
1214         } s;
1215 };
1216 typedef union cvmx_usbcx_hcspltx cvmx_usbcx_hcspltx_t;
1217
1218 /**
1219  * cvmx_usbc#_hctsiz#
1220  *
1221  * Host Channel-n Transfer Size Register (HCTSIZ)
1222  *
1223  */
1224 union cvmx_usbcx_hctsizx {
1225         uint32_t u32;
1226         /**
1227          * struct cvmx_usbcx_hctsizx_s
1228          * @dopng: Do Ping (DoPng)
1229          *      Setting this field to 1 directs the host to do PING protocol.
1230          * @pid: PID (Pid)
1231          *      The application programs this field with the type of PID to use
1232          *      for the initial transaction. The host will maintain this field
1233          *      for the rest of the transfer.
1234          *      * 2'b00: DATA0
1235          *      * 2'b01: DATA2
1236          *      * 2'b10: DATA1
1237          *      * 2'b11: MDATA (non-control)/SETUP (control)
1238          * @pktcnt: Packet Count (PktCnt)
1239          *      This field is programmed by the application with the expected
1240          *      number of packets to be transmitted (OUT) or received (IN).
1241          *      The host decrements this count on every successful
1242          *      transmission or reception of an OUT/IN packet. Once this count
1243          *      reaches zero, the application is interrupted to indicate normal
1244          *      completion.
1245          * @xfersize: Transfer Size (XferSize)
1246          *      For an OUT, this field is the number of data bytes the host will
1247          *      send during the transfer.
1248          *      For an IN, this field is the buffer size that the application
1249          *      has reserved for the transfer. The application is expected to
1250          *      program this field as an integer multiple of the maximum packet
1251          *      size for IN transactions (periodic and non-periodic).
1252          */
1253         struct cvmx_usbcx_hctsizx_s {
1254                 uint32_t dopng          : 1;
1255                 uint32_t pid            : 2;
1256                 uint32_t pktcnt         : 10;
1257                 uint32_t xfersize       : 19;
1258         } s;
1259 };
1260 typedef union cvmx_usbcx_hctsizx cvmx_usbcx_hctsizx_t;
1261
1262 /**
1263  * cvmx_usbc#_hfir
1264  *
1265  * Host Frame Interval Register (HFIR)
1266  *
1267  * This register stores the frame interval information for the current speed to
1268  * which the O2P USB core has enumerated.
1269  */
1270 union cvmx_usbcx_hfir {
1271         uint32_t u32;
1272         /**
1273          * struct cvmx_usbcx_hfir_s
1274          * @frint: Frame Interval (FrInt)
1275          *      The value that the application programs to this field specifies
1276          *      the interval between two consecutive SOFs (FS) or micro-
1277          *      SOFs (HS) or Keep-Alive tokens (HS). This field contains the
1278          *      number of PHY clocks that constitute the required frame
1279          *      interval. The default value set in this field for a FS operation
1280          *      when the PHY clock frequency is 60 MHz. The application can
1281          *      write a value to this register only after the Port Enable bit of
1282          *      the Host Port Control and Status register (HPRT.PrtEnaPort)
1283          *      has been set. If no value is programmed, the core calculates
1284          *      the value based on the PHY clock specified in the FS/LS PHY
1285          *      Clock Select field of the Host Configuration register
1286          *      (HCFG.FSLSPclkSel). Do not change the value of this field
1287          *      after the initial configuration.
1288          *      * 125 us (PHY clock frequency for HS)
1289          *      * 1 ms (PHY clock frequency for FS/LS)
1290          */
1291         struct cvmx_usbcx_hfir_s {
1292                 uint32_t reserved_16_31 : 16;
1293                 uint32_t frint          : 16;
1294         } s;
1295 };
1296 typedef union cvmx_usbcx_hfir cvmx_usbcx_hfir_t;
1297
1298 /**
1299  * cvmx_usbc#_hfnum
1300  *
1301  * Host Frame Number/Frame Time Remaining Register (HFNUM)
1302  *
1303  * This register indicates the current frame number.
1304  * It also indicates the time remaining (in terms of the number of PHY clocks)
1305  * in the current (micro)frame.
1306  */
1307 union cvmx_usbcx_hfnum {
1308         uint32_t u32;
1309         /**
1310          * struct cvmx_usbcx_hfnum_s
1311          * @frrem: Frame Time Remaining (FrRem)
1312          *      Indicates the amount of time remaining in the current
1313          *      microframe (HS) or frame (FS/LS), in terms of PHY clocks.
1314          *      This field decrements on each PHY clock. When it reaches
1315          *      zero, this field is reloaded with the value in the Frame
1316          *      Interval register and a new SOF is transmitted on the USB.
1317          * @frnum: Frame Number (FrNum)
1318          *      This field increments when a new SOF is transmitted on the
1319          *      USB, and is reset to 0 when it reaches 16'h3FFF.
1320          */
1321         struct cvmx_usbcx_hfnum_s {
1322                 uint32_t frrem  : 16;
1323                 uint32_t frnum  : 16;
1324         } s;
1325 };
1326 typedef union cvmx_usbcx_hfnum cvmx_usbcx_hfnum_t;
1327
1328 /**
1329  * cvmx_usbc#_hprt
1330  *
1331  * Host Port Control and Status Register (HPRT)
1332  *
1333  * This register is available in both Host and Device modes.
1334  * Currently, the OTG Host supports only one port.
1335  * A single register holds USB port-related information such as USB reset,
1336  * enable, suspend, resume, connect status, and test mode for each port. The
1337  * R_SS_WC bits in this register can trigger an interrupt to the application
1338  * through the Host Port Interrupt bit of the Core Interrupt register
1339  * (GINTSTS.PrtInt). On a Port Interrupt, the application must read this
1340  * register and clear the bit that caused the interrupt. For the R_SS_WC bits,
1341  * the application must write a 1 to the bit to clear the interrupt.
1342  */
1343 union cvmx_usbcx_hprt {
1344         uint32_t u32;
1345         /**
1346          * struct cvmx_usbcx_hprt_s
1347          * @prtspd: Port Speed (PrtSpd)
1348          *      Indicates the speed of the device attached to this port.
1349          *      * 2'b00: High speed
1350          *      * 2'b01: Full speed
1351          *      * 2'b10: Low speed
1352          *      * 2'b11: Reserved
1353          * @prttstctl: Port Test Control (PrtTstCtl)
1354          *      The application writes a nonzero value to this field to put
1355          *      the port into a Test mode, and the corresponding pattern is
1356          *      signaled on the port.
1357          *      * 4'b0000: Test mode disabled
1358          *      * 4'b0001: Test_J mode
1359          *      * 4'b0010: Test_K mode
1360          *      * 4'b0011: Test_SE0_NAK mode
1361          *      * 4'b0100: Test_Packet mode
1362          *      * 4'b0101: Test_Force_Enable
1363          *      * Others: Reserved
1364          *      PrtSpd must be zero (i.e. the interface must be in high-speed
1365          *      mode) to use the PrtTstCtl test modes.
1366          * @prtpwr: Port Power (PrtPwr)
1367          *      The application uses this field to control power to this port,
1368          *      and the core clears this bit on an overcurrent condition.
1369          *      * 1'b0: Power off
1370          *      * 1'b1: Power on
1371          * @prtlnsts: Port Line Status (PrtLnSts)
1372          *      Indicates the current logic level USB data lines
1373          *      * Bit [10]: Logic level of D-
1374          *      * Bit [11]: Logic level of D+
1375          * @prtrst: Port Reset (PrtRst)
1376          *      When the application sets this bit, a reset sequence is
1377          *      started on this port. The application must time the reset
1378          *      period and clear this bit after the reset sequence is
1379          *      complete.
1380          *      * 1'b0: Port not in reset
1381          *      * 1'b1: Port in reset
1382          *      The application must leave this bit set for at least a
1383          *      minimum duration mentioned below to start a reset on the
1384          *      port. The application can leave it set for another 10 ms in
1385          *      addition to the required minimum duration, before clearing
1386          *      the bit, even though there is no maximum limit set by the
1387          *      USB standard.
1388          *      * High speed: 50 ms
1389          *      * Full speed/Low speed: 10 ms
1390          * @prtsusp: Port Suspend (PrtSusp)
1391          *      The application sets this bit to put this port in Suspend
1392          *      mode. The core only stops sending SOFs when this is set.
1393          *      To stop the PHY clock, the application must set the Port
1394          *      Clock Stop bit, which will assert the suspend input pin of
1395          *      the PHY.
1396          *      The read value of this bit reflects the current suspend
1397          *      status of the port. This bit is cleared by the core after a
1398          *      remote wakeup signal is detected or the application sets
1399          *      the Port Reset bit or Port Resume bit in this register or the
1400          *      Resume/Remote Wakeup Detected Interrupt bit or
1401          *      Disconnect Detected Interrupt bit in the Core Interrupt
1402          *      register (GINTSTS.WkUpInt or GINTSTS.DisconnInt,
1403          *      respectively).
1404          *      * 1'b0: Port not in Suspend mode
1405          *      * 1'b1: Port in Suspend mode
1406          * @prtres: Port Resume (PrtRes)
1407          *      The application sets this bit to drive resume signaling on
1408          *      the port. The core continues to drive the resume signal
1409          *      until the application clears this bit.
1410          *      If the core detects a USB remote wakeup sequence, as
1411          *      indicated by the Port Resume/Remote Wakeup Detected
1412          *      Interrupt bit of the Core Interrupt register
1413          *      (GINTSTS.WkUpInt), the core starts driving resume
1414          *      signaling without application intervention and clears this bit
1415          *      when it detects a disconnect condition. The read value of
1416          *      this bit indicates whether the core is currently driving
1417          *      resume signaling.
1418          *      * 1'b0: No resume driven
1419          *      * 1'b1: Resume driven
1420          * @prtovrcurrchng: Port Overcurrent Change (PrtOvrCurrChng)
1421          *      The core sets this bit when the status of the Port
1422          *      Overcurrent Active bit (bit 4) in this register changes.
1423          * @prtovrcurract: Port Overcurrent Active (PrtOvrCurrAct)
1424          *      Indicates the overcurrent condition of the port.
1425          *      * 1'b0: No overcurrent condition
1426          *      * 1'b1: Overcurrent condition
1427          * @prtenchng: Port Enable/Disable Change (PrtEnChng)
1428          *      The core sets this bit when the status of the Port Enable bit
1429          *      [2] of this register changes.
1430          * @prtena: Port Enable (PrtEna)
1431          *      A port is enabled only by the core after a reset sequence,
1432          *      and is disabled by an overcurrent condition, a disconnect
1433          *      condition, or by the application clearing this bit. The
1434          *      application cannot set this bit by a register write. It can only
1435          *      clear it to disable the port. This bit does not trigger any
1436          *      interrupt to the application.
1437          *      * 1'b0: Port disabled
1438          *      * 1'b1: Port enabled
1439          * @prtconndet: Port Connect Detected (PrtConnDet)
1440          *      The core sets this bit when a device connection is detected
1441          *      to trigger an interrupt to the application using the Host Port
1442          *      Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).
1443          *      The application must write a 1 to this bit to clear the
1444          *      interrupt.
1445          * @prtconnsts: Port Connect Status (PrtConnSts)
1446          *      * 0: No device is attached to the port.
1447          *      * 1: A device is attached to the port.
1448          */
1449         struct cvmx_usbcx_hprt_s {
1450                 uint32_t reserved_19_31 : 13;
1451                 uint32_t prtspd         : 2;
1452                 uint32_t prttstctl      : 4;
1453                 uint32_t prtpwr         : 1;
1454                 uint32_t prtlnsts       : 2;
1455                 uint32_t reserved_9_9   : 1;
1456                 uint32_t prtrst         : 1;
1457                 uint32_t prtsusp        : 1;
1458                 uint32_t prtres         : 1;
1459                 uint32_t prtovrcurrchng : 1;
1460                 uint32_t prtovrcurract  : 1;
1461                 uint32_t prtenchng      : 1;
1462                 uint32_t prtena         : 1;
1463                 uint32_t prtconndet     : 1;
1464                 uint32_t prtconnsts     : 1;
1465         } s;
1466 };
1467 typedef union cvmx_usbcx_hprt cvmx_usbcx_hprt_t;
1468
1469 /**
1470  * cvmx_usbc#_hptxfsiz
1471  *
1472  * Host Periodic Transmit FIFO Size Register (HPTXFSIZ)
1473  *
1474  * This register holds the size and the memory start address of the Periodic
1475  * TxFIFO, as shown in Figures 310 and 311.
1476  */
1477 union cvmx_usbcx_hptxfsiz {
1478         uint32_t u32;
1479         /**
1480          * struct cvmx_usbcx_hptxfsiz_s
1481          * @ptxfsize: Host Periodic TxFIFO Depth (PTxFSize)
1482          *      This value is in terms of 32-bit words.
1483          *      * Minimum value is 16
1484          *      * Maximum value is 32768
1485          * @ptxfstaddr: Host Periodic TxFIFO Start Address (PTxFStAddr)
1486          */
1487         struct cvmx_usbcx_hptxfsiz_s {
1488                 uint32_t ptxfsize       : 16;
1489                 uint32_t ptxfstaddr     : 16;
1490         } s;
1491 };
1492 typedef union cvmx_usbcx_hptxfsiz cvmx_usbcx_hptxfsiz_t;
1493
1494 /**
1495  * cvmx_usbc#_hptxsts
1496  *
1497  * Host Periodic Transmit FIFO/Queue Status Register (HPTXSTS)
1498  *
1499  * This read-only register contains the free space information for the Periodic
1500  * TxFIFO and the Periodic Transmit Request Queue
1501  */
1502 union cvmx_usbcx_hptxsts {
1503         uint32_t u32;
1504         /**
1505          * struct cvmx_usbcx_hptxsts_s
1506          * @ptxqtop: Top of the Periodic Transmit Request Queue (PTxQTop)
1507          *      This indicates the entry in the Periodic Tx Request Queue that
1508          *      is currently being processes by the MAC.
1509          *      This register is used for debugging.
1510          *      * Bit [31]: Odd/Even (micro)frame
1511          *      - 1'b0: send in even (micro)frame
1512          *      - 1'b1: send in odd (micro)frame
1513          *      * Bits [30:27]: Channel/endpoint number
1514          *      * Bits [26:25]: Type
1515          *      - 2'b00: IN/OUT
1516          *      - 2'b01: Zero-length packet
1517          *      - 2'b10: CSPLIT
1518          *      - 2'b11: Disable channel command
1519          *      * Bit [24]: Terminate (last entry for the selected
1520          *      channel/endpoint)
1521          * @ptxqspcavail: Periodic Transmit Request Queue Space Available
1522          *      (PTxQSpcAvail)
1523          *      Indicates the number of free locations available to be written
1524          *      in the Periodic Transmit Request Queue. This queue holds both
1525          *      IN and OUT requests.
1526          *      * 8'h0: Periodic Transmit Request Queue is full
1527          *      * 8'h1: 1 location available
1528          *      * 8'h2: 2 locations available
1529          *      * n: n locations available (0..8)
1530          *      * Others: Reserved
1531          * @ptxfspcavail: Periodic Transmit Data FIFO Space Available
1532          *                (PTxFSpcAvail)
1533          *      Indicates the number of free locations available to be written
1534          *      to in the Periodic TxFIFO.
1535          *      Values are in terms of 32-bit words
1536          *      * 16'h0: Periodic TxFIFO is full
1537          *      * 16'h1: 1 word available
1538          *      * 16'h2: 2 words available
1539          *      * 16'hn: n words available (where 0..32768)
1540          *      * 16'h8000: 32768 words available
1541          *      * Others: Reserved
1542          */
1543         struct cvmx_usbcx_hptxsts_s {
1544                 uint32_t ptxqtop        : 8;
1545                 uint32_t ptxqspcavail   : 8;
1546                 uint32_t ptxfspcavail   : 16;
1547         } s;
1548 };
1549 typedef union cvmx_usbcx_hptxsts cvmx_usbcx_hptxsts_t;
1550
1551 #endif