target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts

   1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
   2 /*
   3  * Copyright (C) 2019 Marvell International Ltd.
   4  *
   5  * Device tree for the CN9131-DB board.
   6  */
   7
   8 #include "cn9130.dtsi"
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12
  13 / {
  14         model = "iEi Puzzle-M901";
  15         compatible = "iei,puzzle-m901",
  16                      "marvell,armada-ap807-quad", "marvell,armada-ap807";
  17
  18         chosen {
  19                 stdout-path = "serial0:115200n8";
  20         };
  21
  22         aliases {
  23                 i2c0 = &cp1_i2c0;
  24                 i2c1 = &cp0_i2c0;
  25                 ethernet0 = &cp0_eth0;
  26                 ethernet1 = &cp0_eth1;
  27                 ethernet2 = &cp0_eth2;
  28                 ethernet3 = &cp1_eth0;
  29                 ethernet4 = &cp1_eth1;
  30                 ethernet5 = &cp1_eth2;
  31                 gpio1 = &cp0_gpio1;
  32                 gpio2 = &cp0_gpio2;
  33                 gpio3 = &cp1_gpio1;
  34                 gpio4 = &cp1_gpio2;
  35                 led-boot = &led_power;
  36                 led-failsafe = &led_info;
  37                 led-running = &led_power;
  38                 led-upgrade = &led_info;
  39         };
  40
  41         memory@00000000 {
  42                 device_type = "memory";
  43                 reg = <0x0 0x0 0x0 0x80000000>;
  44         };
  45
  46         gpio_keys {
  47                 compatible = "gpio-keys";
  48
  49                 reset {
  50                         label = "Reset";
  51                         linux,code = <KEY_RESTART>;
  52                         gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
  53                 };
  54         };
  55 };
  56
  57 &uart0 {
  58         status = "okay";
  59 };
  60
  61 &cp0_uart0 {
  62         status = "okay";
  63
  64         puzzle-mcu {
  65                 compatible = "iei,wt61p803-puzzle";
  66                 #address-cells = <1>;
  67                 #size-cells = <1>;
  68                 current-speed = <115200>;
  69                 enable-beep;
  70                 status = "okay";
  71
  72                 leds {
  73                         compatible = "iei,wt61p803-puzzle-leds";
  74                         #address-cells = <1>;
  75                         #size-cells = <0>;
  76                         status = "okay";
  77
  78                         led@0 {
  79                                 reg = <0>;
  80                                 label = "white:network";
  81                                 active-low;
  82                         };
  83
  84                         led@1 {
  85                                 reg = <1>;
  86                                 label = "green:cloud";
  87                                 active-low;
  88                         };
  89
  90                         led_info: led@2 {
  91                                 reg = <2>;
  92                                 label = "orange:info";
  93                                 active-low;
  94                         };
  95
  96                         led_power: led@3 {
  97                                 reg = <3>;
  98                                 label = "yellow:power";
  99                                 active-low;
 100                                 default-state = "on";
 101                         };
 102                 };
 103
 104                 hwmon {
 105                         compatible = "iei,wt61p803-puzzle-hwmon";
 106                         #address-cells = <1>;
 107                         #size-cells = <0>;
 108
 109                         chassis_fan_group0: fan-group@0 {
 110                                 #cooling-cells = <2>;
 111                                 reg = <0x00>;
 112                                 cooling-levels = <64 102 170 230 250>;
 113                         };
 114                 };
 115         };
 116 };
 117
 118 &ap_thermal_cpu1 {
 119         trips {
 120                 cpu_active: cpu-active {
 121                         temperature = <44000>;
 122                         hysteresis = <2000>;
 123                         type = "active";
 124                 };
 125         };
 126         cooling-maps {
 127                 fan-map {
 128                         trip = <&cpu_active>;
 129                         cooling-device = <&chassis_fan_group0 64 THERMAL_NO_LIMIT>;
 130                 };
 131         };
 132 };
 133
 134 /* on-board eMMC - U9 */
 135 &ap_sdhci0 {
 136         pinctrl-names = "default";
 137         bus-width = <8>;
 138         status = "okay";
 139         mmc-ddr-1_8v;
 140         mmc-hs400-1_8v;
 141 };
 142
 143 &cp0_crypto {
 144         status = "okay";
 145 };
 146
 147 &cp0_xmdio {
 148         status = "okay";
 149         cp0_nbaset_phy0: ethernet-phy@0 {
 150                 compatible = "ethernet-phy-ieee802.3-c45";
 151                 reg = <2>;
 152         };
 153         cp0_nbaset_phy1: ethernet-phy@1 {
 154                 compatible = "ethernet-phy-ieee802.3-c45";
 155                 reg = <0>;
 156         };
 157         cp0_nbaset_phy2: ethernet-phy@2 {
 158                 compatible = "ethernet-phy-ieee802.3-c45";
 159                 reg = <8>;
 160         };
 161 };
 162
 163 &cp0_ethernet {
 164         status = "okay";
 165 };
 166
 167 /* SLM-1521-V2, CON9 */
 168 &cp0_eth0 {
 169         status = "okay";
 170         phy-mode = "2500base-x";
 171         phys = <&cp0_comphy2 0>;
 172         phy = <&cp0_nbaset_phy0>;
 173 };
 174
 175 &cp0_eth1 {
 176         status = "okay";
 177         phy-mode = "2500base-x";
 178         phys = <&cp0_comphy4 1>;
 179         phy = <&cp0_nbaset_phy1>;
 180 };
 181
 182 &cp0_eth2 {
 183         status = "okay";
 184         phy-mode = "2500base-x";
 185         phys = <&cp0_comphy5 2>;
 186         phy = <&cp0_nbaset_phy2>;
 187 };
 188
 189 &cp0_gpio1 {
 190         status = "okay";
 191 };
 192
 193 &cp0_gpio2 {
 194         status = "okay";
 195 };
 196
 197 &cp0_i2c0 {
 198         pinctrl-names = "default";
 199         pinctrl-0 = <&cp0_i2c0_pins>;
 200         status = "okay";
 201         clock-frequency = <100000>;
 202         rtc@32 {
 203                 compatible = "epson,rx8130";
 204                 reg = <0x32>;
 205                 wakeup-source;
 206         };
 207 };
 208
 209 /* SLM-1521-V2, CON6 */
 210 &cp0_pcie0 {
 211         status = "okay";
 212         num-lanes = <2>;
 213         num-viewport = <8>;
 214         phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
 215 };
 216
 217 /* U55 */
 218 &cp0_spi1 {
 219         pinctrl-names = "default";
 220         pinctrl-0 = <&cp0_spi0_pins>;
 221         reg = <0x700680 0x50>,          /* control */
 222               <0x2000000 0x1000000>;    /* CS0 */
 223         status = "okay";
 224         spi-flash@0 {
 225                 #address-cells = <0x1>;
 226                 #size-cells = <0x1>;
 227                 compatible = "jedec,spi-nor";
 228                 reg = <0x0>;
 229                 spi-max-frequency = <40000000>;
 230                 partitions {
 231                         compatible = "fixed-partitions";
 232                         #address-cells = <1>;
 233                         #size-cells = <1>;
 234                         partition@0 {
 235                                 label = "U-Boot";
 236                                 reg = <0x0 0x1f0000>;
 237                         };
 238                         partition@1f0000 {
 239                                 label = "U-Boot ENV Factory";
 240                                 reg = <0x1f0000 0x10000>;
 241                         };
 242                         partition@200000 {
 243                                 label = "Reserved";
 244                                 reg = <0x200000 0x1f0000>;
 245                         };
 246                         partition@3f0000 {
 247                                 label = "U-Boot ENV";
 248                                 reg = <0x3f0000 0x10000>;
 249                         };
 250                 };
 251         };
 252 };
 253
 254 &cp0_syscon0 {
 255         cp0_pinctrl: pinctrl {
 256                 compatible = "marvell,cp115-standalone-pinctrl";
 257                 cp0_i2c0_pins: cp0-i2c-pins-0 {
 258                         marvell,pins = "mpp37", "mpp38";
 259                         marvell,function = "i2c0";
 260                 };
 261                 cp0_i2c1_pins: cp0-i2c-pins-1 {
 262                         marvell,pins = "mpp35", "mpp36";
 263                         marvell,function = "i2c1";
 264                 };
 265                 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
 266                         marvell,pins = "mpp0", "mpp1", "mpp2",
 267                                        "mpp3", "mpp4", "mpp5",
 268                                        "mpp6", "mpp7", "mpp8",
 269                                        "mpp9", "mpp10", "mpp11";
 270                         marvell,function = "ge0";
 271                 };
 272                 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
 273                         marvell,pins = "mpp44", "mpp45", "mpp46",
 274                                        "mpp47", "mpp48", "mpp49",
 275                                        "mpp50", "mpp51", "mpp52",
 276                                        "mpp53", "mpp54", "mpp55";
 277                         marvell,function = "ge1";
 278                 };
 279                 cp0_spi0_pins: cp0-spi-pins-0 {
 280                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 281                         marvell,function = "spi1";
 282                 };
 283         };
 284 };
 285
 286 /*
 287  * Instantiate the first connected CP115
 288  */
 289
 290 #define CP11X_NAME              cp1
 291 #define CP11X_BASE              f6000000
 292 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
 293 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
 294 #define CP11X_PCIE0_BASE        f6600000
 295 #define CP11X_PCIE1_BASE        f6620000
 296 #define CP11X_PCIE2_BASE        f6640000
 297
 298 #include "armada-cp115.dtsi"
 299
 300 #undef CP11X_NAME
 301 #undef CP11X_BASE
 302 #undef CP11X_PCIEx_MEM_BASE
 303 #undef CP11X_PCIEx_MEM_SIZE
 304 #undef CP11X_PCIE0_BASE
 305 #undef CP11X_PCIE1_BASE
 306 #undef CP11X_PCIE2_BASE
 307
 308 &cp1_crypto {
 309         status = "okay";
 310 };
 311
 312 &cp1_xmdio {
 313         status = "okay";
 314         cp1_nbaset_phy0: ethernet-phy@3 {
 315                 compatible = "ethernet-phy-ieee802.3-c45";
 316                 reg = <2>;
 317         };
 318         cp1_nbaset_phy1: ethernet-phy@4 {
 319                 compatible = "ethernet-phy-ieee802.3-c45";
 320                 reg = <0>;
 321         };
 322         cp1_nbaset_phy2: ethernet-phy@5 {
 323                 compatible = "ethernet-phy-ieee802.3-c45";
 324                 reg = <8>;
 325         };
 326 };
 327
 328 &cp1_ethernet {
 329         status = "okay";
 330 };
 331
 332 /* CON50 */
 333 &cp1_eth0 {
 334         status = "okay";
 335         phy-mode = "2500base-x";
 336         phys = <&cp1_comphy2 0>;
 337         phy = <&cp1_nbaset_phy0>;
 338 };
 339
 340 &cp1_eth1 {
 341         status = "okay";
 342         phy-mode = "2500base-x";
 343         phys = <&cp1_comphy4 1>;
 344         phy = <&cp1_nbaset_phy1>;
 345 };
 346
 347 &cp1_eth2 {
 348         status = "okay";
 349         phy-mode = "2500base-x";
 350         phys = <&cp1_comphy5 2>;
 351         phy = <&cp1_nbaset_phy2>;
 352 };
 353
 354 &cp1_sata0 {
 355         status = "okay";
 356         sata-port@1 {
 357                 status = "okay";
 358                 phys = <&cp1_comphy0 1>;
 359         };
 360 };
 361
 362 &cp1_gpio1 {
 363         status = "okay";
 364 };
 365
 366 &cp1_gpio2 {
 367         status = "okay";
 368 };
 369
 370 &cp1_i2c0 {
 371         status = "okay";
 372         pinctrl-names = "default";
 373         pinctrl-0 = <&cp1_i2c0_pins>;
 374         clock-frequency = <100000>;
 375 };
 376
 377 &cp1_syscon0 {
 378         cp1_pinctrl: pinctrl {
 379                 compatible = "marvell,cp115-standalone-pinctrl";
 380                 cp1_i2c0_pins: cp1-i2c-pins-0 {
 381                         marvell,pins = "mpp37", "mpp38";
 382                         marvell,function = "i2c0";
 383                 };
 384                 cp1_spi0_pins: cp1-spi-pins-0 {
 385                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 386                         marvell,function = "spi1";
 387                 };
 388                 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
 389                         marvell,pins = "mpp3";
 390                         marvell,function = "gpio";
 391                 };
 392                 cp1_sfp_pins: sfp-pins {
 393                         marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
 394                         marvell,function = "gpio";
 395                 };
 396         };
 397 };
 398
 399 &cp1_usb3_1 {
 400         status = "okay";
 401         phys = <&cp1_comphy3 1>;
 402         phy-names = "usb";
 403 };