506e01f0ff1b00f206e7f58a871ff17226914b02
[openwrt/openwrt.git] / target / linux / mvebu / files / arch / arm / boot / dts / armada-385-fortinet-fg-50e.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 /dts-v1/;
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8 #include "armada-385.dtsi"
9
10 / {
11 model = "Fortinet FortiGate 50E";
12 compatible = "fortinet,fg-50e", "marvell,armada385", "marvell,armada380";
13
14 aliases {
15 led-boot = &led_status_green;
16 led-failsafe = &led_status_red;
17 led-running = &led_status_green;
18 led-upgrade = &led_status_green;
19 label-mac-device = &eth0;
20 };
21
22 chosen {
23 stdout-path = "serial0:9600n8";
24 };
25
26 memory@0 {
27 device_type = "memory";
28 reg = <0x00000000 0x80000000>; /* 2GB */
29 };
30
31 soc {
32 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
33 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
34 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
35 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
36 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
37 };
38
39 gpio-keys {
40 compatible = "gpio-keys";
41 pinctrl-names = "default";
42 pinctrl-0 = <&pmx_gpio_keys_pins>;
43
44 reset {
45 label = "reset";
46 linux,code = <KEY_RESTART>;
47 gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
48 };
49 };
50
51 gpio-leds {
52 compatible = "gpio-leds";
53 pinctrl-names = "default";
54 pinctrl-0 = <&pmx_gpio_leds_pins>;
55
56 led-0 {
57 label = "red:alarm";
58 gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
59 color = <LED_COLOR_ID_RED>;
60 function = LED_FUNCTION_ALARM;
61 };
62
63 led-1 {
64 label = "red:ha";
65 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
66 color = <LED_COLOR_ID_RED>;
67 };
68
69 led_status_green: led-2 {
70 label = "green:sta";
71 gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
72 color = <LED_COLOR_ID_GREEN>;
73 function = LED_FUNCTION_STATUS;
74 };
75
76 led-3 {
77 label = "green:ha";
78 gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
79 color = <LED_COLOR_ID_GREEN>;
80 };
81
82 led-4 {
83 label = "amber:alarm";
84 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
85 color = <LED_COLOR_ID_AMBER>;
86 function = LED_FUNCTION_ALARM;
87 };
88
89 led_status_red: led-5 {
90 label = "red:sta";
91 gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
92 color = <LED_COLOR_ID_RED>;
93 function = LED_FUNCTION_STATUS;
94 };
95
96 led-6 {
97 label = "green:speed_wan1";
98 gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
99 color = <LED_COLOR_ID_GREEN>;
100 };
101
102 led-7 {
103 label = "green:speed_wan2";
104 gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
105 color = <LED_COLOR_ID_GREEN>;
106 };
107
108 led-8 {
109 label = "amber:speed_lan5";
110 gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
111 color = <LED_COLOR_ID_AMBER>;
112 };
113
114 led-9 {
115 label = "green:speed_lan5";
116 gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
117 color = <LED_COLOR_ID_GREEN>;
118 };
119
120 led-10 {
121 label = "green:speed_lan4";
122 gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
123 color = <LED_COLOR_ID_GREEN>;
124 };
125
126 led-11 {
127 label = "amber:speed_lan4";
128 gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
129 color = <LED_COLOR_ID_AMBER>;
130 };
131
132 led-12 {
133 label = "amber:speed_lan3";
134 gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
135 color = <LED_COLOR_ID_AMBER>;
136 };
137
138 led-13 {
139 label = "green:speed_lan3";
140 gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
141 color = <LED_COLOR_ID_GREEN>;
142 };
143
144 led-14 {
145 label = "green:speed_lan1";
146 gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
147 color = <LED_COLOR_ID_GREEN>;
148 };
149
150 led-15 {
151 label = "amber:speed_lan1";
152 gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
153 color = <LED_COLOR_ID_AMBER>;
154 };
155
156 led-16 {
157 label = "green:speed_lan2";
158 gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
159 color = <LED_COLOR_ID_GREEN>;
160 };
161
162 led-17 {
163 label = "amber:speed_lan2";
164 gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
165 color = <LED_COLOR_ID_AMBER>;
166 };
167 };
168
169 reg_usb_vbus: regulator-usb-vbus {
170 compatible = "fixed-regulator";
171 regulator-name = "usb-vbus";
172 regulator-min-microvolt = <5000000>;
173 regulator-max-microvolt = <5000000>;
174 gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
175 regulator-always-on;
176 };
177 };
178
179 &i2c0 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&i2c0_pins>;
182 status = "okay";
183
184 gpio2: gpio@24 {
185 compatible = "nxp,pca9555";
186 reg = <0x24>;
187 gpio-controller;
188 #gpio-cells = <0x2>;
189 };
190
191 hwmon@28 {
192 compatible = "nuvoton,nct7802";
193 reg = <0x28>;
194 };
195 };
196
197 &uart0 {
198 pinctrl-names = "default";
199 pinctrl-0 = <&uart0_pins>;
200 status = "okay";
201 };
202
203 &pinctrl {
204 pmx_phy_switch_pins: phy-switch-pins {
205 marvell,pins = "mpp19", "mpp20", "mpp23", "mpp34", "mpp41";
206 marvell,function = "gpio";
207 };
208
209 pmx_gpio_leds_pins: gpio-leds-pins {
210 marvell,pins = "mpp30", "mpp32", "mpp33", "mpp35",
211 "mpp45", "mpp47";
212 marvell,function = "gpio";
213 };
214
215 pmx_usb_pins: usb-pins {
216 marvell,pins = "mpp53";
217 marvell,function = "gpio";
218 };
219
220 pmx_gpio_keys_pins: gpio-keys-pins {
221 marvell,pins = "mpp54";
222 marvell,function = "gpio";
223 };
224 };
225
226 &bm {
227 status = "okay";
228 };
229
230 &bm_bppi {
231 status = "okay";
232 };
233
234 &eth0 {
235 pinctrl-names = "default";
236 pinctrl-0 = <&ge0_rgmii_pins>;
237 status = "okay";
238
239 phy-connection-type = "rgmii-id";
240 buffer-manager = <&bm>;
241 bm,pool-long = <0>;
242 bm,pool-short = <1>;
243 nvmem-cells = <&macaddr_bdinfo_d880>;
244 nvmem-cell-names = "mac-address";
245
246 fixed-link {
247 speed = <1000>;
248 full-duplex;
249 };
250 };
251
252 &eth1 {
253 status = "okay";
254
255 phy-handle = <&ethphy0>;
256 phy-connection-type = "sgmii";
257 buffer-manager = <&bm>;
258 bm,pool-long = <2>;
259 nvmem-cells = <&macaddr_bdinfo_d880>;
260 nvmem-cell-names = "mac-address";
261 mac-address-increment = <1>;
262 };
263
264 &eth2 {
265 status = "okay";
266
267 phy-handle = <&ethphy1>;
268 phy-connection-type = "sgmii";
269 buffer-manager = <&bm>;
270 bm,pool-long = <3>;
271 nvmem-cells = <&macaddr_bdinfo_d880>;
272 nvmem-cell-names = "mac-address";
273 mac-address-increment = <2>;
274 };
275
276 &mdio {
277 pinctrl-names = "default";
278 pinctrl-0 = <&mdio_pins>, <&pmx_phy_switch_pins>;
279
280 /* Marvell 88E1512 */
281 ethphy0: ethernet-phy@0 {
282 compatible = "ethernet-phy-id0141,0dd1",
283 "ethernet-phy-ieee802.3-c22";
284 reg = <0>;
285 interrupt-parent = <&gpio0>;
286 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
287 reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
288 /*
289 * LINK/ACT (Green): LED[0], Active Low
290 * SPEED 100M (Amber): LED[1], Active High
291 */
292 marvell,reg-init = <3 16 0 0x71>,
293 <3 17 0 0x4>;
294 };
295
296 /* Marvell 88E1512 */
297 ethphy1: ethernet-phy@1 {
298 compatible = "ethernet-phy-id0141,0dd1",
299 "ethernet-phy-ieee802.3-c22";
300 reg = <1>;
301 interrupt-parent = <&gpio1>;
302 interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
303 reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
304 /*
305 * LINK/ACT (Green): LED[0], Active Low
306 * SPEED 100M (Amber): LED[1], Active High
307 */
308 marvell,reg-init = <3 16 0 0x71>,
309 <3 17 0 0x4>;
310 };
311
312 /* Marvell 88E6176 */
313 switch@2 {
314 compatible = "marvell,mv88e6085";
315 reg = <0x2>;
316 reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
317
318 ports {
319 #address-cells = <1>;
320 #size-cells = <0>;
321
322 port@0 {
323 reg = <0>;
324 label = "lan5";
325 nvmem-cells = <&macaddr_bdinfo_d880>;
326 nvmem-cell-names = "mac-address";
327 mac-address-increment = <7>;
328 };
329
330 port@1 {
331 reg = <1>;
332 label = "lan4";
333 nvmem-cells = <&macaddr_bdinfo_d880>;
334 nvmem-cell-names = "mac-address";
335 mac-address-increment = <6>;
336 };
337
338 port@2 {
339 reg = <2>;
340 label = "lan3";
341 nvmem-cells = <&macaddr_bdinfo_d880>;
342 nvmem-cell-names = "mac-address";
343 mac-address-increment = <5>;
344 };
345
346 port@3 {
347 reg = <3>;
348 label = "lan2";
349 nvmem-cells = <&macaddr_bdinfo_d880>;
350 nvmem-cell-names = "mac-address";
351 mac-address-increment = <4>;
352 };
353
354 port@4 {
355 reg = <4>;
356 label = "lan1";
357 nvmem-cells = <&macaddr_bdinfo_d880>;
358 nvmem-cell-names = "mac-address";
359 mac-address-increment = <3>;
360 };
361
362 port@6 {
363 reg = <6>;
364 ethernet = <&eth0>;
365 phy-connection-type = "rgmii-id";
366
367 fixed-link {
368 speed = <1000>;
369 full-duplex;
370 };
371 };
372 };
373 };
374 };
375
376 &usb3_0 {
377 pinctrl-names = "default";
378 pinctrl-0 = <&pmx_usb_pins>;
379 status = "okay";
380
381 vbus-supply = <&reg_usb_vbus>;
382 };
383
384 &spi1 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&spi1_pins>;
387 status = "okay";
388
389 flash@0 {
390 compatible = "jedec,spi-nor";
391 reg = <0>;
392 spi-max-frequency = <50000000>;
393
394 partitions {
395 compatible = "fixed-partitions";
396 #address-cells = <1>;
397 #size-cells = <1>;
398
399 partition@0 {
400 reg = <0x0 0x1c0000>;
401 label = "u-boot";
402 read-only;
403 };
404
405 partition@1c0000 {
406 reg = <0x1c0000 0x10000>;
407 label = "firmware-info";
408
409 /*
410 * 0x10 - 0x2f : image name (image1)
411 * 0x30 - 0x4f : image name (image2)
412 * 0x170 (1byte): active image (0x0/0x1)
413 * 0x184 - 0x185: kernel block count (image1)
414 * 0x18c - 0x18d: rootfs block count (image1)
415 * 0x194 - 0x195: kernel block count (image2)
416 * 0x19c - 0x19d: rootfs block count (image2)
417 * 0x1be (1byte): bit7 -> active flag (image1)?
418 * 0x1ce (1byte): bit7 -> active flag (image2)?
419 *
420 * Note: block size --> 0x200 (512 bytes)
421 */
422 };
423
424 partition@1d0000 {
425 reg = <0x1d0000 0x10000>;
426 label = "dtb";
427 read-only;
428 };
429
430 partition@1e0000 {
431 reg = <0x1e0000 0x10000>;
432 label = "u-boot-env";
433 read-only;
434 };
435
436 partition@1f0000 {
437 reg = <0x1f0000 0x10000>;
438 label = "board-info";
439 read-only;
440
441 compatible = "nvmem-cells";
442 #address-cells = <1>;
443 #size-cells = <1>;
444
445 macaddr_bdinfo_d880: macaddr@d880 {
446 reg = <0xd880 0x6>;
447 };
448 };
449
450 partition@200000 {
451 reg = <0x200000 0x600000>;
452 label = "kernel";
453 };
454
455 partition@800000 {
456 reg = <0x800000 0x1800000>;
457 label = "rootfs";
458 };
459
460 partition@2000000 {
461 reg = <0x2000000 0x600000>;
462 label = "kn2";
463 read-only;
464 };
465
466 partition@2600000 {
467 reg = <0x2600000 0x1800000>;
468 label = "rfs2";
469 read-only;
470 };
471
472 partition@3e00000 {
473 reg = <0x3e00000 0x1200000>;
474 label = "part1";
475 read-only;
476 };
477
478 partition@5000000 {
479 reg = <0x5000000 0x1200000>;
480 label = "part2";
481 read-only;
482 };
483
484 partition@6200000 {
485 reg = <0x6200000 0x1e00000>;
486 label = "config";
487 read-only;
488 };
489 };
490 };
491 };