target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch

   1 From a751f7412e0098801673b80bc7a4738ae7d710ce Mon Sep 17 00:00:00 2001
   2 From: Frank Wunderlich <frank-w@public-files.de>
   3 Date: Fri, 6 Jan 2023 16:28:45 +0100
   4 Subject: [PATCH 10/19] arm64: dts: mt7986: add Bananapi R3
   5
   6 Add support for Bananapi R3 SBC.
   7
   8 - SD/eMMC support (switching first 4 bits of data-bus with sw6/D)
   9 - SPI-NAND/NOR support (switched CS by sw5/C)
  10 - all rj45 ports and both SFP working (eth1/lan4)
  11 - all USB-Ports + SIM-Slot tested
  12 - i2c and all uarts tested
  13 - wifi tested (with eeprom calibration data)
  14
  15 The device can boot from all 4 storage options. Both, SPI and MMC, can
  16 be switched using hardware switches on the board, see
  17 https://wiki.banana-pi.org/Banana_Pi_BPI-R3#Jumper_setting
  18
  19 Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
  20 Link: https://lore.kernel.org/r/20230106152845.88717-6-linux@fw-web.de
  21 Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  22 ---
  23  arch/arm64/boot/dts/mediatek/Makefile         |   5 +
  24  .../mt7986a-bananapi-bpi-r3-emmc.dtso         |  29 ++
  25  .../mt7986a-bananapi-bpi-r3-nand.dtso         |  55 +++
  26  .../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso |  68 +++
  27  .../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso  |  23 +
  28  .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts  | 450 ++++++++++++++++++
  29  6 files changed, 630 insertions(+)
  30  create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
  31  create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
  32  create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
  33  create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
  34  create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
  35
  36 --- a/arch/arm64/boot/dts/mediatek/Makefile
  37 +++ b/arch/arm64/boot/dts/mediatek/Makefile
  38 @@ -7,6 +7,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-ev
  39  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
  40  dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
  41  dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
  42 +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
  43 +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
  44 +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
  45 +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
  46 +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
  47  dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
  48  dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
  49  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
  50 --- /dev/null
  51 +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
  52 @@ -0,0 +1,29 @@
  53 +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
  54 +/*
  55 + * Copyright (C) 2021 MediaTek Inc.
  56 + * Author: Sam.Shih <sam.shih@mediatek.com>
  57 + */
  58 +
  59 +/dts-v1/;
  60 +/plugin/;
  61 +
  62 +/ {
  63 +       compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
  64 +
  65 +       fragment@0 {
  66 +               target-path = "/soc/mmc@11230000";
  67 +               __overlay__ {
  68 +                       bus-width = <8>;
  69 +                       max-frequency = <200000000>;
  70 +                       cap-mmc-highspeed;
  71 +                       mmc-hs200-1_8v;
  72 +                       mmc-hs400-1_8v;
  73 +                       hs400-ds-delay = <0x14014>;
  74 +                       non-removable;
  75 +                       no-sd;
  76 +                       no-sdio;
  77 +                       status = "okay";
  78 +               };
  79 +       };
  80 +};
  81 +
  82 --- /dev/null
  83 +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
  84 @@ -0,0 +1,55 @@
  85 +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
  86 +/*
  87 + * Authors: Daniel Golle <daniel@makrotopia.org>
  88 + *          Frank Wunderlich <frank-w@public-files.de>
  89 + */
  90 +
  91 +/dts-v1/;
  92 +/plugin/;
  93 +
  94 +/ {
  95 +       compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
  96 +
  97 +       fragment@0 {
  98 +               target-path = "/soc/spi@1100a000";
  99 +               __overlay__ {
 100 +                       #address-cells = <1>;
 101 +                       #size-cells = <0>;
 102 +                       spi_nand: spi_nand@0 {
 103 +                               compatible = "spi-nand";
 104 +                               reg = <0>;
 105 +                               spi-max-frequency = <10000000>;
 106 +                               spi-tx-bus-width = <4>;
 107 +                               spi-rx-bus-width = <4>;
 108 +
 109 +                               partitions {
 110 +                                       compatible = "fixed-partitions";
 111 +                                       #address-cells = <1>;
 112 +                                       #size-cells = <1>;
 113 +
 114 +                                       partition@0 {
 115 +                                               label = "bl2";
 116 +                                               reg = <0x0 0x80000>;
 117 +                                               read-only;
 118 +                                       };
 119 +
 120 +                                       partition@80000 {
 121 +                                               label = "reserved";
 122 +                                               reg = <0x80000 0x300000>;
 123 +                                       };
 124 +
 125 +                                       partition@380000 {
 126 +                                               label = "fip";
 127 +                                               reg = <0x380000 0x200000>;
 128 +                                               read-only;
 129 +                                       };
 130 +
 131 +                                       partition@580000 {
 132 +                                               label = "ubi";
 133 +                                               reg = <0x580000 0x7a80000>;
 134 +                                       };
 135 +                               };
 136 +                       };
 137 +               };
 138 +       };
 139 +};
 140 --- /dev/null
 141 +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
 142 @@ -0,0 +1,68 @@
 143 +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
 144 +/*
 145 + * Authors: Daniel Golle <daniel@makrotopia.org>
 146 + *          Frank Wunderlich <frank-w@public-files.de>
 147 + */
 148 +
 149 +/dts-v1/;
 150 +/plugin/;
 151 +
 152 +/ {
 153 +       compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
 154 +
 155 +       fragment@0 {
 156 +               target-path = "/soc/spi@1100a000";
 157 +               __overlay__ {
 158 +                       #address-cells = <1>;
 159 +                       #size-cells = <0>;
 160 +                       flash@0 {
 161 +                               compatible = "jedec,spi-nor";
 162 +                               reg = <0>;
 163 +                               spi-max-frequency = <10000000>;
 164 +
 165 +                               partitions {
 166 +                                       compatible = "fixed-partitions";
 167 +                                       #address-cells = <1>;
 168 +                                       #size-cells = <1>;
 169 +
 170 +                                       partition@0 {
 171 +                                               label = "bl2";
 172 +                                               reg = <0x0 0x20000>;
 173 +                                               read-only;
 174 +                                       };
 175 +
 176 +                                       partition@20000 {
 177 +                                               label = "reserved";
 178 +                                               reg = <0x20000 0x20000>;
 179 +                                       };
 180 +
 181 +                                       partition@40000 {
 182 +                                               label = "u-boot-env";
 183 +                                               reg = <0x40000 0x40000>;
 184 +                                       };
 185 +
 186 +                                       partition@80000 {
 187 +                                               label = "reserved2";
 188 +                                               reg = <0x80000 0x80000>;
 189 +                                       };
 190 +
 191 +                                       partition@100000 {
 192 +                                               label = "fip";
 193 +                                               reg = <0x100000 0x80000>;
 194 +                                               read-only;
 195 +                                       };
 196 +
 197 +                                       partition@180000 {
 198 +                                               label = "recovery";
 199 +                                               reg = <0x180000 0xa80000>;
 200 +                                       };
 201 +
 202 +                                       partition@c00000 {
 203 +                                               label = "fit";
 204 +                                               reg = <0xc00000 0x1400000>;
 205 +                                       };
 206 +                               };
 207 +                       };
 208 +               };
 209 +       };
 210 +};
 211 --- /dev/null
 212 +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
 213 @@ -0,0 +1,23 @@
 214 +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
 215 +/*
 216 + * Copyright (C) 2021 MediaTek Inc.
 217 + * Author: Sam.Shih <sam.shih@mediatek.com>
 218 + */
 219 +
 220 +/dts-v1/;
 221 +/plugin/;
 222 +
 223 +/ {
 224 +       compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
 225 +
 226 +       fragment@0 {
 227 +               target-path = "/soc/mmc@11230000";
 228 +               __overlay__ {
 229 +                       bus-width = <4>;
 230 +                       max-frequency = <52000000>;
 231 +                       cap-sd-highspeed;
 232 +                       status = "okay";
 233 +               };
 234 +       };
 235 +};
 236 +
 237 --- /dev/null
 238 +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
 239 @@ -0,0 +1,450 @@
 240 +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
 241 +/*
 242 + * Copyright (C) 2021 MediaTek Inc.
 243 + * Authors: Sam.Shih <sam.shih@mediatek.com>
 244 + *          Frank Wunderlich <frank-w@public-files.de>
 245 + *          Daniel Golle <daniel@makrotopia.org>
 246 + */
 247 +
 248 +/dts-v1/;
 249 +#include <dt-bindings/gpio/gpio.h>
 250 +#include <dt-bindings/input/input.h>
 251 +#include <dt-bindings/leds/common.h>
 252 +#include <dt-bindings/pinctrl/mt65xx.h>
 253 +
 254 +#include "mt7986a.dtsi"
 255 +
 256 +/ {
 257 +       model = "Bananapi BPI-R3";
 258 +       compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
 259 +
 260 +       aliases {
 261 +               serial0 = &uart0;
 262 +               ethernet0 = &gmac0;
 263 +               ethernet1 = &gmac1;
 264 +       };
 265 +
 266 +       chosen {
 267 +               stdout-path = "serial0:115200n8";
 268 +       };
 269 +
 270 +       dcin: regulator-12vd {
 271 +               compatible = "regulator-fixed";
 272 +               regulator-name = "12vd";
 273 +               regulator-min-microvolt = <12000000>;
 274 +               regulator-max-microvolt = <12000000>;
 275 +               regulator-boot-on;
 276 +               regulator-always-on;
 277 +       };
 278 +
 279 +       gpio-keys {
 280 +               compatible = "gpio-keys";
 281 +
 282 +               reset-key {
 283 +                       label = "reset";
 284 +                       linux,code = <KEY_RESTART>;
 285 +                       gpios = <&pio 9 GPIO_ACTIVE_LOW>;
 286 +               };
 287 +
 288 +               wps-key {
 289 +                       label = "wps";
 290 +                       linux,code = <KEY_WPS_BUTTON>;
 291 +                       gpios = <&pio 10 GPIO_ACTIVE_LOW>;
 292 +               };
 293 +       };
 294 +
 295 +       /* i2c of the left SFP cage (wan) */
 296 +       i2c_sfp1: i2c-gpio-0 {
 297 +               compatible = "i2c-gpio";
 298 +               sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 299 +               scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 300 +               i2c-gpio,delay-us = <2>;
 301 +               #address-cells = <1>;
 302 +               #size-cells = <0>;
 303 +       };
 304 +
 305 +       /* i2c of the right SFP cage (lan) */
 306 +       i2c_sfp2: i2c-gpio-1 {
 307 +               compatible = "i2c-gpio";
 308 +               sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 309 +               scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 310 +               i2c-gpio,delay-us = <2>;
 311 +               #address-cells = <1>;
 312 +               #size-cells = <0>;
 313 +       };
 314 +
 315 +       leds {
 316 +               compatible = "gpio-leds";
 317 +
 318 +               green_led: led-0 {
 319 +                       color = <LED_COLOR_ID_GREEN>;
 320 +                       function = LED_FUNCTION_POWER;
 321 +                       gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
 322 +                       default-state = "on";
 323 +               };
 324 +
 325 +               blue_led: led-1 {
 326 +                       color = <LED_COLOR_ID_BLUE>;
 327 +                       function = LED_FUNCTION_STATUS;
 328 +                       gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
 329 +                       default-state = "off";
 330 +               };
 331 +       };
 332 +
 333 +       reg_1p8v: regulator-1p8v {
 334 +               compatible = "regulator-fixed";
 335 +               regulator-name = "1.8vd";
 336 +               regulator-min-microvolt = <1800000>;
 337 +               regulator-max-microvolt = <1800000>;
 338 +               regulator-boot-on;
 339 +               regulator-always-on;
 340 +               vin-supply = <&dcin>;
 341 +       };
 342 +
 343 +       reg_3p3v: regulator-3p3v {
 344 +               compatible = "regulator-fixed";
 345 +               regulator-name = "3.3vd";
 346 +               regulator-min-microvolt = <3300000>;
 347 +               regulator-max-microvolt = <3300000>;
 348 +               regulator-boot-on;
 349 +               regulator-always-on;
 350 +               vin-supply = <&dcin>;
 351 +       };
 352 +
 353 +       /* left SFP cage (wan) */
 354 +       sfp1: sfp-1 {
 355 +               compatible = "sff,sfp";
 356 +               i2c-bus = <&i2c_sfp1>;
 357 +               los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
 358 +               mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
 359 +               tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
 360 +               tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
 361 +       };
 362 +
 363 +       /* right SFP cage (lan) */
 364 +       sfp2: sfp-2 {
 365 +               compatible = "sff,sfp";
 366 +               i2c-bus = <&i2c_sfp2>;
 367 +               los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
 368 +               mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
 369 +               tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
 370 +               tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
 371 +       };
 372 +};
 373 +
 374 +&crypto {
 375 +       status = "okay";
 376 +};
 377 +
 378 +&eth {
 379 +       status = "okay";
 380 +
 381 +       gmac0: mac@0 {
 382 +               compatible = "mediatek,eth-mac";
 383 +               reg = <0>;
 384 +               phy-mode = "2500base-x";
 385 +
 386 +               fixed-link {
 387 +                       speed = <2500>;
 388 +                       full-duplex;
 389 +                       pause;
 390 +               };
 391 +       };
 392 +
 393 +       gmac1: mac@1 {
 394 +               compatible = "mediatek,eth-mac";
 395 +               reg = <1>;
 396 +               phy-mode = "2500base-x";
 397 +               sfp = <&sfp1>;
 398 +               managed = "in-band-status";
 399 +       };
 400 +
 401 +       mdio: mdio-bus {
 402 +               #address-cells = <1>;
 403 +               #size-cells = <0>;
 404 +       };
 405 +};
 406 +
 407 +&mdio {
 408 +       switch: switch@31 {
 409 +               compatible = "mediatek,mt7531";
 410 +               reg = <31>;
 411 +               interrupt-controller;
 412 +               #interrupt-cells = <1>;
 413 +               interrupt-parent = <&pio>;
 414 +               interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
 415 +               reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
 416 +       };
 417 +};
 418 +
 419 +&mmc0 {
 420 +       pinctrl-names = "default", "state_uhs";
 421 +       pinctrl-0 = <&mmc0_pins_default>;
 422 +       pinctrl-1 = <&mmc0_pins_uhs>;
 423 +       vmmc-supply = <&reg_3p3v>;
 424 +       vqmmc-supply = <&reg_1p8v>;
 425 +};
 426 +
 427 +&i2c0 {
 428 +       pinctrl-names = "default";
 429 +       pinctrl-0 = <&i2c_pins>;
 430 +       status = "okay";
 431 +};
 432 +
 433 +&pcie {
 434 +       pinctrl-names = "default";
 435 +       pinctrl-0 = <&pcie_pins>;
 436 +       status = "okay";
 437 +};
 438 +
 439 +&pcie_phy {
 440 +       status = "okay";
 441 +};
 442 +
 443 +&pio {
 444 +       i2c_pins: i2c-pins {
 445 +               mux {
 446 +                       function = "i2c";
 447 +                       groups = "i2c";
 448 +               };
 449 +       };
 450 +
 451 +       mmc0_pins_default: mmc0-pins {
 452 +               mux {
 453 +                       function = "emmc";
 454 +                       groups = "emmc_51";
 455 +               };
 456 +               conf-cmd-dat {
 457 +                       pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
 458 +                              "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
 459 +                              "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
 460 +                       input-enable;
 461 +                       drive-strength = <4>;
 462 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
 463 +               };
 464 +               conf-clk {
 465 +                       pins = "EMMC_CK";
 466 +                       drive-strength = <6>;
 467 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
 468 +               };
 469 +               conf-ds {
 470 +                       pins = "EMMC_DSL";
 471 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
 472 +               };
 473 +               conf-rst {
 474 +                       pins = "EMMC_RSTB";
 475 +                       drive-strength = <4>;
 476 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
 477 +               };
 478 +       };
 479 +
 480 +       mmc0_pins_uhs: mmc0-uhs-pins {
 481 +               mux {
 482 +                       function = "emmc";
 483 +                       groups = "emmc_51";
 484 +               };
 485 +               conf-cmd-dat {
 486 +                       pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
 487 +                              "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
 488 +                              "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
 489 +                       input-enable;
 490 +                       drive-strength = <4>;
 491 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
 492 +               };
 493 +               conf-clk {
 494 +                       pins = "EMMC_CK";
 495 +                       drive-strength = <6>;
 496 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
 497 +               };
 498 +               conf-ds {
 499 +                       pins = "EMMC_DSL";
 500 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
 501 +               };
 502 +               conf-rst {
 503 +                       pins = "EMMC_RSTB";
 504 +                       drive-strength = <4>;
 505 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
 506 +               };
 507 +       };
 508 +
 509 +       pcie_pins: pcie-pins {
 510 +               mux {
 511 +                       function = "pcie";
 512 +                       groups = "pcie_clk", "pcie_pereset";
 513 +               };
 514 +       };
 515 +
 516 +       spi_flash_pins: spi-flash-pins {
 517 +               mux {
 518 +                       function = "spi";
 519 +                       groups = "spi0", "spi0_wp_hold";
 520 +               };
 521 +       };
 522 +
 523 +       spic_pins: spic-pins {
 524 +               mux {
 525 +                       function = "spi";
 526 +                       groups = "spi1_0";
 527 +               };
 528 +       };
 529 +
 530 +       uart1_pins: uart1-pins {
 531 +               mux {
 532 +                       function = "uart";
 533 +                       groups = "uart1_rx_tx";
 534 +               };
 535 +       };
 536 +
 537 +       uart2_pins: uart2-pins {
 538 +               mux {
 539 +                       function = "uart";
 540 +                       groups = "uart2_0_rx_tx";
 541 +               };
 542 +       };
 543 +
 544 +       wf_2g_5g_pins: wf-2g-5g-pins {
 545 +               mux {
 546 +                       function = "wifi";
 547 +                       groups = "wf_2g", "wf_5g";
 548 +               };
 549 +               conf {
 550 +                       pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 551 +                              "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 552 +                              "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 553 +                              "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 554 +                              "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 555 +                              "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 556 +                              "WF1_TOP_CLK", "WF1_TOP_DATA";
 557 +                       drive-strength = <4>;
 558 +               };
 559 +       };
 560 +
 561 +       wf_dbdc_pins: wf-dbdc-pins {
 562 +               mux {
 563 +                       function = "wifi";
 564 +                       groups = "wf_dbdc";
 565 +               };
 566 +               conf {
 567 +                       pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 568 +                              "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 569 +                              "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 570 +                              "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 571 +                              "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 572 +                              "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 573 +                              "WF1_TOP_CLK", "WF1_TOP_DATA";
 574 +                       drive-strength = <4>;
 575 +               };
 576 +       };
 577 +
 578 +       wf_led_pins: wf-led-pins {
 579 +               mux {
 580 +                       function = "led";
 581 +                       groups = "wifi_led";
 582 +               };
 583 +       };
 584 +};
 585 +
 586 +&spi0 {
 587 +       pinctrl-names = "default";
 588 +       pinctrl-0 = <&spi_flash_pins>;
 589 +       status = "okay";
 590 +};
 591 +
 592 +&spi1 {
 593 +       pinctrl-names = "default";
 594 +       pinctrl-0 = <&spic_pins>;
 595 +       status = "okay";
 596 +};
 597 +
 598 +&ssusb {
 599 +       status = "okay";
 600 +};
 601 +
 602 +&switch {
 603 +       ports {
 604 +               #address-cells = <1>;
 605 +               #size-cells = <0>;
 606 +
 607 +               port@0 {
 608 +                       reg = <0>;
 609 +                       label = "wan";
 610 +               };
 611 +
 612 +               port@1 {
 613 +                       reg = <1>;
 614 +                       label = "lan0";
 615 +               };
 616 +
 617 +               port@2 {
 618 +                       reg = <2>;
 619 +                       label = "lan1";
 620 +               };
 621 +
 622 +               port@3 {
 623 +                       reg = <3>;
 624 +                       label = "lan2";
 625 +               };
 626 +
 627 +               port@4 {
 628 +                       reg = <4>;
 629 +                       label = "lan3";
 630 +               };
 631 +
 632 +               port5: port@5 {
 633 +                       reg = <5>;
 634 +                       label = "lan4";
 635 +                       phy-mode = "2500base-x";
 636 +                       sfp = <&sfp2>;
 637 +                       managed = "in-band-status";
 638 +               };
 639 +
 640 +               port@6 {
 641 +                       reg = <6>;
 642 +                       label = "cpu";
 643 +                       ethernet = <&gmac0>;
 644 +                       phy-mode = "2500base-x";
 645 +
 646 +                       fixed-link {
 647 +                               speed = <2500>;
 648 +                               full-duplex;
 649 +                               pause;
 650 +                       };
 651 +               };
 652 +       };
 653 +};
 654 +
 655 +&trng {
 656 +       status = "okay";
 657 +};
 658 +
 659 +&uart0 {
 660 +       status = "okay";
 661 +};
 662 +
 663 +&uart1 {
 664 +       pinctrl-names = "default";
 665 +       pinctrl-0 = <&uart1_pins>;
 666 +       status = "okay";
 667 +};
 668 +
 669 +&uart2 {
 670 +       pinctrl-names = "default";
 671 +       pinctrl-0 = <&uart2_pins>;
 672 +       status = "okay";
 673 +};
 674 +
 675 +&usb_phy {
 676 +       status = "okay";
 677 +};
 678 +
 679 +&watchdog {
 680 +       status = "okay";
 681 +};
 682 +
 683 +&wifi {
 684 +       status = "okay";
 685 +       pinctrl-names = "default", "dbdc";
 686 +       pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
 687 +       pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
 688 +};
 689 +