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kernel: update 4.4 to 4.4.83
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.9 / 0092-dsa5.patch
1 From patchwork Wed Mar 29 09:38:23 2017
2 Content-Type: text/plain; charset="utf-8"
3 MIME-Version: 1.0
4 Content-Transfer-Encoding: 7bit
5 Subject: [net-next, v3,
6 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch
7 From: sean.wang@mediatek.com
8 X-Patchwork-Id: 9651095
9 Message-Id: <1490780303-18598-6-git-send-email-sean.wang@mediatek.com>
10 To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
11 <vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
12 <robh+dt@kernel.org>, <mark.rutland@arm.com>
13 Cc: devicetree@vger.kernel.org, Landen.Chao@mediatek.com, keyhaede@gmail.com,
14 netdev@vger.kernel.org, sean.wang@mediatek.com,
15 linux-kernel@vger.kernel.org,
16 linux-mediatek@lists.infradead.org, objelf@gmail.com, davem@davemloft.net
17 Date: Wed, 29 Mar 2017 17:38:23 +0800
18
19 From: Sean Wang <sean.wang@mediatek.com>
20
21 MT7530 is a 7-ports Gigabit Ethernet Switch that could be found on
22 Mediatek router platforms such as MT7623A or MT7623N platform which
23 includes 7-port Gigabit Ethernet MAC and 5-port Gigabit Ethernet PHY.
24 Among these ports, The port from 0 to 4 are the user ports connecting
25 with the remote devices while the port 5 and 6 are the CPU ports
26 connecting into Mediatek Ethernet GMAC.
27
28 For port 6, it can communicate with the CPU via Mediatek Ethernet GMAC
29 through either the TRGMII or RGMII which could be controlled by phy-mode
30 in the dt-bindings to specify which mode is preferred to use. And for
31 port 5, only RGMII can be specified. However, currently, only port 6 is
32 being supported in this DSA driver.
33
34 The driver is made with the reference to qca8k and other existing DSA
35 driver. The most of the essential callbacks of the DSA are already
36 support in the driver, including tag insert for user port distinguishing,
37 port control, bridge offloading, STP setup and ethtool operation to allow
38 DSA to model each user port into a standalone netdevice as the other DSA
39 driver had done.
40
41 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
42 Signed-off-by: Landen Chao <Landen.Chao@mediatek.com>
43 ---
44 drivers/net/dsa/Kconfig | 8 +
45 drivers/net/dsa/Makefile | 2 +-
46 drivers/net/dsa/mt7530.c | 1126 ++++++++++++++++++++++++++++++++++++++++++++++
47 drivers/net/dsa/mt7530.h | 390 ++++++++++++++++
48 4 files changed, 1525 insertions(+), 1 deletion(-)
49 create mode 100644 drivers/net/dsa/mt7530.c
50 create mode 100644 drivers/net/dsa/mt7530.h
51
52 --- a/drivers/net/dsa/Kconfig
53 +++ b/drivers/net/dsa/Kconfig
54 @@ -34,4 +34,12 @@ config NET_DSA_QCA8K
55 This enables support for the Qualcomm Atheros QCA8K Ethernet
56 switch chips.
57
58 +config NET_DSA_MT7530
59 + tristate "Mediatek MT7530 Ethernet switch support"
60 + depends on NET_DSA
61 + select NET_DSA_TAG_MTK
62 + ---help---
63 + This enables support for the Mediatek MT7530 Ethernet switch
64 + chip.
65 +
66 endmenu
67 --- a/drivers/net/dsa/Makefile
68 +++ b/drivers/net/dsa/Makefile
69 @@ -1,6 +1,6 @@
70 obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
71 obj-$(CONFIG_NET_DSA_BCM_SF2) += bcm_sf2.o
72 obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o
73 -
74 +obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
75 obj-y += b53/
76 obj-y += mv88e6xxx/
77 --- /dev/null
78 +++ b/drivers/net/dsa/mt7530.c
79 @@ -0,0 +1,1126 @@
80 +/*
81 + * Mediatek MT7530 DSA Switch driver
82 + * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
83 + *
84 + * This program is free software; you can redistribute it and/or modify
85 + * it under the terms of the GNU General Public License version 2 as
86 + * published by the Free Software Foundation.
87 + *
88 + * This program is distributed in the hope that it will be useful,
89 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
90 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
91 + * GNU General Public License for more details.
92 + */
93 +#include <linux/etherdevice.h>
94 +#include <linux/if_bridge.h>
95 +#include <linux/iopoll.h>
96 +#include <linux/mdio.h>
97 +#include <linux/mfd/syscon.h>
98 +#include <linux/module.h>
99 +#include <linux/netdevice.h>
100 +#include <linux/of_gpio.h>
101 +#include <linux/of_mdio.h>
102 +#include <linux/of_net.h>
103 +#include <linux/of_platform.h>
104 +#include <linux/phy.h>
105 +#include <linux/regmap.h>
106 +#include <linux/regulator/consumer.h>
107 +#include <linux/reset.h>
108 +#include <net/dsa.h>
109 +#include <net/switchdev.h>
110 +
111 +#include "mt7530.h"
112 +
113 +/* String, offset, and register size in bytes if different from 4 bytes */
114 +static const struct mt7530_mib_desc mt7530_mib[] = {
115 + MIB_DESC(1, 0x00, "TxDrop"),
116 + MIB_DESC(1, 0x04, "TxCrcErr"),
117 + MIB_DESC(1, 0x08, "TxUnicast"),
118 + MIB_DESC(1, 0x0c, "TxMulticast"),
119 + MIB_DESC(1, 0x10, "TxBroadcast"),
120 + MIB_DESC(1, 0x14, "TxCollision"),
121 + MIB_DESC(1, 0x18, "TxSingleCollision"),
122 + MIB_DESC(1, 0x1c, "TxMultipleCollision"),
123 + MIB_DESC(1, 0x20, "TxDeferred"),
124 + MIB_DESC(1, 0x24, "TxLateCollision"),
125 + MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
126 + MIB_DESC(1, 0x2c, "TxPause"),
127 + MIB_DESC(1, 0x30, "TxPktSz64"),
128 + MIB_DESC(1, 0x34, "TxPktSz65To127"),
129 + MIB_DESC(1, 0x38, "TxPktSz128To255"),
130 + MIB_DESC(1, 0x3c, "TxPktSz256To511"),
131 + MIB_DESC(1, 0x40, "TxPktSz512To1023"),
132 + MIB_DESC(1, 0x44, "Tx1024ToMax"),
133 + MIB_DESC(2, 0x48, "TxBytes"),
134 + MIB_DESC(1, 0x60, "RxDrop"),
135 + MIB_DESC(1, 0x64, "RxFiltering"),
136 + MIB_DESC(1, 0x6c, "RxMulticast"),
137 + MIB_DESC(1, 0x70, "RxBroadcast"),
138 + MIB_DESC(1, 0x74, "RxAlignErr"),
139 + MIB_DESC(1, 0x78, "RxCrcErr"),
140 + MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
141 + MIB_DESC(1, 0x80, "RxFragErr"),
142 + MIB_DESC(1, 0x84, "RxOverSzErr"),
143 + MIB_DESC(1, 0x88, "RxJabberErr"),
144 + MIB_DESC(1, 0x8c, "RxPause"),
145 + MIB_DESC(1, 0x90, "RxPktSz64"),
146 + MIB_DESC(1, 0x94, "RxPktSz65To127"),
147 + MIB_DESC(1, 0x98, "RxPktSz128To255"),
148 + MIB_DESC(1, 0x9c, "RxPktSz256To511"),
149 + MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
150 + MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
151 + MIB_DESC(2, 0xa8, "RxBytes"),
152 + MIB_DESC(1, 0xb0, "RxCtrlDrop"),
153 + MIB_DESC(1, 0xb4, "RxIngressDrop"),
154 + MIB_DESC(1, 0xb8, "RxArlDrop"),
155 +};
156 +
157 +static struct mt7530_priv *lpriv;
158 +static void mt7530_port_disable(struct dsa_switch *ds, int port,
159 + struct phy_device *phy);
160 +static int mt7530_cpu_port_enable(struct mt7530_priv *priv,
161 + int port);
162 +
163 +static int
164 +mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val)
165 +{
166 + int ret;
167 +
168 + ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val);
169 + if (ret < 0)
170 + dev_err(priv->dev,
171 + "failed to priv write register\n");
172 + return ret;
173 +}
174 +
175 +static u32
176 +mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg)
177 +{
178 + int ret;
179 + u32 val;
180 +
181 + ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val);
182 + if (ret < 0) {
183 + dev_err(priv->dev,
184 + "failed to priv read register\n");
185 + return ret;
186 + }
187 +
188 + return val;
189 +}
190 +
191 +static void
192 +mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg,
193 + u32 mask, u32 set)
194 +{
195 + u32 val;
196 +
197 + val = mt7623_trgmii_read(priv, reg);
198 + val &= ~mask;
199 + val |= set;
200 + mt7623_trgmii_write(priv, reg, val);
201 +}
202 +
203 +static void
204 +mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val)
205 +{
206 + mt7623_trgmii_rmw(priv, reg, 0, val);
207 +}
208 +
209 +static void
210 +mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val)
211 +{
212 + mt7623_trgmii_rmw(priv, reg, val, 0);
213 +}
214 +
215 +static int
216 +core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
217 +{
218 + struct mii_bus *bus = priv->bus;
219 + int value, ret;
220 +
221 + /* Write the desired MMD Devad */
222 + ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
223 + if (ret < 0)
224 + goto err;
225 +
226 + /* Write the desired MMD register address */
227 + ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
228 + if (ret < 0)
229 + goto err;
230 +
231 + /* Select the Function : DATA with no post increment */
232 + ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
233 + if (ret < 0)
234 + goto err;
235 +
236 + /* Read the content of the MMD's selected register */
237 + value = bus->read(bus, 0, MII_MMD_DATA);
238 +
239 + return value;
240 +err:
241 + dev_err(&bus->dev, "failed to read mmd register\n");
242 +
243 + return ret;
244 +}
245 +
246 +static int
247 +core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
248 + int devad, u32 data)
249 +{
250 + struct mii_bus *bus = priv->bus;
251 + int ret;
252 +
253 + /* Write the desired MMD Devad */
254 + ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
255 + if (ret < 0)
256 + goto err;
257 +
258 + /* Write the desired MMD register address */
259 + ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
260 + if (ret < 0)
261 + goto err;
262 +
263 + /* Select the Function : DATA with no post increment */
264 + ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
265 + if (ret < 0)
266 + goto err;
267 +
268 + /* Write the data into MMD's selected register */
269 + ret = bus->write(bus, 0, MII_MMD_DATA, data);
270 +err:
271 + if (ret < 0)
272 + dev_err(&bus->dev,
273 + "failed to write mmd register\n");
274 + return ret;
275 +}
276 +
277 +static void
278 +core_write(struct mt7530_priv *priv, u32 reg, u32 val)
279 +{
280 + struct mii_bus *bus = priv->bus;
281 +
282 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
283 +
284 + core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
285 +
286 + mutex_unlock(&bus->mdio_lock);
287 +}
288 +
289 +static void
290 +core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
291 +{
292 + struct mii_bus *bus = priv->bus;
293 + u32 val;
294 +
295 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
296 +
297 + val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
298 + val &= ~mask;
299 + val |= set;
300 + core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
301 +
302 + mutex_unlock(&bus->mdio_lock);
303 +}
304 +
305 +static void
306 +core_set(struct mt7530_priv *priv, u32 reg, u32 val)
307 +{
308 + core_rmw(priv, reg, 0, val);
309 +}
310 +
311 +static void
312 +core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
313 +{
314 + core_rmw(priv, reg, val, 0);
315 +}
316 +
317 +static int
318 +mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
319 +{
320 + struct mii_bus *bus = priv->bus;
321 + u16 page, r, lo, hi;
322 + int ret;
323 +
324 + page = (reg >> 6) & 0x3ff;
325 + r = (reg >> 2) & 0xf;
326 + lo = val & 0xffff;
327 + hi = val >> 16;
328 +
329 + /* MT7530 uses 31 as the pseudo port */
330 + ret = bus->write(bus, 0x1f, 0x1f, page);
331 + if (ret < 0)
332 + goto err;
333 +
334 + ret = bus->write(bus, 0x1f, r, lo);
335 + if (ret < 0)
336 + goto err;
337 +
338 + ret = bus->write(bus, 0x1f, 0x10, hi);
339 +err:
340 + if (ret < 0)
341 + dev_err(&bus->dev,
342 + "failed to write mt7530 register\n");
343 + return ret;
344 +}
345 +
346 +static u32
347 +mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
348 +{
349 + struct mii_bus *bus = priv->bus;
350 + u16 page, r, lo, hi;
351 + int ret;
352 +
353 + page = (reg >> 6) & 0x3ff;
354 + r = (reg >> 2) & 0xf;
355 +
356 + /* MT7530 uses 31 as the pseudo port */
357 + ret = bus->write(bus, 0x1f, 0x1f, page);
358 + if (ret < 0) {
359 + dev_err(&bus->dev,
360 + "failed to read mt7530 register\n");
361 + return ret;
362 + }
363 +
364 + lo = bus->read(bus, 0x1f, r);
365 + hi = bus->read(bus, 0x1f, 0x10);
366 +
367 + return (hi << 16) | (lo & 0xffff);
368 +}
369 +
370 +static void
371 +mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
372 +{
373 + struct mii_bus *bus = priv->bus;
374 +
375 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
376 +
377 + mt7530_mii_write(priv, reg, val);
378 +
379 + mutex_unlock(&bus->mdio_lock);
380 +}
381 +
382 +static u32
383 +_mt7530_read(u32 reg)
384 +{
385 + struct mt7530_priv *priv = lpriv;
386 + struct mii_bus *bus = priv->bus;
387 + u32 val;
388 +
389 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
390 +
391 + val = mt7530_mii_read(priv, reg);
392 +
393 + mutex_unlock(&bus->mdio_lock);
394 +
395 + return val;
396 +}
397 +
398 +static u32
399 +mt7530_read(struct mt7530_priv *priv, u32 reg)
400 +{
401 + return _mt7530_read(reg);
402 +}
403 +
404 +static void
405 +mt7530_rmw(struct mt7530_priv *priv, u32 reg,
406 + u32 mask, u32 set)
407 +{
408 + struct mii_bus *bus = priv->bus;
409 + u32 val;
410 +
411 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
412 +
413 + val = mt7530_mii_read(priv, reg);
414 + val &= ~mask;
415 + val |= set;
416 + mt7530_mii_write(priv, reg, val);
417 +
418 + mutex_unlock(&bus->mdio_lock);
419 +}
420 +
421 +static void
422 +mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
423 +{
424 + mt7530_rmw(priv, reg, 0, val);
425 +}
426 +
427 +static void
428 +mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
429 +{
430 + mt7530_rmw(priv, reg, val, 0);
431 +}
432 +
433 +static int
434 +mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
435 +{
436 + u32 val;
437 + int ret;
438 +
439 + /* Set the command operating upon the MAC address entries */
440 + val = ATC_BUSY | ATC_MAT(0) | cmd;
441 + mt7530_write(priv, MT7530_ATC, val);
442 +
443 + ret = readx_poll_timeout(_mt7530_read, MT7530_ATC, val,
444 + !(val & ATC_BUSY), 20, 20000);
445 + if (ret < 0) {
446 + dev_err(priv->dev, "reset timeout\n");
447 + return ret;
448 + }
449 +
450 + /* Additional sanity for read command if the specified
451 + * entry is invalid
452 + */
453 + val = mt7530_read(priv, MT7530_ATC);
454 + if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
455 + return -EINVAL;
456 +
457 + if (rsp)
458 + *rsp = val;
459 +
460 + return 0;
461 +}
462 +
463 +static void
464 +mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
465 +{
466 + u32 reg[3];
467 + int i;
468 +
469 + /* Read from ARL table into an array */
470 + for (i = 0; i < 3; i++) {
471 + reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
472 +
473 + dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
474 + __func__, __LINE__, i, reg[i]);
475 + }
476 +
477 + fdb->vid = (reg[1] >> CVID) & CVID_MASK;
478 + fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
479 + fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
480 + fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
481 + fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
482 + fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
483 + fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
484 + fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
485 + fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
486 + fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
487 +}
488 +
489 +static void
490 +mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
491 + u8 port_mask, const u8 *mac,
492 + u8 aging, u8 type)
493 +{
494 + u32 reg[3] = { 0 };
495 + int i;
496 +
497 + reg[1] |= vid & CVID_MASK;
498 + reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
499 + reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
500 + /* STATIC_ENT indicate that entry is static wouldn't
501 + * be aged out and STATIC_EMP specified as erasing an
502 + * entry
503 + */
504 + reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
505 + reg[1] |= mac[5] << MAC_BYTE_5;
506 + reg[1] |= mac[4] << MAC_BYTE_4;
507 + reg[0] |= mac[3] << MAC_BYTE_3;
508 + reg[0] |= mac[2] << MAC_BYTE_2;
509 + reg[0] |= mac[1] << MAC_BYTE_1;
510 + reg[0] |= mac[0] << MAC_BYTE_0;
511 +
512 + /* Write array into the ARL table */
513 + for (i = 0; i < 3; i++)
514 + mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
515 +}
516 +
517 +static int
518 +mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
519 +{
520 + struct mt7530_priv *priv = ds->priv;
521 + u32 ncpo1, ssc_delta, trgint, i;
522 +
523 + switch (mode) {
524 + case PHY_INTERFACE_MODE_RGMII:
525 + trgint = 0;
526 + ncpo1 = 0x0c80;
527 + ssc_delta = 0x87;
528 + break;
529 + case PHY_INTERFACE_MODE_TRGMII:
530 + trgint = 1;
531 + ncpo1 = 0x1400;
532 + ssc_delta = 0x57;
533 + break;
534 + default:
535 + dev_err(priv->dev, "xMII mode %d not supported\n", mode);
536 + return -EINVAL;
537 + }
538 +
539 + mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
540 + P6_INTF_MODE(trgint));
541 +
542 + /* Lower Tx Driving for TRGMII path */
543 + for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
544 + mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
545 + TD_DM_DRVP(8) | TD_DM_DRVN(8));
546 +
547 + /* Setup core clock for MT7530 */
548 + if (!trgint) {
549 + /* Disable MT7530 core clock */
550 + core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
551 +
552 + /* Disable PLL, since phy_device has not yet been created
553 + * provided for phy_[read,write]_mmd_indirect is called, we
554 + * provide our own core_write_mmd_indirect to complete this
555 + * function.
556 + */
557 + core_write_mmd_indirect(priv,
558 + CORE_GSWPLL_GRP1,
559 + MDIO_MMD_VEND2,
560 + 0);
561 +
562 + /* Set core clock into 500Mhz */
563 + core_write(priv, CORE_GSWPLL_GRP2,
564 + RG_GSWPLL_POSDIV_500M(1) |
565 + RG_GSWPLL_FBKDIV_500M(25));
566 +
567 + /* Enable PLL */
568 + core_write(priv, CORE_GSWPLL_GRP1,
569 + RG_GSWPLL_EN_PRE |
570 + RG_GSWPLL_POSDIV_200M(2) |
571 + RG_GSWPLL_FBKDIV_200M(32));
572 +
573 + /* Enable MT7530 core clock */
574 + core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
575 + }
576 +
577 + /* Setup the MT7530 TRGMII Tx Clock */
578 + core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
579 + core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
580 + core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
581 + core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
582 + core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
583 + core_write(priv, CORE_PLL_GROUP4,
584 + RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
585 + RG_SYSPLL_BIAS_LPF_EN);
586 + core_write(priv, CORE_PLL_GROUP2,
587 + RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
588 + RG_SYSPLL_POSDIV(1));
589 + core_write(priv, CORE_PLL_GROUP7,
590 + RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
591 + RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
592 + core_set(priv, CORE_TRGMII_GSW_CLK_CG,
593 + REG_GSWCK_EN | REG_TRGMIICK_EN);
594 +
595 + if (!trgint)
596 + for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
597 + mt7530_rmw(priv, MT7530_TRGMII_RD(i),
598 + RD_TAP_MASK, RD_TAP(16));
599 + else
600 + mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII);
601 +
602 + return 0;
603 +}
604 +
605 +static int
606 +mt7623_pad_clk_setup(struct dsa_switch *ds)
607 +{
608 + struct mt7530_priv *priv = ds->priv;
609 + int i;
610 +
611 + for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
612 + mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i),
613 + TD_DM_DRVP(8) | TD_DM_DRVN(8));
614 +
615 + mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL);
616 + mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST);
617 +
618 + return 0;
619 +}
620 +
621 +static void
622 +mt7530_mib_reset(struct dsa_switch *ds)
623 +{
624 + struct mt7530_priv *priv = ds->priv;
625 +
626 + mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
627 + mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
628 +}
629 +
630 +static void
631 +mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable)
632 +{
633 + u32 mask = PMCR_TX_EN | PMCR_RX_EN;
634 +
635 + if (enable)
636 + mt7530_set(priv, MT7530_PMCR_P(port), mask);
637 + else
638 + mt7530_clear(priv, MT7530_PMCR_P(port), mask);
639 +}
640 +
641 +static int
642 +mt7530_setup(struct dsa_switch *ds)
643 +{
644 + struct mt7530_priv *priv = ds->priv;
645 + int ret, i;
646 + u32 id, val;
647 + struct device_node *dn;
648 +
649 + /* The parent node of master_netdev which holds the common system
650 + * controller also is the container for two GMACs nodes representing
651 + * as two netdev instances.
652 + */
653 + dn = ds->master_netdev->dev.of_node->parent;
654 + priv->ethernet = syscon_node_to_regmap(dn);
655 + if (IS_ERR(priv->ethernet))
656 + return PTR_ERR(priv->ethernet);
657 +
658 + regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
659 + ret = regulator_enable(priv->core_pwr);
660 + if (ret < 0) {
661 + dev_err(priv->dev,
662 + "Failed to enable core power: %d\n", ret);
663 + return ret;
664 + }
665 +
666 + regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
667 + ret = regulator_enable(priv->io_pwr);
668 + if (ret < 0) {
669 + dev_err(priv->dev, "Failed to enable io pwr: %d\n",
670 + ret);
671 + return ret;
672 + }
673 +
674 + /* Reset whole chip through gpio pin or memory-mapped registers for
675 + * different type of hardware
676 + */
677 + if (priv->mcm) {
678 + reset_control_assert(priv->rstc);
679 + usleep_range(1000, 1100);
680 + reset_control_deassert(priv->rstc);
681 + } else {
682 + gpiod_set_value_cansleep(priv->reset, 0);
683 + usleep_range(1000, 1100);
684 + gpiod_set_value_cansleep(priv->reset, 1);
685 + }
686 +
687 + /* Waiting for MT7530 got to stable */
688 + ret = readx_poll_timeout(_mt7530_read, MT7530_HWTRAP, val, val != 0,
689 + 20, 1000000);
690 + if (ret < 0) {
691 + dev_err(priv->dev, "reset timeout\n");
692 + return ret;
693 + }
694 +
695 + id = mt7530_read(priv, MT7530_CREV);
696 + id >>= CHIP_NAME_SHIFT;
697 + if (id != MT7530_ID) {
698 + dev_err(priv->dev, "chip %x can't be supported\n", id);
699 + return -ENODEV;
700 + }
701 +
702 + /* Reset the switch through internal reset */
703 + mt7530_write(priv, MT7530_SYS_CTRL,
704 + SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
705 + SYS_CTRL_REG_RST);
706 +
707 + /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
708 + val = mt7530_read(priv, MT7530_MHWTRAP);
709 + val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
710 + val |= MHWTRAP_MANUAL;
711 + mt7530_write(priv, MT7530_MHWTRAP, val);
712 +
713 + /* Enable and reset MIB counters */
714 + mt7530_mib_reset(ds);
715 +
716 + mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK);
717 +
718 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
719 + /* Disable forwarding by default on all ports */
720 + mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
721 + PCR_MATRIX_CLR);
722 +
723 + if (dsa_is_cpu_port(ds, i))
724 + mt7530_cpu_port_enable(priv, i);
725 + else
726 + mt7530_port_disable(ds, i, NULL);
727 + }
728 +
729 + /* Flush the FDB table */
730 + ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, 0);
731 + if (ret < 0)
732 + return ret;
733 +
734 + return 0;
735 +}
736 +
737 +static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
738 +{
739 + struct mt7530_priv *priv = ds->priv;
740 +
741 + return mdiobus_read_nested(priv->bus, port, regnum);
742 +}
743 +
744 +int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
745 +{
746 + struct mt7530_priv *priv = ds->priv;
747 +
748 + return mdiobus_write_nested(priv->bus, port, regnum, val);
749 +}
750 +
751 +static void
752 +mt7530_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
753 +{
754 + int i;
755 +
756 + for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
757 + strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
758 + ETH_GSTRING_LEN);
759 +}
760 +
761 +static void
762 +mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
763 + uint64_t *data)
764 +{
765 + struct mt7530_priv *priv = ds->priv;
766 + const struct mt7530_mib_desc *mib;
767 + u32 reg, i;
768 + u64 hi;
769 +
770 + for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
771 + mib = &mt7530_mib[i];
772 + reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
773 +
774 + data[i] = mt7530_read(priv, reg);
775 + if (mib->size == 2) {
776 + hi = mt7530_read(priv, reg + 4);
777 + data[i] |= hi << 32;
778 + }
779 + }
780 +}
781 +
782 +static int
783 +mt7530_get_sset_count(struct dsa_switch *ds)
784 +{
785 + return ARRAY_SIZE(mt7530_mib);
786 +}
787 +
788 +static void mt7530_adjust_link(struct dsa_switch *ds, int port,
789 + struct phy_device *phydev)
790 +{
791 + struct mt7530_priv *priv = ds->priv;
792 +
793 + if (phy_is_pseudo_fixed_link(phydev)) {
794 + dev_dbg(priv->dev, "phy-mode for master device = %x\n",
795 + phydev->interface);
796 +
797 + /* Setup TX circuit incluing relevant PAD and driving */
798 + mt7530_pad_clk_setup(ds, phydev->interface);
799 +
800 + /* Setup RX circuit, relevant PAD and driving on the host
801 + * which must be placed after the setup on the device side is
802 + * all finished.
803 + */
804 + mt7623_pad_clk_setup(ds);
805 + }
806 +}
807 +
808 +static int
809 +mt7530_cpu_port_enable(struct mt7530_priv *priv,
810 + int port)
811 +{
812 + /* Enable Mediatek header mode on the cpu port */
813 + mt7530_write(priv, MT7530_PVC_P(port),
814 + PORT_SPEC_TAG);
815 +
816 + /* Setup the MAC by default for the cpu port */
817 + mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK);
818 +
819 + /* Disable auto learning on the cpu port */
820 + mt7530_set(priv, MT7530_PSC_P(port), SA_DIS);
821 +
822 + /* Unknown unicast frame fordwarding to the cpu port */
823 + mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port)));
824 +
825 + /* CPU port gets connected to all user ports of
826 + * the switch
827 + */
828 + mt7530_write(priv, MT7530_PCR_P(port),
829 + PCR_MATRIX(priv->ds->enabled_port_mask));
830 +
831 + return 0;
832 +}
833 +
834 +static int
835 +mt7530_port_enable(struct dsa_switch *ds, int port,
836 + struct phy_device *phy)
837 +{
838 + struct mt7530_priv *priv = ds->priv;
839 +
840 + mutex_lock(&priv->reg_mutex);
841 +
842 + /* Setup the MAC for the user port */
843 + mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK);
844 +
845 + /* Allow the user port gets connected to the cpu port and also
846 + * restore the port matrix if the port is the member of a certain
847 + * bridge.
848 + */
849 + priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
850 + priv->ports[port].enable = true;
851 + mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
852 + priv->ports[port].pm);
853 + mt7530_port_set_status(priv, port, 1);
854 +
855 + mutex_unlock(&priv->reg_mutex);
856 +
857 + return 0;
858 +}
859 +
860 +static void
861 +mt7530_port_disable(struct dsa_switch *ds, int port,
862 + struct phy_device *phy)
863 +{
864 + struct mt7530_priv *priv = ds->priv;
865 +
866 + mutex_lock(&priv->reg_mutex);
867 +
868 + /* Clear up all port matrix which could be restored in the next
869 + * enablement for the port.
870 + */
871 + priv->ports[port].enable = false;
872 + mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
873 + PCR_MATRIX_CLR);
874 + mt7530_port_set_status(priv, port, 0);
875 +
876 + mutex_unlock(&priv->reg_mutex);
877 +}
878 +
879 +static void
880 +mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
881 +{
882 + struct mt7530_priv *priv = ds->priv;
883 + u32 stp_state;
884 +
885 + switch (state) {
886 + case BR_STATE_DISABLED:
887 + stp_state = MT7530_STP_DISABLED;
888 + break;
889 + case BR_STATE_BLOCKING:
890 + stp_state = MT7530_STP_BLOCKING;
891 + break;
892 + case BR_STATE_LISTENING:
893 + stp_state = MT7530_STP_LISTENING;
894 + break;
895 + case BR_STATE_LEARNING:
896 + stp_state = MT7530_STP_LEARNING;
897 + break;
898 + case BR_STATE_FORWARDING:
899 + default:
900 + stp_state = MT7530_STP_FORWARDING;
901 + break;
902 + }
903 +
904 + mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
905 +}
906 +
907 +static int
908 +mt7530_port_bridge_join(struct dsa_switch *ds, int port,
909 + struct net_device *bridge)
910 +{
911 + struct mt7530_priv *priv = ds->priv;
912 + u32 port_bitmap = BIT(MT7530_CPU_PORT);
913 + int i;
914 +
915 + mutex_lock(&priv->reg_mutex);
916 +
917 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
918 + /* Add this port to the port matrix of the other ports in the
919 + * same bridge. If the port is disabled, port matrix is kept
920 + * and not being setup until the port becomes enabled.
921 + */
922 + if (ds->enabled_port_mask & BIT(i) && i != port) {
923 + if (ds->ports[i].bridge_dev != bridge)
924 + continue;
925 + if (priv->ports[i].enable)
926 + mt7530_set(priv, MT7530_PCR_P(i),
927 + PCR_MATRIX(BIT(port)));
928 + priv->ports[i].pm |= PCR_MATRIX(BIT(port));
929 +
930 + port_bitmap |= BIT(i);
931 + }
932 + }
933 +
934 + /* Add the all other ports to this port matrix. */
935 + if (priv->ports[port].enable)
936 + mt7530_rmw(priv, MT7530_PCR_P(port),
937 + PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
938 + priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
939 +
940 + mutex_unlock(&priv->reg_mutex);
941 +
942 + return 0;
943 +}
944 +
945 +static void
946 +mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
947 + struct net_device *bridge)
948 +{
949 + struct mt7530_priv *priv = ds->priv;
950 + int i;
951 +
952 + mutex_lock(&priv->reg_mutex);
953 +
954 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
955 + /* Remove this port from the port matrix of the other ports
956 + * in the same bridge. If the port is disabled, port matrix
957 + * is kept and not being setup until the port becomes enabled.
958 + */
959 + if (ds->enabled_port_mask & BIT(i) && i != port) {
960 + if (ds->ports[i].bridge_dev != bridge)
961 + continue;
962 + if (priv->ports[i].enable)
963 + mt7530_clear(priv, MT7530_PCR_P(i),
964 + PCR_MATRIX(BIT(port)));
965 + priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
966 + }
967 + }
968 +
969 + /* Set the cpu port to be the only one in the port matrix of
970 + * this port.
971 + */
972 + if (priv->ports[port].enable)
973 + mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
974 + PCR_MATRIX(BIT(MT7530_CPU_PORT)));
975 + priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
976 +
977 + mutex_unlock(&priv->reg_mutex);
978 +}
979 +
980 +static int
981 +mt7530_port_fdb_prepare(struct dsa_switch *ds, int port,
982 + const struct switchdev_obj_port_fdb *fdb,
983 + struct switchdev_trans *trans)
984 +{
985 + struct mt7530_priv *priv = ds->priv;
986 + int ret;
987 +
988 + /* Because auto-learned entrie shares the same FDB table.
989 + * an entry is reserved with no port_mask to make sure fdb_add
990 + * is called while the entry is still available.
991 + */
992 + mutex_lock(&priv->reg_mutex);
993 + mt7530_fdb_write(priv, fdb->vid, 0, fdb->addr, -1, STATIC_ENT);
994 + ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0);
995 + mutex_unlock(&priv->reg_mutex);
996 +
997 + return ret;
998 +}
999 +
1000 +static void
1001 +mt7530_port_fdb_add(struct dsa_switch *ds, int port,
1002 + const struct switchdev_obj_port_fdb *fdb,
1003 + struct switchdev_trans *trans)
1004 +{
1005 + struct mt7530_priv *priv = ds->priv;
1006 + u8 port_mask = BIT(port);
1007 +
1008 + mutex_lock(&priv->reg_mutex);
1009 + mt7530_fdb_write(priv, fdb->vid, port_mask, fdb->addr, -1, STATIC_ENT);
1010 + mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0);
1011 + mutex_unlock(&priv->reg_mutex);
1012 +}
1013 +
1014 +static int
1015 +mt7530_port_fdb_del(struct dsa_switch *ds, int port,
1016 + const struct switchdev_obj_port_fdb *fdb)
1017 +{
1018 + struct mt7530_priv *priv = ds->priv;
1019 + int ret;
1020 + u8 port_mask = BIT(port);
1021 +
1022 + mutex_lock(&priv->reg_mutex);
1023 + mt7530_fdb_write(priv, fdb->vid, port_mask, fdb->addr, -1, STATIC_EMP);
1024 + ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0);
1025 + mutex_unlock(&priv->reg_mutex);
1026 +
1027 + return ret;
1028 +}
1029 +
1030 +static int
1031 +mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
1032 + struct switchdev_obj_port_fdb *fdb,
1033 + int (*cb)(struct switchdev_obj *obj))
1034 +{
1035 + struct mt7530_priv *priv = ds->priv;
1036 + struct mt7530_fdb _fdb = { 0 };
1037 + int cnt = MT7530_NUM_FDB_RECORDS;
1038 + int ret = 0;
1039 + u32 rsp = 0;
1040 +
1041 + mutex_lock(&priv->reg_mutex);
1042 +
1043 + ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
1044 + if (ret < 0)
1045 + goto err;
1046 +
1047 + do {
1048 + if (rsp & ATC_SRCH_HIT) {
1049 + mt7530_fdb_read(priv, &_fdb);
1050 + if (_fdb.port_mask & BIT(port)) {
1051 + ether_addr_copy(fdb->addr, _fdb.mac);
1052 + fdb->vid = _fdb.vid;
1053 + fdb->ndm_state = _fdb.noarp ?
1054 + NUD_NOARP : NUD_REACHABLE;
1055 + ret = cb(&fdb->obj);
1056 + if (ret < 0)
1057 + break;
1058 + }
1059 + }
1060 + } while (--cnt &&
1061 + !(rsp & ATC_SRCH_END) &&
1062 + !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1063 +err:
1064 + mutex_unlock(&priv->reg_mutex);
1065 +
1066 + return 0;
1067 +}
1068 +
1069 +static enum dsa_tag_protocol
1070 +mtk_get_tag_protocol(struct dsa_switch *ds)
1071 +{
1072 + struct mt7530_priv *priv = ds->priv;
1073 +
1074 + if (!dsa_is_cpu_port(ds, MT7530_CPU_PORT)) {
1075 + dev_warn(priv->dev,
1076 + "port not matched with tagging CPU port\n");
1077 + return DSA_TAG_PROTO_NONE;
1078 + } else {
1079 + return DSA_TAG_PROTO_MTK;
1080 + }
1081 +}
1082 +
1083 +static struct dsa_switch_ops mt7530_switch_ops = {
1084 + .get_tag_protocol = mtk_get_tag_protocol,
1085 + .setup = mt7530_setup,
1086 + .get_strings = mt7530_get_strings,
1087 + .phy_read = mt7530_phy_read,
1088 + .phy_write = mt7530_phy_write,
1089 + .get_ethtool_stats = mt7530_get_ethtool_stats,
1090 + .get_sset_count = mt7530_get_sset_count,
1091 + .adjust_link = mt7530_adjust_link,
1092 + .port_enable = mt7530_port_enable,
1093 + .port_disable = mt7530_port_disable,
1094 + .port_stp_state_set = mt7530_stp_state_set,
1095 + .port_bridge_join = mt7530_port_bridge_join,
1096 + .port_bridge_leave = mt7530_port_bridge_leave,
1097 + .port_fdb_prepare = mt7530_port_fdb_prepare,
1098 + .port_fdb_add = mt7530_port_fdb_add,
1099 + .port_fdb_del = mt7530_port_fdb_del,
1100 + .port_fdb_dump = mt7530_port_fdb_dump,
1101 +};
1102 +
1103 +static int
1104 +mt7530_probe(struct mdio_device *mdiodev)
1105 +{
1106 + struct mt7530_priv *priv;
1107 + struct device_node *dn;
1108 +
1109 + dn = mdiodev->dev.of_node;
1110 +
1111 + priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1112 + if (!priv)
1113 + return -ENOMEM;
1114 +
1115 + priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS);
1116 + if (!priv->ds)
1117 + return -ENOMEM;
1118 +
1119 + /* Use medatek,mcm property to distinguish hardware type that would
1120 + * casues a little bit differences on power-on sequence.
1121 + */
1122 + priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
1123 + if (priv->mcm) {
1124 + dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
1125 +
1126 + priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
1127 + if (IS_ERR(priv->rstc)) {
1128 + dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1129 + return PTR_ERR(priv->rstc);
1130 + }
1131 + }
1132 +
1133 + priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
1134 + if (IS_ERR(priv->core_pwr))
1135 + return PTR_ERR(priv->core_pwr);
1136 +
1137 + priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
1138 + if (IS_ERR(priv->io_pwr))
1139 + return PTR_ERR(priv->io_pwr);
1140 +
1141 + /* Not MCM that indicates switch works as the remote standalone
1142 + * integrated circuit so the GPIO pin would be used to complete
1143 + * the reset, otherwise memory-mapped register accessing used
1144 + * through syscon provides in the case of MCM.
1145 + */
1146 + if (!priv->mcm) {
1147 + priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
1148 + GPIOD_OUT_LOW);
1149 + if (IS_ERR(priv->reset)) {
1150 + dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1151 + return PTR_ERR(priv->reset);
1152 + }
1153 + }
1154 +
1155 + priv->bus = mdiodev->bus;
1156 + priv->dev = &mdiodev->dev;
1157 + priv->ds->priv = priv;
1158 + priv->ds->ops = &mt7530_switch_ops;
1159 + mutex_init(&priv->reg_mutex);
1160 + lpriv = priv;
1161 + dev_set_drvdata(&mdiodev->dev, priv);
1162 +
1163 + return dsa_register_switch(priv->ds, &mdiodev->dev);
1164 +}
1165 +
1166 +static void
1167 +mt7530_remove(struct mdio_device *mdiodev)
1168 +{
1169 + struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
1170 + int ret = 0;
1171 +
1172 + ret = regulator_disable(priv->core_pwr);
1173 + if (ret < 0)
1174 + dev_err(priv->dev,
1175 + "Failed to disable core power: %d\n", ret);
1176 +
1177 + ret = regulator_disable(priv->io_pwr);
1178 + if (ret < 0)
1179 + dev_err(priv->dev, "Failed to disable io pwr: %d\n",
1180 + ret);
1181 +
1182 + dsa_unregister_switch(priv->ds);
1183 + mutex_destroy(&priv->reg_mutex);
1184 +}
1185 +
1186 +static const struct of_device_id mt7530_of_match[] = {
1187 + { .compatible = "mediatek,mt7530" },
1188 + { /* sentinel */ },
1189 +};
1190 +
1191 +static struct mdio_driver mt7530_mdio_driver = {
1192 + .probe = mt7530_probe,
1193 + .remove = mt7530_remove,
1194 + .mdiodrv.driver = {
1195 + .name = "mt7530",
1196 + .of_match_table = mt7530_of_match,
1197 + },
1198 +};
1199 +
1200 +mdio_module_driver(mt7530_mdio_driver);
1201 +
1202 +MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1203 +MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
1204 +MODULE_LICENSE("GPL");
1205 +MODULE_ALIAS("platform:mediatek-mt7530");
1206 --- /dev/null
1207 +++ b/drivers/net/dsa/mt7530.h
1208 @@ -0,0 +1,390 @@
1209 +/*
1210 + * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
1211 + *
1212 + * This program is free software; you can redistribute it and/or modify
1213 + * it under the terms of the GNU General Public License version 2 as
1214 + * published by the Free Software Foundation.
1215 + *
1216 + * This program is distributed in the hope that it will be useful,
1217 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1218 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1219 + * GNU General Public License for more details.
1220 + */
1221 +
1222 +#ifndef __MT7530_H
1223 +#define __MT7530_H
1224 +
1225 +#define MT7530_NUM_PORTS 7
1226 +#define MT7530_CPU_PORT 6
1227 +#define MT7530_NUM_FDB_RECORDS 2048
1228 +
1229 +#define NUM_TRGMII_CTRL 5
1230 +
1231 +#define TRGMII_BASE(x) (0x10000 + (x))
1232 +
1233 +/* Registers to ethsys access */
1234 +#define ETHSYS_CLKCFG0 0x2c
1235 +#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
1236 +
1237 +#define SYSC_REG_RSTCTRL 0x34
1238 +#define RESET_MCM BIT(2)
1239 +
1240 +/* Registers to mac forward control for unknown frames */
1241 +#define MT7530_MFC 0x10
1242 +#define BC_FFP(x) (((x) & 0xff) << 24)
1243 +#define UNM_FFP(x) (((x) & 0xff) << 16)
1244 +#define UNU_FFP(x) (((x) & 0xff) << 8)
1245 +#define UNU_FFP_MASK UNU_FFP(~0)
1246 +
1247 +/* Registers for address table access */
1248 +#define MT7530_ATA1 0x74
1249 +#define STATIC_EMP 0
1250 +#define STATIC_ENT 3
1251 +#define MT7530_ATA2 0x78
1252 +
1253 +/* Register for address table write data */
1254 +#define MT7530_ATWD 0x7c
1255 +
1256 +/* Register for address table control */
1257 +#define MT7530_ATC 0x80
1258 +#define ATC_HASH (((x) & 0xfff) << 16)
1259 +#define ATC_BUSY BIT(15)
1260 +#define ATC_SRCH_END BIT(14)
1261 +#define ATC_SRCH_HIT BIT(13)
1262 +#define ATC_INVALID BIT(12)
1263 +#define ATC_MAT(x) (((x) & 0xf) << 8)
1264 +#define ATC_MAT_MACTAB ATC_MAT(0)
1265 +
1266 +enum mt7530_fdb_cmd {
1267 + MT7530_FDB_READ = 0,
1268 + MT7530_FDB_WRITE = 1,
1269 + MT7530_FDB_FLUSH = 2,
1270 + MT7530_FDB_START = 4,
1271 + MT7530_FDB_NEXT = 5,
1272 +};
1273 +
1274 +/* Registers for table search read address */
1275 +#define MT7530_TSRA1 0x84
1276 +#define MAC_BYTE_0 24
1277 +#define MAC_BYTE_1 16
1278 +#define MAC_BYTE_2 8
1279 +#define MAC_BYTE_3 0
1280 +#define MAC_BYTE_MASK 0xff
1281 +
1282 +#define MT7530_TSRA2 0x88
1283 +#define MAC_BYTE_4 24
1284 +#define MAC_BYTE_5 16
1285 +#define CVID 0
1286 +#define CVID_MASK 0xfff
1287 +
1288 +#define MT7530_ATRD 0x8C
1289 +#define AGE_TIMER 24
1290 +#define AGE_TIMER_MASK 0xff
1291 +#define PORT_MAP 4
1292 +#define PORT_MAP_MASK 0xff
1293 +#define ENT_STATUS 2
1294 +#define ENT_STATUS_MASK 0x3
1295 +
1296 +/* Register for vlan table control */
1297 +#define MT7530_VTCR 0x90
1298 +#define VTCR_BUSY BIT(31)
1299 +#define VTCR_FUNC (((x) & 0xf) << 12)
1300 +#define VTCR_FUNC_RD_VID 0x1
1301 +#define VTCR_FUNC_WR_VID 0x2
1302 +#define VTCR_FUNC_INV_VID 0x3
1303 +#define VTCR_FUNC_VAL_VID 0x4
1304 +#define VTCR_VID ((x) & 0xfff)
1305 +
1306 +/* Register for setup vlan and acl write data */
1307 +#define MT7530_VAWD1 0x94
1308 +#define PORT_STAG BIT(31)
1309 +#define IVL_MAC BIT(30)
1310 +#define PORT_MEM(x) (((x) & 0xff) << 16)
1311 +#define VALID BIT(1)
1312 +
1313 +#define MT7530_VAWD2 0x98
1314 +
1315 +/* Register for port STP state control */
1316 +#define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
1317 +#define FID_PST(x) ((x) & 0x3)
1318 +#define FID_PST_MASK FID_PST(0x3)
1319 +
1320 +enum mt7530_stp_state {
1321 + MT7530_STP_DISABLED = 0,
1322 + MT7530_STP_BLOCKING = 1,
1323 + MT7530_STP_LISTENING = 1,
1324 + MT7530_STP_LEARNING = 2,
1325 + MT7530_STP_FORWARDING = 3
1326 +};
1327 +
1328 +/* Register for port control */
1329 +#define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
1330 +#define PORT_VLAN(x) ((x) & 0x3)
1331 +#define PCR_MATRIX(x) (((x) & 0xff) << 16)
1332 +#define PORT_PRI(x) (((x) & 0x7) << 24)
1333 +#define EG_TAG(x) (((x) & 0x3) << 28)
1334 +#define PCR_MATRIX_MASK PCR_MATRIX(0xff)
1335 +#define PCR_MATRIX_CLR PCR_MATRIX(0)
1336 +
1337 +/* Register for port security control */
1338 +#define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
1339 +#define SA_DIS BIT(4)
1340 +
1341 +/* Register for port vlan control */
1342 +#define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
1343 +#define PORT_SPEC_TAG BIT(5)
1344 +#define VLAN_ATTR(x) (((x) & 0x3) << 6)
1345 +#define STAG_VPID (((x) & 0xffff) << 16)
1346 +
1347 +/* Register for port port-and-protocol based vlan 1 control */
1348 +#define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
1349 +
1350 +/* Register for port MAC control register */
1351 +#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
1352 +#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
1353 +#define PMCR_MAC_MODE BIT(16)
1354 +#define PMCR_FORCE_MODE BIT(15)
1355 +#define PMCR_TX_EN BIT(14)
1356 +#define PMCR_RX_EN BIT(13)
1357 +#define PMCR_BACKOFF_EN BIT(9)
1358 +#define PMCR_BACKPR_EN BIT(8)
1359 +#define PMCR_TX_FC_EN BIT(5)
1360 +#define PMCR_RX_FC_EN BIT(4)
1361 +#define PMCR_FORCE_SPEED_1000 BIT(3)
1362 +#define PMCR_FORCE_FDX BIT(1)
1363 +#define PMCR_FORCE_LNK BIT(0)
1364 +#define PMCR_COMMON_LINK (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
1365 + PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
1366 + PMCR_TX_EN | PMCR_RX_EN | \
1367 + PMCR_TX_FC_EN | PMCR_RX_FC_EN)
1368 +#define PMCR_CPUP_LINK (PMCR_COMMON_LINK | PMCR_FORCE_MODE | \
1369 + PMCR_FORCE_SPEED_1000 | \
1370 + PMCR_FORCE_FDX | \
1371 + PMCR_FORCE_LNK)
1372 +#define PMCR_USERP_LINK PMCR_COMMON_LINK
1373 +#define PMCR_FIXED_LINK (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
1374 + PMCR_FORCE_MODE | PMCR_TX_EN | \
1375 + PMCR_RX_EN | PMCR_BACKPR_EN | \
1376 + PMCR_BACKOFF_EN | \
1377 + PMCR_FORCE_SPEED_1000 | \
1378 + PMCR_FORCE_FDX | \
1379 + PMCR_FORCE_LNK)
1380 +#define PMCR_FIXED_LINK_FC (PMCR_FIXED_LINK | \
1381 + PMCR_TX_FC_EN | PMCR_RX_FC_EN)
1382 +
1383 +#define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
1384 +
1385 +/* Register for MIB */
1386 +#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
1387 +#define MT7530_MIB_CCR 0x4fe0
1388 +#define CCR_MIB_ENABLE BIT(31)
1389 +#define CCR_RX_OCT_CNT_GOOD BIT(7)
1390 +#define CCR_RX_OCT_CNT_BAD BIT(6)
1391 +#define CCR_TX_OCT_CNT_GOOD BIT(5)
1392 +#define CCR_TX_OCT_CNT_BAD BIT(4)
1393 +#define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \
1394 + CCR_RX_OCT_CNT_BAD | \
1395 + CCR_TX_OCT_CNT_GOOD | \
1396 + CCR_TX_OCT_CNT_BAD)
1397 +#define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \
1398 + CCR_RX_OCT_CNT_GOOD | \
1399 + CCR_RX_OCT_CNT_BAD | \
1400 + CCR_TX_OCT_CNT_GOOD | \
1401 + CCR_TX_OCT_CNT_BAD)
1402 +/* Register for system reset */
1403 +#define MT7530_SYS_CTRL 0x7000
1404 +#define SYS_CTRL_PHY_RST BIT(2)
1405 +#define SYS_CTRL_SW_RST BIT(1)
1406 +#define SYS_CTRL_REG_RST BIT(0)
1407 +
1408 +/* Register for hw trap status */
1409 +#define MT7530_HWTRAP 0x7800
1410 +
1411 +/* Register for hw trap modification */
1412 +#define MT7530_MHWTRAP 0x7804
1413 +#define MHWTRAP_MANUAL BIT(16)
1414 +#define MHWTRAP_P5_MAC_SEL BIT(13)
1415 +#define MHWTRAP_P6_DIS BIT(8)
1416 +#define MHWTRAP_P5_RGMII_MODE BIT(7)
1417 +#define MHWTRAP_P5_DIS BIT(6)
1418 +#define MHWTRAP_PHY_ACCESS BIT(5)
1419 +
1420 +/* Register for TOP signal control */
1421 +#define MT7530_TOP_SIG_CTRL 0x7808
1422 +#define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
1423 +
1424 +#define MT7530_IO_DRV_CR 0x7810
1425 +#define P5_IO_CLK_DRV(x) ((x) & 0x3)
1426 +#define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
1427 +
1428 +#define MT7530_P6ECR 0x7830
1429 +#define P6_INTF_MODE_MASK 0x3
1430 +#define P6_INTF_MODE(x) ((x) & 0x3)
1431 +
1432 +/* Registers for TRGMII on the both side */
1433 +#define MT7530_TRGMII_RCK_CTRL 0x7a00
1434 +#define GSW_TRGMII_RCK_CTRL 0x300
1435 +#define RX_RST BIT(31)
1436 +#define RXC_DQSISEL BIT(30)
1437 +#define DQSI1_TAP_MASK (0x7f << 8)
1438 +#define DQSI0_TAP_MASK 0x7f
1439 +#define DQSI1_TAP(x) (((x) & 0x7f) << 8)
1440 +#define DQSI0_TAP(x) ((x) & 0x7f)
1441 +
1442 +#define MT7530_TRGMII_RCK_RTT 0x7a04
1443 +#define GSW_TRGMII_RCK_RTT 0x304
1444 +#define DQS1_GATE BIT(31)
1445 +#define DQS0_GATE BIT(30)
1446 +
1447 +#define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
1448 +#define GSW_TRGMII_RD(x) (0x310 + (x) * 8)
1449 +#define BSLIP_EN BIT(31)
1450 +#define EDGE_CHK BIT(30)
1451 +#define RD_TAP_MASK 0x7f
1452 +#define RD_TAP(x) ((x) & 0x7f)
1453 +
1454 +#define GSW_TRGMII_TXCTRL 0x340
1455 +#define MT7530_TRGMII_TXCTRL 0x7a40
1456 +#define TRAIN_TXEN BIT(31)
1457 +#define TXC_INV BIT(30)
1458 +#define TX_RST BIT(28)
1459 +
1460 +#define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
1461 +#define GSW_TRGMII_TD_ODT(i) (0x354 + 8 * (i))
1462 +#define TD_DM_DRVP(x) ((x) & 0xf)
1463 +#define TD_DM_DRVN(x) (((x) & 0xf) << 4)
1464 +
1465 +#define GSW_INTF_MODE 0x390
1466 +#define INTF_MODE_TRGMII BIT(1)
1467 +
1468 +#define MT7530_TRGMII_TCK_CTRL 0x7a78
1469 +#define TCK_TAP(x) (((x) & 0xf) << 8)
1470 +
1471 +#define MT7530_P5RGMIIRXCR 0x7b00
1472 +#define CSR_RGMII_EDGE_ALIGN BIT(8)
1473 +#define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
1474 +
1475 +#define MT7530_P5RGMIITXCR 0x7b04
1476 +#define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
1477 +
1478 +#define MT7530_CREV 0x7ffc
1479 +#define CHIP_NAME_SHIFT 16
1480 +#define MT7530_ID 0x7530
1481 +
1482 +/* Registers for core PLL access through mmd indirect */
1483 +#define CORE_PLL_GROUP2 0x401
1484 +#define RG_SYSPLL_EN_NORMAL BIT(15)
1485 +#define RG_SYSPLL_VODEN BIT(14)
1486 +#define RG_SYSPLL_LF BIT(13)
1487 +#define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
1488 +#define RG_SYSPLL_LVROD_EN BIT(10)
1489 +#define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
1490 +#define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
1491 +#define RG_SYSPLL_FBKSEL BIT(4)
1492 +#define RT_SYSPLL_EN_AFE_OLT BIT(0)
1493 +
1494 +#define CORE_PLL_GROUP4 0x403
1495 +#define RG_SYSPLL_DDSFBK_EN BIT(12)
1496 +#define RG_SYSPLL_BIAS_EN BIT(11)
1497 +#define RG_SYSPLL_BIAS_LPF_EN BIT(10)
1498 +
1499 +#define CORE_PLL_GROUP5 0x404
1500 +#define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
1501 +
1502 +#define CORE_PLL_GROUP6 0x405
1503 +#define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
1504 +
1505 +#define CORE_PLL_GROUP7 0x406
1506 +#define RG_LCDDS_PWDB BIT(15)
1507 +#define RG_LCDDS_ISO_EN BIT(13)
1508 +#define RG_LCCDS_C(x) (((x) & 0x7) << 4)
1509 +#define RG_LCDDS_PCW_NCPO_CHG BIT(3)
1510 +
1511 +#define CORE_PLL_GROUP10 0x409
1512 +#define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
1513 +
1514 +#define CORE_PLL_GROUP11 0x40a
1515 +#define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
1516 +
1517 +#define CORE_GSWPLL_GRP1 0x40d
1518 +#define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
1519 +#define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
1520 +#define RG_GSWPLL_EN_PRE BIT(11)
1521 +#define RG_GSWPLL_FBKSEL BIT(10)
1522 +#define RG_GSWPLL_BP BIT(9)
1523 +#define RG_GSWPLL_BR BIT(8)
1524 +#define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
1525 +
1526 +#define CORE_GSWPLL_GRP2 0x40e
1527 +#define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
1528 +#define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
1529 +
1530 +#define CORE_TRGMII_GSW_CLK_CG 0x410
1531 +#define REG_GSWCK_EN BIT(0)
1532 +#define REG_TRGMIICK_EN BIT(1)
1533 +
1534 +#define MIB_DESC(_s, _o, _n) \
1535 + { \
1536 + .size = (_s), \
1537 + .offset = (_o), \
1538 + .name = (_n), \
1539 + }
1540 +
1541 +struct mt7530_mib_desc {
1542 + unsigned int size;
1543 + unsigned int offset;
1544 + const char *name;
1545 +};
1546 +
1547 +struct mt7530_fdb {
1548 + u16 vid;
1549 + u8 port_mask;
1550 + u8 aging;
1551 + u8 mac[6];
1552 + bool noarp;
1553 +};
1554 +
1555 +struct mt7530_port {
1556 + bool enable;
1557 + u32 pm;
1558 +};
1559 +
1560 +/* struct mt7530_priv - This is the main data structure for holding the state
1561 + * of the driver
1562 + * @dev: The device pointer
1563 + * @ds: The pointer to the dsa core structure
1564 + * @bus: The bus used for the device and built-in PHY
1565 + * @rstc: The pointer to reset control used by MCM
1566 + * @ethernet: The regmap used for access TRGMII-based registers
1567 + * @core_pwr: The power supplied into the core
1568 + * @io_pwr: The power supplied into the I/O
1569 + * @reset: The descriptor for GPIO line tied to its reset pin
1570 + * @mcm: Flag for distinguishing if standalone IC or module
1571 + * coupling
1572 + * @ports: Holding the state among ports
1573 + * @reg_mutex: The lock for protecting among process accessing
1574 + * registers
1575 + */
1576 +struct mt7530_priv {
1577 + struct device *dev;
1578 + struct dsa_switch *ds;
1579 + struct mii_bus *bus;
1580 + struct reset_control *rstc;
1581 + struct regmap *ethernet;
1582 + struct regulator *core_pwr;
1583 + struct regulator *io_pwr;
1584 + struct gpio_desc *reset;
1585 + bool mcm;
1586 +
1587 + struct mt7530_port ports[MT7530_NUM_PORTS];
1588 + /* protect among processes for registers access*/
1589 + struct mutex reg_mutex;
1590 +};
1591 +
1592 +struct mt7530_hw_stats {
1593 + const char *string;
1594 + u16 reg;
1595 + u8 sizeof_stat;
1596 +};
1597 +
1598 +#endif /* __MT7530_H */
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