target/linux/mediatek/patches-4.9/0058-pinctrl-update.patch

   1 --- a/drivers/pinctrl/mediatek/Kconfig
   2 +++ b/drivers/pinctrl/mediatek/Kconfig
   3 @@ -15,12 +15,6 @@ config PINCTRL_MT2701
   4         default MACH_MT2701
   5         select PINCTRL_MTK
   6
   7 -config PINCTRL_MT7623
   8 -       bool "Mediatek MT7623 pin control" if COMPILE_TEST && !MACH_MT7623
   9 -       depends on OF
  10 -       default MACH_MT7623
  11 -       select PINCTRL_MTK_COMMON
  12 -
  13  config PINCTRL_MT8135
  14         bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
  15         depends on OF
  16 --- a/drivers/pinctrl/mediatek/Makefile
  17 +++ b/drivers/pinctrl/mediatek/Makefile
  18 @@ -3,7 +3,6 @@ obj-y                           += pinctrl-mtk-common.o
  19
  20  # SoC Drivers
  21  obj-$(CONFIG_PINCTRL_MT2701)   += pinctrl-mt2701.o
  22 -obj-$(CONFIG_PINCTRL_MT7623)   += pinctrl-mt7623.o
  23  obj-$(CONFIG_PINCTRL_MT8135)   += pinctrl-mt8135.o
  24  obj-$(CONFIG_PINCTRL_MT8127)   += pinctrl-mt8127.o
  25  obj-$(CONFIG_PINCTRL_MT8173)   += pinctrl-mt8173.o
  26 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
  27 +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
  28 @@ -565,6 +565,7 @@ static int mt2701_pinctrl_probe(struct p
  29
  30  static const struct of_device_id mt2701_pctrl_match[] = {
  31         { .compatible = "mediatek,mt2701-pinctrl", },
  32 +       { .compatible = "mediatek,mt7623-pinctrl", },
  33         {}
  34  };
  35  MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
  36 --- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
  37 +++ /dev/null
  38 @@ -1,379 +0,0 @@
  39 -/*
  40 - * Copyright (c) 2016 John Crispin <blogic@openwrt.org>
  41 - *
  42 - * This program is free software; you can redistribute it and/or modify
  43 - * it under the terms of the GNU General Public License version 2 as
  44 - * published by the Free Software Foundation.
  45 - *
  46 - * This program is distributed in the hope that it will be useful,
  47 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
  48 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  49 - * GNU General Public License for more details.
  50 - */
  51 -
  52 -#include <dt-bindings/pinctrl/mt65xx.h>
  53 -#include <linux/module.h>
  54 -#include <linux/of.h>
  55 -#include <linux/of_device.h>
  56 -#include <linux/platform_device.h>
  57 -#include <linux/pinctrl/pinctrl.h>
  58 -#include <linux/regmap.h>
  59 -
  60 -#include "pinctrl-mtk-common.h"
  61 -#include "pinctrl-mtk-mt7623.h"
  62 -
  63 -static const struct mtk_drv_group_desc mt7623_drv_grp[] =  {
  64 -       /* 0E4E8SR 4/8/12/16 */
  65 -       MTK_DRV_GRP(4, 16, 1, 2, 4),
  66 -       /* 0E2E4SR  2/4/6/8 */
  67 -       MTK_DRV_GRP(2, 8, 1, 2, 2),
  68 -       /* E8E4E2  2/4/6/8/10/12/14/16 */
  69 -       MTK_DRV_GRP(2, 16, 0, 2, 2)
  70 -};
  71 -
  72 -#define DRV_SEL0       0xf50
  73 -#define DRV_SEL1       0xf60
  74 -#define DRV_SEL2       0xf70
  75 -#define DRV_SEL3       0xf80
  76 -#define DRV_SEL4       0xf90
  77 -#define DRV_SEL5       0xfa0
  78 -#define DRV_SEL6       0xfb0
  79 -#define DRV_SEL7       0xfe0
  80 -#define DRV_SEL8       0xfd0
  81 -#define DRV_SEL9       0xff0
  82 -#define DRV_SEL10      0xf00
  83 -
  84 -#define MSDC0_CTRL0    0xcc0
  85 -#define MSDC0_CTRL1    0xcd0
  86 -#define MSDC0_CTRL2    0xce0
  87 -#define MSDC0_CTRL3    0xcf0
  88 -#define MSDC0_CTRL4    0xd00
  89 -#define MSDC0_CTRL5    0xd10
  90 -#define MSDC0_CTRL6    0xd20
  91 -#define MSDC1_CTRL0    0xd30
  92 -#define MSDC1_CTRL1    0xd40
  93 -#define MSDC1_CTRL2    0xd50
  94 -#define MSDC1_CTRL3    0xd60
  95 -#define MSDC1_CTRL4    0xd70
  96 -#define MSDC1_CTRL5    0xd80
  97 -#define MSDC1_CTRL6    0xd90
  98 -
  99 -#define IES_EN0                0xb20
 100 -#define IES_EN1                0xb30
 101 -#define IES_EN2                0xb40
 102 -
 103 -#define SMT_EN0                0xb50
 104 -#define SMT_EN1                0xb60
 105 -#define SMT_EN2                0xb70
 106 -
 107 -static const struct mtk_pin_drv_grp mt7623_pin_drv[] = {
 108 -       MTK_PIN_DRV_GRP(0, DRV_SEL0, 0, 1),
 109 -       MTK_PIN_DRV_GRP(1, DRV_SEL0, 0, 1),
 110 -       MTK_PIN_DRV_GRP(2, DRV_SEL0, 0, 1),
 111 -       MTK_PIN_DRV_GRP(3, DRV_SEL0, 0, 1),
 112 -       MTK_PIN_DRV_GRP(4, DRV_SEL0, 0, 1),
 113 -       MTK_PIN_DRV_GRP(5, DRV_SEL0, 0, 1),
 114 -       MTK_PIN_DRV_GRP(6, DRV_SEL0, 0, 1),
 115 -       MTK_PIN_DRV_GRP(7, DRV_SEL0, 4, 1),
 116 -       MTK_PIN_DRV_GRP(8, DRV_SEL0, 4, 1),
 117 -       MTK_PIN_DRV_GRP(9, DRV_SEL0, 4, 1),
 118 -       MTK_PIN_DRV_GRP(10, DRV_SEL0, 8, 1),
 119 -       MTK_PIN_DRV_GRP(11, DRV_SEL0, 8, 1),
 120 -       MTK_PIN_DRV_GRP(12, DRV_SEL0, 8, 1),
 121 -       MTK_PIN_DRV_GRP(13, DRV_SEL0, 8, 1),
 122 -       MTK_PIN_DRV_GRP(14, DRV_SEL0, 12, 0),
 123 -       MTK_PIN_DRV_GRP(15, DRV_SEL0, 12, 0),
 124 -       MTK_PIN_DRV_GRP(18, DRV_SEL1, 4, 0),
 125 -       MTK_PIN_DRV_GRP(19, DRV_SEL1, 4, 0),
 126 -       MTK_PIN_DRV_GRP(20, DRV_SEL1, 4, 0),
 127 -       MTK_PIN_DRV_GRP(21, DRV_SEL1, 4, 0),
 128 -       MTK_PIN_DRV_GRP(22, DRV_SEL1, 8, 0),
 129 -       MTK_PIN_DRV_GRP(23, DRV_SEL1, 8, 0),
 130 -       MTK_PIN_DRV_GRP(24, DRV_SEL1, 8, 0),
 131 -       MTK_PIN_DRV_GRP(25, DRV_SEL1, 8, 0),
 132 -       MTK_PIN_DRV_GRP(26, DRV_SEL1, 8, 0),
 133 -       MTK_PIN_DRV_GRP(27, DRV_SEL1, 12, 0),
 134 -       MTK_PIN_DRV_GRP(28, DRV_SEL1, 12, 0),
 135 -       MTK_PIN_DRV_GRP(29, DRV_SEL1, 12, 0),
 136 -       MTK_PIN_DRV_GRP(33, DRV_SEL2, 0, 0),
 137 -       MTK_PIN_DRV_GRP(34, DRV_SEL2, 0, 0),
 138 -       MTK_PIN_DRV_GRP(35, DRV_SEL2, 0, 0),
 139 -       MTK_PIN_DRV_GRP(36, DRV_SEL2, 0, 0),
 140 -       MTK_PIN_DRV_GRP(37, DRV_SEL2, 0, 0),
 141 -       MTK_PIN_DRV_GRP(39, DRV_SEL2, 8, 1),
 142 -       MTK_PIN_DRV_GRP(40, DRV_SEL2, 8, 1),
 143 -       MTK_PIN_DRV_GRP(41, DRV_SEL2, 8, 1),
 144 -       MTK_PIN_DRV_GRP(42, DRV_SEL2, 8, 1),
 145 -       MTK_PIN_DRV_GRP(43, DRV_SEL2, 12, 0),
 146 -       MTK_PIN_DRV_GRP(44, DRV_SEL2, 12, 0),
 147 -       MTK_PIN_DRV_GRP(45, DRV_SEL2, 12, 0),
 148 -       MTK_PIN_DRV_GRP(47, DRV_SEL3, 0, 0),
 149 -       MTK_PIN_DRV_GRP(48, DRV_SEL3, 0, 0),
 150 -       MTK_PIN_DRV_GRP(49, DRV_SEL3, 4, 0),
 151 -       MTK_PIN_DRV_GRP(53, DRV_SEL3, 12, 0),
 152 -       MTK_PIN_DRV_GRP(54, DRV_SEL3, 12, 0),
 153 -       MTK_PIN_DRV_GRP(55, DRV_SEL3, 12, 0),
 154 -       MTK_PIN_DRV_GRP(56, DRV_SEL3, 12, 0),
 155 -       MTK_PIN_DRV_GRP(60, DRV_SEL4, 8, 1),
 156 -       MTK_PIN_DRV_GRP(61, DRV_SEL4, 8, 1),
 157 -       MTK_PIN_DRV_GRP(62, DRV_SEL4, 8, 1),
 158 -       MTK_PIN_DRV_GRP(63, DRV_SEL4, 12, 1),
 159 -       MTK_PIN_DRV_GRP(64, DRV_SEL4, 12, 1),
 160 -       MTK_PIN_DRV_GRP(65, DRV_SEL4, 12, 1),
 161 -       MTK_PIN_DRV_GRP(66, DRV_SEL5, 0, 1),
 162 -       MTK_PIN_DRV_GRP(67, DRV_SEL5, 0, 1),
 163 -       MTK_PIN_DRV_GRP(68, DRV_SEL5, 0, 1),
 164 -       MTK_PIN_DRV_GRP(69, DRV_SEL5, 0, 1),
 165 -       MTK_PIN_DRV_GRP(70, DRV_SEL5, 0, 1),
 166 -       MTK_PIN_DRV_GRP(71, DRV_SEL5, 0, 1),
 167 -       MTK_PIN_DRV_GRP(72, DRV_SEL3, 4, 0),
 168 -       MTK_PIN_DRV_GRP(73, DRV_SEL3, 4, 0),
 169 -       MTK_PIN_DRV_GRP(74, DRV_SEL3, 4, 0),
 170 -       MTK_PIN_DRV_GRP(83, DRV_SEL5, 0, 1),
 171 -       MTK_PIN_DRV_GRP(84, DRV_SEL5, 0, 1),
 172 -       MTK_PIN_DRV_GRP(105, MSDC1_CTRL1, 0, 1),
 173 -       MTK_PIN_DRV_GRP(106, MSDC1_CTRL0, 0, 1),
 174 -       MTK_PIN_DRV_GRP(107, MSDC1_CTRL2, 0, 1),
 175 -       MTK_PIN_DRV_GRP(108, MSDC1_CTRL2, 0, 1),
 176 -       MTK_PIN_DRV_GRP(109, MSDC1_CTRL2, 0, 1),
 177 -       MTK_PIN_DRV_GRP(110, MSDC1_CTRL2, 0, 1),
 178 -       MTK_PIN_DRV_GRP(111, MSDC0_CTRL2, 0, 1),
 179 -       MTK_PIN_DRV_GRP(112, MSDC0_CTRL2, 0, 1),
 180 -       MTK_PIN_DRV_GRP(113, MSDC0_CTRL2, 0, 1),
 181 -       MTK_PIN_DRV_GRP(114, MSDC0_CTRL2, 0, 1),
 182 -       MTK_PIN_DRV_GRP(115, MSDC0_CTRL2, 0, 1),
 183 -       MTK_PIN_DRV_GRP(116, MSDC0_CTRL1, 0, 1),
 184 -       MTK_PIN_DRV_GRP(117, MSDC0_CTRL0, 0, 1),
 185 -       MTK_PIN_DRV_GRP(118, MSDC0_CTRL2, 0, 1),
 186 -       MTK_PIN_DRV_GRP(119, MSDC0_CTRL2, 0, 1),
 187 -       MTK_PIN_DRV_GRP(120, MSDC0_CTRL2, 0, 1),
 188 -       MTK_PIN_DRV_GRP(121, MSDC0_CTRL2, 0, 1),
 189 -       MTK_PIN_DRV_GRP(126, DRV_SEL3, 4, 0),
 190 -       MTK_PIN_DRV_GRP(199, DRV_SEL0, 4, 1),
 191 -       MTK_PIN_DRV_GRP(200, DRV_SEL8, 0, 0),
 192 -       MTK_PIN_DRV_GRP(201, DRV_SEL8, 0, 0),
 193 -       MTK_PIN_DRV_GRP(203, DRV_SEL8, 4, 0),
 194 -       MTK_PIN_DRV_GRP(204, DRV_SEL8, 4, 0),
 195 -       MTK_PIN_DRV_GRP(205, DRV_SEL8, 4, 0),
 196 -       MTK_PIN_DRV_GRP(206, DRV_SEL8, 4, 0),
 197 -       MTK_PIN_DRV_GRP(207, DRV_SEL8, 4, 0),
 198 -       MTK_PIN_DRV_GRP(208, DRV_SEL8, 8, 0),
 199 -       MTK_PIN_DRV_GRP(209, DRV_SEL8, 8, 0),
 200 -       MTK_PIN_DRV_GRP(236, DRV_SEL9, 4, 0),
 201 -       MTK_PIN_DRV_GRP(237, DRV_SEL9, 4, 0),
 202 -       MTK_PIN_DRV_GRP(238, DRV_SEL9, 4, 0),
 203 -       MTK_PIN_DRV_GRP(239, DRV_SEL9, 4, 0),
 204 -       MTK_PIN_DRV_GRP(240, DRV_SEL9, 4, 0),
 205 -       MTK_PIN_DRV_GRP(241, DRV_SEL9, 4, 0),
 206 -       MTK_PIN_DRV_GRP(242, DRV_SEL9, 8, 0),
 207 -       MTK_PIN_DRV_GRP(243, DRV_SEL9, 8, 0),
 208 -       MTK_PIN_DRV_GRP(257, MSDC0_CTRL2, 0, 1),
 209 -       MTK_PIN_DRV_GRP(261, MSDC1_CTRL2, 0, 1),
 210 -       MTK_PIN_DRV_GRP(262, DRV_SEL10, 8, 0),
 211 -       MTK_PIN_DRV_GRP(263, DRV_SEL10, 8, 0),
 212 -       MTK_PIN_DRV_GRP(264, DRV_SEL10, 8, 0),
 213 -       MTK_PIN_DRV_GRP(265, DRV_SEL10, 8, 0),
 214 -       MTK_PIN_DRV_GRP(266, DRV_SEL10, 8, 0),
 215 -       MTK_PIN_DRV_GRP(267, DRV_SEL10, 8, 0),
 216 -       MTK_PIN_DRV_GRP(268, DRV_SEL10, 8, 0),
 217 -       MTK_PIN_DRV_GRP(269, DRV_SEL10, 8, 0),
 218 -       MTK_PIN_DRV_GRP(270, DRV_SEL10, 8, 0),
 219 -       MTK_PIN_DRV_GRP(271, DRV_SEL10, 8, 0),
 220 -       MTK_PIN_DRV_GRP(272, DRV_SEL10, 8, 0),
 221 -       MTK_PIN_DRV_GRP(274, DRV_SEL10, 8, 0),
 222 -       MTK_PIN_DRV_GRP(275, DRV_SEL10, 8, 0),
 223 -       MTK_PIN_DRV_GRP(276, DRV_SEL10, 8, 0),
 224 -       MTK_PIN_DRV_GRP(278, DRV_SEL2, 8, 1),
 225 -};
 226 -
 227 -static const struct mtk_pin_spec_pupd_set_samereg mt7623_spec_pupd[] = {
 228 -       MTK_PIN_PUPD_SPEC_SR(105, MSDC1_CTRL1, 8, 9, 10),
 229 -       MTK_PIN_PUPD_SPEC_SR(106, MSDC1_CTRL0, 8, 9, 10),
 230 -       MTK_PIN_PUPD_SPEC_SR(107, MSDC1_CTRL3, 0, 1, 2),
 231 -       MTK_PIN_PUPD_SPEC_SR(108, MSDC1_CTRL3, 4, 5, 6),
 232 -       MTK_PIN_PUPD_SPEC_SR(109, MSDC1_CTRL3, 8, 9, 10),
 233 -       MTK_PIN_PUPD_SPEC_SR(110, MSDC1_CTRL3, 12, 13, 14),
 234 -       MTK_PIN_PUPD_SPEC_SR(111, MSDC0_CTRL4, 12, 13, 14),
 235 -       MTK_PIN_PUPD_SPEC_SR(112, MSDC0_CTRL4, 8, 9, 10),
 236 -       MTK_PIN_PUPD_SPEC_SR(113, MSDC0_CTRL4, 4, 5, 6),
 237 -       MTK_PIN_PUPD_SPEC_SR(114, MSDC0_CTRL4, 0, 1, 2),
 238 -       MTK_PIN_PUPD_SPEC_SR(115, MSDC0_CTRL5, 0, 1, 2),
 239 -       MTK_PIN_PUPD_SPEC_SR(116, MSDC0_CTRL1, 8, 9, 10),
 240 -       MTK_PIN_PUPD_SPEC_SR(117, MSDC0_CTRL0, 8, 9, 10),
 241 -       MTK_PIN_PUPD_SPEC_SR(118, MSDC0_CTRL3, 12, 13, 14),
 242 -       MTK_PIN_PUPD_SPEC_SR(119, MSDC0_CTRL3, 8, 9, 10),
 243 -       MTK_PIN_PUPD_SPEC_SR(120, MSDC0_CTRL3, 4, 5, 6),
 244 -       MTK_PIN_PUPD_SPEC_SR(121, MSDC0_CTRL3, 0, 1, 2),
 245 -};
 246 -
 247 -static int mt7623_spec_pull_set(struct regmap *regmap, unsigned int pin,
 248 -               unsigned char align, bool isup, unsigned int r1r0)
 249 -{
 250 -       return mtk_pctrl_spec_pull_set_samereg(regmap, mt7623_spec_pupd,
 251 -               ARRAY_SIZE(mt7623_spec_pupd), pin, align, isup, r1r0);
 252 -}
 253 -
 254 -static const struct mtk_pin_ies_smt_set mt7623_ies_set[] = {
 255 -       MTK_PIN_IES_SMT_SPEC(0, 6, IES_EN0, 0),
 256 -       MTK_PIN_IES_SMT_SPEC(7, 9, IES_EN0, 1),
 257 -       MTK_PIN_IES_SMT_SPEC(10, 13, IES_EN0, 2),
 258 -       MTK_PIN_IES_SMT_SPEC(14, 15, IES_EN0, 3),
 259 -       MTK_PIN_IES_SMT_SPEC(18, 21, IES_EN0, 5),
 260 -       MTK_PIN_IES_SMT_SPEC(22, 26, IES_EN0, 6),
 261 -       MTK_PIN_IES_SMT_SPEC(27, 29, IES_EN0, 7),
 262 -       MTK_PIN_IES_SMT_SPEC(33, 37, IES_EN0, 8),
 263 -       MTK_PIN_IES_SMT_SPEC(39, 42, IES_EN0, 9),
 264 -       MTK_PIN_IES_SMT_SPEC(43, 45, IES_EN0, 10),
 265 -       MTK_PIN_IES_SMT_SPEC(47, 48, IES_EN0, 11),
 266 -       MTK_PIN_IES_SMT_SPEC(49, 49, IES_EN0, 12),
 267 -       MTK_PIN_IES_SMT_SPEC(53, 56, IES_EN0, 14),
 268 -       MTK_PIN_IES_SMT_SPEC(60, 62, IES_EN1, 0),
 269 -       MTK_PIN_IES_SMT_SPEC(63, 65, IES_EN1, 1),
 270 -       MTK_PIN_IES_SMT_SPEC(66, 71, IES_EN1, 2),
 271 -       MTK_PIN_IES_SMT_SPEC(72, 74, IES_EN0, 12),
 272 -       MTK_PIN_IES_SMT_SPEC(75, 76, IES_EN1, 3),
 273 -       MTK_PIN_IES_SMT_SPEC(83, 84, IES_EN1, 2),
 274 -       MTK_PIN_IES_SMT_SPEC(105, 121, MSDC1_CTRL1, 4),
 275 -       MTK_PIN_IES_SMT_SPEC(122, 125, IES_EN1, 7),
 276 -       MTK_PIN_IES_SMT_SPEC(126, 126, IES_EN0, 12),
 277 -       MTK_PIN_IES_SMT_SPEC(199, 201, IES_EN0, 1),
 278 -       MTK_PIN_IES_SMT_SPEC(203, 207, IES_EN2, 2),
 279 -       MTK_PIN_IES_SMT_SPEC(208, 209, IES_EN2, 3),
 280 -       MTK_PIN_IES_SMT_SPEC(236, 241, IES_EN2, 6),
 281 -       MTK_PIN_IES_SMT_SPEC(242, 243, IES_EN2, 7),
 282 -       MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL2, 4),
 283 -       MTK_PIN_IES_SMT_SPEC(262, 272, IES_EN2, 12),
 284 -       MTK_PIN_IES_SMT_SPEC(274, 276, IES_EN2, 12),
 285 -       MTK_PIN_IES_SMT_SPEC(278, 278, IES_EN2, 13),
 286 -};
 287 -
 288 -static const struct mtk_pin_ies_smt_set mt7623_smt_set[] = {
 289 -       MTK_PIN_IES_SMT_SPEC(0, 6, SMT_EN0, 0),
 290 -       MTK_PIN_IES_SMT_SPEC(7, 9, SMT_EN0, 1),
 291 -       MTK_PIN_IES_SMT_SPEC(10, 13, SMT_EN0, 2),
 292 -       MTK_PIN_IES_SMT_SPEC(14, 15, SMT_EN0, 3),
 293 -       MTK_PIN_IES_SMT_SPEC(18, 21, SMT_EN0, 5),
 294 -       MTK_PIN_IES_SMT_SPEC(22, 26, SMT_EN0, 6),
 295 -       MTK_PIN_IES_SMT_SPEC(27, 29, SMT_EN0, 7),
 296 -       MTK_PIN_IES_SMT_SPEC(33, 37, SMT_EN0, 8),
 297 -       MTK_PIN_IES_SMT_SPEC(39, 42, SMT_EN0, 9),
 298 -       MTK_PIN_IES_SMT_SPEC(43, 45, SMT_EN0, 10),
 299 -       MTK_PIN_IES_SMT_SPEC(47, 48, SMT_EN0, 11),
 300 -       MTK_PIN_IES_SMT_SPEC(49, 49, SMT_EN0, 12),
 301 -       MTK_PIN_IES_SMT_SPEC(53, 56, SMT_EN0, 14),
 302 -       MTK_PIN_IES_SMT_SPEC(60, 62, SMT_EN1, 0),
 303 -       MTK_PIN_IES_SMT_SPEC(63, 65, SMT_EN1, 1),
 304 -       MTK_PIN_IES_SMT_SPEC(66, 71, SMT_EN1, 2),
 305 -       MTK_PIN_IES_SMT_SPEC(72, 74, SMT_EN0, 12),
 306 -       MTK_PIN_IES_SMT_SPEC(75, 76, SMT_EN1, 3),
 307 -       MTK_PIN_IES_SMT_SPEC(83, 84, SMT_EN1, 2),
 308 -       MTK_PIN_IES_SMT_SPEC(105, 106, MSDC1_CTRL1, 11),
 309 -       MTK_PIN_IES_SMT_SPEC(107, 107, MSDC1_CTRL3, 3),
 310 -       MTK_PIN_IES_SMT_SPEC(108, 108, MSDC1_CTRL3, 7),
 311 -       MTK_PIN_IES_SMT_SPEC(109, 109, MSDC1_CTRL3, 11),
 312 -       MTK_PIN_IES_SMT_SPEC(110, 111, MSDC1_CTRL3, 15),
 313 -       MTK_PIN_IES_SMT_SPEC(112, 112, MSDC0_CTRL4, 11),
 314 -       MTK_PIN_IES_SMT_SPEC(113, 113, MSDC0_CTRL4, 7),
 315 -       MTK_PIN_IES_SMT_SPEC(114, 115, MSDC0_CTRL4, 3),
 316 -       MTK_PIN_IES_SMT_SPEC(116, 117, MSDC0_CTRL1, 11),
 317 -       MTK_PIN_IES_SMT_SPEC(118, 118, MSDC0_CTRL3, 15),
 318 -       MTK_PIN_IES_SMT_SPEC(119, 119, MSDC0_CTRL3, 11),
 319 -       MTK_PIN_IES_SMT_SPEC(120, 120, MSDC0_CTRL3, 7),
 320 -       MTK_PIN_IES_SMT_SPEC(121, 121, MSDC0_CTRL3, 3),
 321 -       MTK_PIN_IES_SMT_SPEC(122, 125, SMT_EN1, 7),
 322 -       MTK_PIN_IES_SMT_SPEC(126, 126, SMT_EN0, 12),
 323 -       MTK_PIN_IES_SMT_SPEC(199, 201, SMT_EN0, 1),
 324 -       MTK_PIN_IES_SMT_SPEC(203, 207, SMT_EN2, 2),
 325 -       MTK_PIN_IES_SMT_SPEC(208, 209, SMT_EN2, 3),
 326 -       MTK_PIN_IES_SMT_SPEC(236, 241, SMT_EN2, 6),
 327 -       MTK_PIN_IES_SMT_SPEC(242, 243, SMT_EN2, 7),
 328 -       MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL6, 3),
 329 -       MTK_PIN_IES_SMT_SPEC(262, 272, SMT_EN2, 12),
 330 -       MTK_PIN_IES_SMT_SPEC(274, 276, SMT_EN2, 12),
 331 -       MTK_PIN_IES_SMT_SPEC(278, 278, SMT_EN2, 13),
 332 -};
 333 -
 334 -static int mt7623_ies_smt_set(struct regmap *regmap, unsigned int pin,
 335 -               unsigned char align, int value, enum pin_config_param arg)
 336 -{
 337 -       if (arg == PIN_CONFIG_INPUT_ENABLE)
 338 -               return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_ies_set,
 339 -                       ARRAY_SIZE(mt7623_ies_set), pin, align, value);
 340 -       else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
 341 -               return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_smt_set,
 342 -                       ARRAY_SIZE(mt7623_smt_set), pin, align, value);
 343 -       return -EINVAL;
 344 -}
 345 -
 346 -static const struct mtk_pinctrl_devdata mt7623_pinctrl_data = {
 347 -       .pins = mtk_pins_mt7623,
 348 -       .npins = ARRAY_SIZE(mtk_pins_mt7623),
 349 -       .grp_desc = mt7623_drv_grp,
 350 -       .n_grp_cls = ARRAY_SIZE(mt7623_drv_grp),
 351 -       .pin_drv_grp = mt7623_pin_drv,
 352 -       .n_pin_drv_grps = ARRAY_SIZE(mt7623_pin_drv),
 353 -       .spec_pull_set = mt7623_spec_pull_set,
 354 -       .spec_ies_smt_set = mt7623_ies_smt_set,
 355 -       .dir_offset = 0x0000,
 356 -       .pullen_offset = 0x0150,
 357 -       .pullsel_offset = 0x0280,
 358 -       .dout_offset = 0x0500,
 359 -       .din_offset = 0x0630,
 360 -       .pinmux_offset = 0x0760,
 361 -       .type1_start = 280,
 362 -       .type1_end = 280,
 363 -       .port_shf = 4,
 364 -       .port_mask = 0x1f,
 365 -       .port_align = 4,
 366 -       .eint_offsets = {
 367 -               .name = "mt7623_eint",
 368 -               .stat      = 0x000,
 369 -               .ack       = 0x040,
 370 -               .mask      = 0x080,
 371 -               .mask_set  = 0x0c0,
 372 -               .mask_clr  = 0x100,
 373 -               .sens      = 0x140,
 374 -               .sens_set  = 0x180,
 375 -               .sens_clr  = 0x1c0,
 376 -               .soft      = 0x200,
 377 -               .soft_set  = 0x240,
 378 -               .soft_clr  = 0x280,
 379 -               .pol       = 0x300,
 380 -               .pol_set   = 0x340,
 381 -               .pol_clr   = 0x380,
 382 -               .dom_en    = 0x400,
 383 -               .dbnc_ctrl = 0x500,
 384 -               .dbnc_set  = 0x600,
 385 -               .dbnc_clr  = 0x700,
 386 -               .port_mask = 6,
 387 -               .ports     = 6,
 388 -       },
 389 -       .ap_num = 169,
 390 -       .db_cnt = 16,
 391 -};
 392 -
 393 -static int mt7623_pinctrl_probe(struct platform_device *pdev)
 394 -{
 395 -       return mtk_pctrl_init(pdev, &mt7623_pinctrl_data, NULL);
 396 -}
 397 -
 398 -static const struct of_device_id mt7623_pctrl_match[] = {
 399 -       { .compatible = "mediatek,mt7623-pinctrl", },
 400 -       {}
 401 -};
 402 -MODULE_DEVICE_TABLE(of, mt7623_pctrl_match);
 403 -
 404 -static struct platform_driver mtk_pinctrl_driver = {
 405 -       .probe = mt7623_pinctrl_probe,
 406 -       .driver = {
 407 -               .name = "mediatek-mt7623-pinctrl",
 408 -               .of_match_table = mt7623_pctrl_match,
 409 -       },
 410 -};
 411 -
 412 -static int __init mtk_pinctrl_init(void)
 413 -{
 414 -       return platform_driver_register(&mtk_pinctrl_driver);
 415 -}
 416 -
 417 -arch_initcall(mtk_pinctrl_init);
 418 --- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h
 419 +++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
 420 @@ -185,6 +185,12 @@
 421  #define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
 422  #define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
 423
 424 +#define MT7623_PIN_57_SDA1_FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
 425 +#define MT7623_PIN_57_SDA1_FUNC_SDA1 (MTK_PIN_NO(57) | 1)
 426 +
 427 +#define MT7623_PIN_58_SCL1_FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
 428 +#define MT7623_PIN_58_SCL1_FUNC_SCL1 (MTK_PIN_NO(58) | 1)
 429 +
 430  #define MT7623_PIN_60_WB_RSTB_FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
 431  #define MT7623_PIN_60_WB_RSTB_FUNC_WB_RSTB (MTK_PIN_NO(60) | 1)
 432
 433 @@ -244,6 +250,22 @@
 434  #define MT7623_PIN_76_SCL0_FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
 435  #define MT7623_PIN_76_SCL0_FUNC_SCL0 (MTK_PIN_NO(76) | 1)
 436
 437 +#define MT7623_PIN_79_URXD0_FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
 438 +#define MT7623_PIN_79_URXD0_FUNC_URXD0 (MTK_PIN_NO(79) | 1)
 439 +#define MT7623_PIN_79_URXD0_FUNC_UTXD0 (MTK_PIN_NO(79) | 2)
 440 +
 441 +#define MT7623_PIN_80_UTXD0_FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
 442 +#define MT7623_PIN_80_UTXD0_FUNC_UTXD0 (MTK_PIN_NO(80) | 1)
 443 +#define MT7623_PIN_80_UTXD0_FUNC_URXD0 (MTK_PIN_NO(80) | 2)
 444 +
 445 +#define MT7623_PIN_81_URXD1_FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
 446 +#define MT7623_PIN_81_URXD1_FUNC_URXD1 (MTK_PIN_NO(81) | 1)
 447 +#define MT7623_PIN_81_URXD1_FUNC_UTXD1 (MTK_PIN_NO(81) | 2)
 448 +
 449 +#define MT7623_PIN_82_UTXD1_FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
 450 +#define MT7623_PIN_82_UTXD1_FUNC_UTXD1 (MTK_PIN_NO(82) | 1)
 451 +#define MT7623_PIN_82_UTXD1_FUNC_URXD1 (MTK_PIN_NO(82) | 2)
 452 +
 453  #define MT7623_PIN_83_LCM_RST_FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
 454  #define MT7623_PIN_83_LCM_RST_FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
 455
 456 @@ -351,10 +373,10 @@
 457  #define MT7623_PIN_122_GPIO122_FUNC_SDA2 (MTK_PIN_NO(122) | 4)
 458  #define MT7623_PIN_122_GPIO122_FUNC_URXD0 (MTK_PIN_NO(122) | 5)
 459
 460 -#define MT7623_PIN_123_GPIO123_FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
 461 -#define MT7623_PIN_123_GPIO123_FUNC_TEST (MTK_PIN_NO(123) | 1)
 462 -#define MT7623_PIN_123_GPIO123_FUNC_SCL2 (MTK_PIN_NO(123) | 4)
 463 -#define MT7623_PIN_123_GPIO123_FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
 464 +#define MT7623_PIN_123_HTPLG_FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
 465 +#define MT7623_PIN_123_HTPLG_FUNC_HTPLG (MTK_PIN_NO(123) | 1)
 466 +#define MT7623_PIN_123_HTPLG_FUNC_SCL2 (MTK_PIN_NO(123) | 4)
 467 +#define MT7623_PIN_123_HTPLG_FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
 468
 469  #define MT7623_PIN_124_GPIO124_FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
 470  #define MT7623_PIN_124_GPIO124_FUNC_TEST (MTK_PIN_NO(124) | 1)