target/linux/mediatek/patches-4.9/0015-soc-mediatek-Add-MT2701-scpsys-driver.patch

   1 From 112ef1882e12094c823937f9d72f2f598db02df7 Mon Sep 17 00:00:00 2001
   2 From: Shunli Wang <shunli.wang@mediatek.com>
   3 Date: Thu, 20 Oct 2016 16:56:38 +0800
   4 Subject: [PATCH 2/2] soc: mediatek: Add MT2701 scpsys driver
   5
   6 Add scpsys driver for MT2701.
   7
   8 mtk-scpsys now supports MT8173 (arm64) and MT2701 (arm). So it should
   9 be enabled on both arm64 and arm platforms.
  10
  11 Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
  12 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  13 Reviewed-by: Kevin Hilman <khilman@baylibre.com>
  14 Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  15 ---
  16  drivers/soc/mediatek/Kconfig      |   2 +-
  17  drivers/soc/mediatek/mtk-scpsys.c | 117 +++++++++++++++++++++++++++++++++++++-
  18  2 files changed, 117 insertions(+), 2 deletions(-)
  19
  20 --- a/drivers/soc/mediatek/Kconfig
  21 +++ b/drivers/soc/mediatek/Kconfig
  22 @@ -23,7 +23,7 @@ config MTK_PMIC_WRAP
  23  config MTK_SCPSYS
  24         bool "MediaTek SCPSYS Support"
  25         depends on ARCH_MEDIATEK || COMPILE_TEST
  26 -       default ARM64 && ARCH_MEDIATEK
  27 +       default ARCH_MEDIATEK
  28         select REGMAP
  29         select MTK_INFRACFG
  30         select PM_GENERIC_DOMAINS if PM
  31 --- a/drivers/soc/mediatek/mtk-scpsys.c
  32 +++ b/drivers/soc/mediatek/mtk-scpsys.c
  33 @@ -20,6 +20,7 @@
  34  #include <linux/regulator/consumer.h>
  35  #include <linux/soc/mediatek/infracfg.h>
  36
  37 +#include <dt-bindings/power/mt2701-power.h>
  38  #include <dt-bindings/power/mt8173-power.h>
  39
  40  #define SPM_VDE_PWR_CON                        0x0210
  41 @@ -27,8 +28,13 @@
  42  #define SPM_VEN_PWR_CON                        0x0230
  43  #define SPM_ISP_PWR_CON                        0x0238
  44  #define SPM_DIS_PWR_CON                        0x023c
  45 +#define SPM_CONN_PWR_CON               0x0280
  46  #define SPM_VEN2_PWR_CON               0x0298
  47 -#define SPM_AUDIO_PWR_CON              0x029c
  48 +#define SPM_AUDIO_PWR_CON              0x029c  /* MT8173 */
  49 +#define SPM_BDP_PWR_CON                        0x029c  /* MT2701 */
  50 +#define SPM_ETH_PWR_CON                        0x02a0
  51 +#define SPM_HIF_PWR_CON                        0x02a4
  52 +#define SPM_IFR_MSC_PWR_CON            0x02a8
  53  #define SPM_MFG_2D_PWR_CON             0x02c0
  54  #define SPM_MFG_ASYNC_PWR_CON          0x02c4
  55  #define SPM_USB_PWR_CON                        0x02cc
  56 @@ -42,10 +48,15 @@
  57  #define PWR_ON_2ND_BIT                 BIT(3)
  58  #define PWR_CLK_DIS_BIT                        BIT(4)
  59
  60 +#define PWR_STATUS_CONN                        BIT(1)
  61  #define PWR_STATUS_DISP                        BIT(3)
  62  #define PWR_STATUS_MFG                 BIT(4)
  63  #define PWR_STATUS_ISP                 BIT(5)
  64  #define PWR_STATUS_VDEC                        BIT(7)
  65 +#define PWR_STATUS_BDP                 BIT(14)
  66 +#define PWR_STATUS_ETH                 BIT(15)
  67 +#define PWR_STATUS_HIF                 BIT(16)
  68 +#define PWR_STATUS_IFR_MSC             BIT(17)
  69  #define PWR_STATUS_VENC_LT             BIT(20)
  70  #define PWR_STATUS_VENC                        BIT(21)
  71  #define PWR_STATUS_MFG_2D              BIT(22)
  72 @@ -59,6 +70,7 @@ enum clk_id {
  73         CLK_MFG,
  74         CLK_VENC,
  75         CLK_VENC_LT,
  76 +       CLK_ETHIF,
  77         CLK_MAX,
  78  };
  79
  80 @@ -68,6 +80,7 @@ static const char * const clk_names[] =
  81         "mfg",
  82         "venc",
  83         "venc_lt",
  84 +       "ethif",
  85         NULL,
  86  };
  87
  88 @@ -455,6 +468,96 @@ static void mtk_register_power_domains(s
  89  }
  90
  91  /*
  92 + * MT2701 power domain support
  93 + */
  94 +
  95 +static const struct scp_domain_data scp_domain_data_mt2701[] = {
  96 +       [MT2701_POWER_DOMAIN_CONN] = {
  97 +               .name = "conn",
  98 +               .sta_mask = PWR_STATUS_CONN,
  99 +               .ctl_offs = SPM_CONN_PWR_CON,
 100 +               .bus_prot_mask = 0x0104,
 101 +               .clk_id = {CLK_NONE},
 102 +               .active_wakeup = true,
 103 +       },
 104 +       [MT2701_POWER_DOMAIN_DISP] = {
 105 +               .name = "disp",
 106 +               .sta_mask = PWR_STATUS_DISP,
 107 +               .ctl_offs = SPM_DIS_PWR_CON,
 108 +               .sram_pdn_bits = GENMASK(11, 8),
 109 +               .clk_id = {CLK_MM},
 110 +               .bus_prot_mask = 0x0002,
 111 +               .active_wakeup = true,
 112 +       },
 113 +       [MT2701_POWER_DOMAIN_VDEC] = {
 114 +               .name = "vdec",
 115 +               .sta_mask = PWR_STATUS_VDEC,
 116 +               .ctl_offs = SPM_VDE_PWR_CON,
 117 +               .sram_pdn_bits = GENMASK(11, 8),
 118 +               .sram_pdn_ack_bits = GENMASK(12, 12),
 119 +               .clk_id = {CLK_MM},
 120 +               .active_wakeup = true,
 121 +       },
 122 +       [MT2701_POWER_DOMAIN_ISP] = {
 123 +               .name = "isp",
 124 +               .sta_mask = PWR_STATUS_ISP,
 125 +               .ctl_offs = SPM_ISP_PWR_CON,
 126 +               .sram_pdn_bits = GENMASK(11, 8),
 127 +               .sram_pdn_ack_bits = GENMASK(13, 12),
 128 +               .clk_id = {CLK_MM},
 129 +               .active_wakeup = true,
 130 +       },
 131 +       [MT2701_POWER_DOMAIN_BDP] = {
 132 +               .name = "bdp",
 133 +               .sta_mask = PWR_STATUS_BDP,
 134 +               .ctl_offs = SPM_BDP_PWR_CON,
 135 +               .sram_pdn_bits = GENMASK(11, 8),
 136 +               .clk_id = {CLK_NONE},
 137 +               .active_wakeup = true,
 138 +       },
 139 +       [MT2701_POWER_DOMAIN_ETH] = {
 140 +               .name = "eth",
 141 +               .sta_mask = PWR_STATUS_ETH,
 142 +               .ctl_offs = SPM_ETH_PWR_CON,
 143 +               .sram_pdn_bits = GENMASK(11, 8),
 144 +               .sram_pdn_ack_bits = GENMASK(15, 12),
 145 +               .clk_id = {CLK_ETHIF},
 146 +               .active_wakeup = true,
 147 +       },
 148 +       [MT2701_POWER_DOMAIN_HIF] = {
 149 +               .name = "hif",
 150 +               .sta_mask = PWR_STATUS_HIF,
 151 +               .ctl_offs = SPM_HIF_PWR_CON,
 152 +               .sram_pdn_bits = GENMASK(11, 8),
 153 +               .sram_pdn_ack_bits = GENMASK(15, 12),
 154 +               .clk_id = {CLK_ETHIF},
 155 +               .active_wakeup = true,
 156 +       },
 157 +       [MT2701_POWER_DOMAIN_IFR_MSC] = {
 158 +               .name = "ifr_msc",
 159 +               .sta_mask = PWR_STATUS_IFR_MSC,
 160 +               .ctl_offs = SPM_IFR_MSC_PWR_CON,
 161 +               .clk_id = {CLK_NONE},
 162 +               .active_wakeup = true,
 163 +       },
 164 +};
 165 +
 166 +#define NUM_DOMAINS_MT2701     ARRAY_SIZE(scp_domain_data_mt2701)
 167 +
 168 +static int __init scpsys_probe_mt2701(struct platform_device *pdev)
 169 +{
 170 +       struct scp *scp;
 171 +
 172 +       scp = init_scp(pdev, scp_domain_data_mt2701, NUM_DOMAINS_MT2701);
 173 +       if (IS_ERR(scp))
 174 +               return PTR_ERR(scp);
 175 +
 176 +       mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT2701);
 177 +
 178 +       return 0;
 179 +}
 180 +
 181 +/*
 182   * MT8173 power domain support
 183   */
 184
 185 @@ -583,6 +686,9 @@ static int __init scpsys_probe_mt8173(st
 186
 187  static const struct of_device_id of_scpsys_match_tbl[] = {
 188         {
 189 +               .compatible = "mediatek,mt2701-scpsys",
 190 +               .data = scpsys_probe_mt2701,
 191 +       }, {
 192                 .compatible = "mediatek,mt8173-scpsys",
 193                 .data = scpsys_probe_mt8173,
 194         }, {