target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch

   1 From 83ef9fb21a896ac03c3a78bc3ae0b21f3b0a43a3 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 5 Jan 2016 12:16:17 +0100
   4 Subject: [PATCH 23/91] ARM: dts: mediatek: add MT7623 basic support
   5
   6 This adds basic chip support for Mediatek MT7623.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  arch/arm/boot/dts/Makefile        |    1 +
  11  arch/arm/boot/dts/mt7623-evb.dts  |  474 +++++++++++++++++++++++++++++
  12  arch/arm/boot/dts/mt7623.dtsi     |  593 +++++++++++++++++++++++++++++++++++++
  13  arch/arm/mach-mediatek/Kconfig    |    4 +
  14  arch/arm/mach-mediatek/mediatek.c |    1 +
  15  5 files changed, 1073 insertions(+)
  16  create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
  17  create mode 100644 arch/arm/boot/dts/mt7623.dtsi
  18
  19 --- a/arch/arm/boot/dts/Makefile
  20 +++ b/arch/arm/boot/dts/Makefile
  21 @@ -774,6 +774,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  22         mt6580-evbp1.dtb \
  23         mt6589-aquaris5.dtb \
  24         mt6592-evb.dtb \
  25 +       mt7623-evb.dtb \
  26         mt8127-moose.dtb \
  27         mt8135-evbp1.dtb
  28  dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
  29 --- /dev/null
  30 +++ b/arch/arm/boot/dts/mt7623-evb.dts
  31 @@ -0,0 +1,474 @@
  32 +/*
  33 + * Copyright (c) 2016 MediaTek Inc.
  34 + * Author: John Crispin <blogic@openwrt.org>
  35 + *
  36 + * This program is free software; you can redistribute it and/or modify
  37 + * it under the terms of the GNU General Public License version 2 as
  38 + * published by the Free Software Foundation.
  39 + *
  40 + * This program is distributed in the hope that it will be useful,
  41 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  42 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  43 + * GNU General Public License for more details.
  44 + */
  45 +
  46 +/dts-v1/;
  47 +
  48 +#include "mt7623.dtsi"
  49 +#include <dt-bindings/gpio/gpio.h>
  50 +
  51 +/ {
  52 +       model = "MediaTek MT7623 evaluation board";
  53 +       compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
  54 +
  55 +       chosen {
  56 +               stdout-path = &uart2;
  57 +       };
  58 +
  59 +       memory {
  60 +               reg = <0 0x80000000 0 0x20000000>;
  61 +       };
  62 +
  63 +       usb_p1_vbus: regulator@0 {
  64 +               compatible = "regulator-fixed";
  65 +               regulator-name = "usb_vbus";
  66 +               regulator-min-microvolt = <5000000>;
  67 +               regulator-max-microvolt = <5000000>;
  68 +               gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
  69 +               enable-active-high;
  70 +       };
  71 +};
  72 +
  73 +&cpu0 {
  74 +       proc-supply = <&mt6323_vproc_reg>;
  75 +};
  76 +
  77 +&cpu1 {
  78 +       proc-supply = <&mt6323_vproc_reg>;
  79 +};
  80 +
  81 +&cpu2 {
  82 +       proc-supply = <&mt6323_vproc_reg>;
  83 +};
  84 +
  85 +&cpu3 {
  86 +       proc-supply = <&mt6323_vproc_reg>;
  87 +};
  88 +
  89 +&pwrap {
  90 +       pmic: mt6323 {
  91 +               compatible = "mediatek,mt6323";
  92 +               interrupt-parent = <&pio>;
  93 +               interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
  94 +               interrupt-controller;
  95 +               #interrupt-cells = <2>;
  96 +
  97 +               mt6323regulator: mt6323regulator{
  98 +                       compatible = "mediatek,mt6323-regulator";
  99 +
 100 +                       mt6323_vproc_reg: buck_vproc{
 101 +                               regulator-name = "vproc";
 102 +                               regulator-min-microvolt = < 700000>;
 103 +                               regulator-max-microvolt = <1350000>;
 104 +                               regulator-ramp-delay = <12500>;
 105 +                               regulator-always-on;
 106 +                               regulator-boot-on;
 107 +                       };
 108 +
 109 +                       mt6323_vsys_reg: buck_vsys{
 110 +                               regulator-name = "vsys";
 111 +                               regulator-min-microvolt = <1400000>;
 112 +                               regulator-max-microvolt = <2987500>;
 113 +                               regulator-ramp-delay = <25000>;
 114 +                               regulator-always-on;
 115 +                               regulator-boot-on;
 116 +                       };
 117 +
 118 +                       mt6323_vpa_reg: buck_vpa{
 119 +                               regulator-name = "vpa";
 120 +                               regulator-min-microvolt = < 500000>;
 121 +                               regulator-max-microvolt = <3650000>;
 122 +                       };
 123 +
 124 +                       mt6323_vtcxo_reg: ldo_vtcxo{
 125 +                               regulator-name = "vtcxo";
 126 +                               regulator-min-microvolt = <2800000>;
 127 +                               regulator-max-microvolt = <2800000>;
 128 +                               regulator-enable-ramp-delay = <90>;
 129 +                               regulator-always-on;
 130 +                               regulator-boot-on;
 131 +                       };
 132 +
 133 +                       mt6323_vcn28_reg: ldo_vcn28{
 134 +                               regulator-name = "vcn28";
 135 +                               regulator-min-microvolt = <2800000>;
 136 +                               regulator-max-microvolt = <2800000>;
 137 +                               regulator-enable-ramp-delay = <185>;
 138 +                       };
 139 +
 140 +                       mt6323_vcn33_bt_reg: ldo_vcn33_bt{
 141 +                               regulator-name = "vcn33_bt";
 142 +                               regulator-min-microvolt = <3300000>;
 143 +                               regulator-max-microvolt = <3600000>;
 144 +                               regulator-enable-ramp-delay = <185>;
 145 +                       };
 146 +
 147 +                       mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
 148 +                               regulator-name = "vcn33_wifi";
 149 +                               regulator-min-microvolt = <3300000>;
 150 +                               regulator-max-microvolt = <3600000>;
 151 +                               regulator-enable-ramp-delay = <185>;
 152 +                       };
 153 +
 154 +                       mt6323_va_reg: ldo_va{
 155 +                               regulator-name = "va";
 156 +                               regulator-min-microvolt = <2800000>;
 157 +                               regulator-max-microvolt = <2800000>;
 158 +                               regulator-enable-ramp-delay = <216>;
 159 +                               regulator-always-on;
 160 +                               regulator-boot-on;
 161 +                       };
 162 +
 163 +                       mt6323_vcama_reg: ldo_vcama{
 164 +                               regulator-name = "vcama";
 165 +                               regulator-min-microvolt = <1500000>;
 166 +                               regulator-max-microvolt = <2800000>;
 167 +                               regulator-enable-ramp-delay = <216>;
 168 +                       };
 169 +
 170 +                       mt6323_vio28_reg: ldo_vio28{
 171 +                               regulator-name = "vio28";
 172 +                               regulator-min-microvolt = <2800000>;
 173 +                               regulator-max-microvolt = <2800000>;
 174 +                               regulator-enable-ramp-delay = <216>;
 175 +                               regulator-always-on;
 176 +                               regulator-boot-on;
 177 +                       };
 178 +
 179 +                       mt6323_vusb_reg: ldo_vusb{
 180 +                               regulator-name = "vusb";
 181 +                               regulator-min-microvolt = <3300000>;
 182 +                               regulator-max-microvolt = <3300000>;
 183 +                               regulator-enable-ramp-delay = <216>;
 184 +                               regulator-boot-on;
 185 +                       };
 186 +
 187 +                       mt6323_vmc_reg: ldo_vmc{
 188 +                               regulator-name = "vmc";
 189 +                               regulator-min-microvolt = <1800000>;
 190 +                               regulator-max-microvolt = <3300000>;
 191 +                               regulator-enable-ramp-delay = <36>;
 192 +                               regulator-boot-on;
 193 +                       };
 194 +
 195 +                       mt6323_vmch_reg: ldo_vmch{
 196 +                               regulator-name = "vmch";
 197 +                               regulator-min-microvolt = <3000000>;
 198 +                               regulator-max-microvolt = <3300000>;
 199 +                               regulator-enable-ramp-delay = <36>;
 200 +                               regulator-boot-on;
 201 +                       };
 202 +
 203 +                       mt6323_vemc3v3_reg: ldo_vemc3v3{
 204 +                               regulator-name = "vemc3v3";
 205 +                               regulator-min-microvolt = <3000000>;
 206 +                               regulator-max-microvolt = <3300000>;
 207 +                               regulator-enable-ramp-delay = <36>;
 208 +                               regulator-boot-on;
 209 +                       };
 210 +
 211 +                       mt6323_vgp1_reg: ldo_vgp1{
 212 +                               regulator-name = "vgp1";
 213 +                               regulator-min-microvolt = <1200000>;
 214 +                               regulator-max-microvolt = <3300000>;
 215 +                               regulator-enable-ramp-delay = <216>;
 216 +                       };
 217 +
 218 +                       mt6323_vgp2_reg: ldo_vgp2{
 219 +                               regulator-name = "vgp2";
 220 +                               regulator-min-microvolt = <1200000>;
 221 +                               regulator-max-microvolt = <3000000>;
 222 +                               regulator-enable-ramp-delay = <216>;
 223 +                       };
 224 +
 225 +                       mt6323_vgp3_reg: ldo_vgp3{
 226 +                               regulator-name = "vgp3";
 227 +                               regulator-min-microvolt = <1200000>;
 228 +                               regulator-max-microvolt = <1800000>;
 229 +                               regulator-enable-ramp-delay = <216>;
 230 +                       };
 231 +
 232 +                       mt6323_vcn18_reg: ldo_vcn18{
 233 +                               regulator-name = "vcn18";
 234 +                               regulator-min-microvolt = <1800000>;
 235 +                               regulator-max-microvolt = <1800000>;
 236 +                               regulator-enable-ramp-delay = <216>;
 237 +                       };
 238 +
 239 +                       mt6323_vsim1_reg: ldo_vsim1{
 240 +                               regulator-name = "vsim1";
 241 +                               regulator-min-microvolt = <1800000>;
 242 +                               regulator-max-microvolt = <3000000>;
 243 +                               regulator-enable-ramp-delay = <216>;
 244 +                       };
 245 +
 246 +                       mt6323_vsim2_reg: ldo_vsim2{
 247 +                               regulator-name = "vsim2";
 248 +                               regulator-min-microvolt = <1800000>;
 249 +                               regulator-max-microvolt = <3000000>;
 250 +                               regulator-enable-ramp-delay = <216>;
 251 +                       };
 252 +
 253 +                       mt6323_vrtc_reg: ldo_vrtc{
 254 +                               regulator-name = "vrtc";
 255 +                               regulator-min-microvolt = <2800000>;
 256 +                               regulator-max-microvolt = <2800000>;
 257 +                               regulator-always-on;
 258 +                               regulator-boot-on;
 259 +                       };
 260 +
 261 +                       mt6323_vcamaf_reg: ldo_vcamaf{
 262 +                               regulator-name = "vcamaf";
 263 +                               regulator-min-microvolt = <1200000>;
 264 +                               regulator-max-microvolt = <3300000>;
 265 +                               regulator-enable-ramp-delay = <216>;
 266 +                       };
 267 +
 268 +                       mt6323_vibr_reg: ldo_vibr{
 269 +                               regulator-name = "vibr";
 270 +                               regulator-min-microvolt = <1200000>;
 271 +                               regulator-max-microvolt = <3300000>;
 272 +                               regulator-enable-ramp-delay = <36>;
 273 +                       };
 274 +
 275 +                       mt6323_vrf18_reg: ldo_vrf18{
 276 +                               regulator-name = "vrf18";
 277 +                               regulator-min-microvolt = <1825000>;
 278 +                               regulator-max-microvolt = <1825000>;
 279 +                               regulator-enable-ramp-delay = <187>;
 280 +                       };
 281 +
 282 +                       mt6323_vm_reg: ldo_vm{
 283 +                               regulator-name = "vm";
 284 +                               regulator-min-microvolt = <1200000>;
 285 +                               regulator-max-microvolt = <1800000>;
 286 +                               regulator-enable-ramp-delay = <216>;
 287 +                               regulator-always-on;
 288 +                               regulator-boot-on;
 289 +                       };
 290 +
 291 +                       mt6323_vio18_reg: ldo_vio18{
 292 +                               regulator-name = "vio18";
 293 +                               regulator-min-microvolt = <1800000>;
 294 +                               regulator-max-microvolt = <1800000>;
 295 +                               regulator-enable-ramp-delay = <216>;
 296 +                               regulator-always-on;
 297 +                               regulator-boot-on;
 298 +                       };
 299 +
 300 +                       mt6323_vcamd_reg: ldo_vcamd{
 301 +                               regulator-name = "vcamd";
 302 +                               regulator-min-microvolt = <1200000>;
 303 +                               regulator-max-microvolt = <1800000>;
 304 +                               regulator-enable-ramp-delay = <216>;
 305 +                       };
 306 +
 307 +                       mt6323_vcamio_reg: ldo_vcamio{
 308 +                               regulator-name = "vcamio";
 309 +                               regulator-min-microvolt = <1800000>;
 310 +                               regulator-max-microvolt = <1800000>;
 311 +                               regulator-enable-ramp-delay = <216>;
 312 +                       };
 313 +               };
 314 +       };
 315 +};
 316 +
 317 +&uart2 {
 318 +       status = "okay";
 319 +};
 320 +
 321 +&mmc0 {
 322 +       status = "okay";
 323 +       pinctrl-names = "default", "state_uhs";
 324 +       pinctrl-0 = <&mmc0_pins_default>;
 325 +       pinctrl-1 = <&mmc0_pins_uhs>;
 326 +       bus-width = <8>;
 327 +       max-frequency = <50000000>;
 328 +       cap-mmc-highspeed;
 329 +       vmmc-supply = <&mt6323_vemc3v3_reg>;
 330 +       vqmmc-supply = <&mt6323_vio18_reg>;
 331 +       non-removable;
 332 +};
 333 +
 334 +&mmc1 {
 335 +       status = "okay";
 336 +       pinctrl-names = "default", "state_uhs";
 337 +       pinctrl-0 = <&mmc1_pins_default>;
 338 +       pinctrl-1 = <&mmc1_pins_uhs>;
 339 +       bus-width = <4>;
 340 +       max-frequency = <50000000>;
 341 +       cap-sd-highspeed;
 342 +       sd-uhs-sdr25;
 343 +//     cd-gpios = <&pio 132 0>;
 344 +       vmmc-supply = <&mt6323_vmch_reg>;
 345 +       vqmmc-supply = <&mt6323_vmc_reg>;
 346 +};
 347 +
 348 +&pio {
 349 +       mmc0_pins_default: mmc0default {
 350 +               pins_cmd_dat {
 351 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 352 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 353 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 354 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 355 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 356 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 357 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 358 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 359 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 360 +                       input-enable;
 361 +                       bias-pull-up;
 362 +               };
 363 +
 364 +               pins_clk {
 365 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 366 +                       bias-pull-down;
 367 +               };
 368 +
 369 +               pins_rst {
 370 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 371 +                       bias-pull-up;
 372 +               };
 373 +       };
 374 +
 375 +       mmc0_pins_uhs: mmc0 {
 376 +               pins_cmd_dat {
 377 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 378 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 379 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 380 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 381 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 382 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 383 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 384 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 385 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 386 +                       input-enable;
 387 +                       drive-strength = <MTK_DRIVE_2mA>;
 388 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 389 +               };
 390 +
 391 +               pins_clk {
 392 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 393 +                       drive-strength = <MTK_DRIVE_2mA>;
 394 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
 395 +               };
 396 +
 397 +               pins_rst {
 398 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 399 +                       bias-pull-up;
 400 +               };
 401 +       };
 402 +
 403 +       mmc1_pins_default: mmc1default {
 404 +               pins_cmd_dat {
 405 +                       pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
 406 +                                <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
 407 +                                <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
 408 +                                <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
 409 +                                <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
 410 +                       input-enable;
 411 +                       drive-strength = <MTK_DRIVE_4mA>;
 412 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
 413 +               };
 414 +
 415 +               pins_clk {
 416 +                       pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
 417 +                       bias-pull-down;
 418 +                       drive-strength = <MTK_DRIVE_4mA>;
 419 +               };
 420 +
 421 +//             pins_insert {
 422 +//                     pinmux = <MT8173_PIN_132_I2S0_DATA1_FUNC_GPIO132>;
 423 +//                     bias-pull-up;
 424 +//             };
 425 +       };
 426 +
 427 +       mmc1_pins_uhs: mmc1 {
 428 +               pins_cmd_dat {
 429 +                       pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
 430 +                                <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
 431 +                                <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
 432 +                                <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
 433 +                                <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
 434 +                       input-enable;
 435 +                       drive-strength = <MTK_DRIVE_4mA>;
 436 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
 437 +               };
 438 +
 439 +               pins_clk {
 440 +                       pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
 441 +                       drive-strength = <MTK_DRIVE_4mA>;
 442 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 443 +               };
 444 +       };
 445 +
 446 +       eth_default: eth {
 447 +               pins_eth {
 448 +                       pinmux = <MT7623_PIN_275_G2_MDC_FUNC_MDC>,
 449 +                                <MT7623_PIN_276_G2_MDIO_FUNC_MDIO>,
 450 +                                <MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN>,
 451 +                                <MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3>,
 452 +                                <MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2>,
 453 +                                <MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1>,
 454 +                                <MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0>,
 455 +                                <MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC>,
 456 +                                <MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC>,
 457 +                                <MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0>,
 458 +                                <MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
 459 +                                <MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
 460 +                                <MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
 461 +                                <MT7623_PIN_273_ESW_INT_FUNC_ESW_INT>,
 462 +                                <MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
 463 +               };
 464 +
 465 +               pins_eth_rst {
 466 +                       pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
 467 +                       output-low;
 468 +               };
 469 +       };
 470 +};
 471 +
 472 +&usb1 {
 473 +       vusb33-supply = <&mt6323_vusb_reg>;
 474 +       vbus-supply = <&usb_p1_vbus>;
 475 +       status = "okay";
 476 +};
 477 +
 478 +&u3phy1 {
 479 +       status = "okay";
 480 +};
 481 +
 482 +&pcie {
 483 +       status = "okay";
 484 +};
 485 +
 486 +&eth {
 487 +       status = "okay";
 488 +};
 489 +
 490 +&gmac1 {
 491 +       mac-address = [00 11 22 33 44 56];
 492 +       status = "okay";
 493 +};
 494 +
 495 +&gmac2 {
 496 +       mac-address = [00 11 22 33 44 55];
 497 +       status = "okay";
 498 +};
 499 +
 500 +&gsw {
 501 +       pinctrl-names = "default";
 502 +       pinctrl-0 = <&eth_default>;
 503 +       mediatek,reset-pin = <&pio 15 0>;
 504 +       status = "okay";
 505 +};
 506 diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
 507 new file mode 100644
 508 index 0000000..80c1ab8
 509 --- /dev/null
 510 +++ b/arch/arm/boot/dts/mt7623.dtsi
 511 @@ -0,0 +1,593 @@
 512 +/*
 513 + * Copyright (c) 2016 MediaTek Inc.
 514 + * Author: John Crispin <blogic@openwrt.org>
 515 + *
 516 + * This program is free software; you can redistribute it and/or modify
 517 + * it under the terms of the GNU General Public License version 2 as
 518 + * published by the Free Software Foundation.
 519 + *
 520 + * This program is distributed in the hope that it will be useful,
 521 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 522 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 523 + * GNU General Public License for more details.
 524 + */
 525 +
 526 +#include <dt-bindings/interrupt-controller/irq.h>
 527 +#include <dt-bindings/interrupt-controller/arm-gic.h>
 528 +#include <dt-bindings/clock/mt2701-clk.h>
 529 +#include <dt-bindings/power/mt2701-power.h>
 530 +#include <dt-bindings/phy/phy.h>
 531 +#include <dt-bindings/reset-controller/mt2701-resets.h>
 532 +#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
 533 +#include "skeleton64.dtsi"
 534 +
 535 +
 536 +/ {
 537 +       compatible = "mediatek,mt7623";
 538 +       interrupt-parent = <&sysirq>;
 539 +
 540 +       cpus {
 541 +               #address-cells = <1>;
 542 +               #size-cells = <0>;
 543 +               enable-method = "mediatek,mt6589-smp";
 544 +
 545 +               cpu0: cpu@0 {
 546 +                       device_type = "cpu";
 547 +                       compatible = "arm,cortex-a7";
 548 +                       reg = <0x0>;
 549 +                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
 550 +                                <&apmixedsys CLK_APMIXED_MAINPLL>;
 551 +                       clock-names = "cpu", "intermediate";
 552 +                       operating-points = <
 553 +                               598000 1150000
 554 +                               747500 1150000
 555 +                               1040000 1150000
 556 +                               1196000 1200000
 557 +                               1300000 1300000
 558 +                       >;
 559 +               };
 560 +               cpu1: cpu@1 {
 561 +                       device_type = "cpu";
 562 +                       compatible = "arm,cortex-a7";
 563 +                       reg = <0x1>;
 564 +                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
 565 +                                <&apmixedsys CLK_APMIXED_MAINPLL>;
 566 +                       clock-names = "cpu", "intermediate";
 567 +                       operating-points = <
 568 +                               598000 1150000
 569 +                               747500 1150000
 570 +                               1040000 1150000
 571 +                               1196000 1200000
 572 +                               1300000 1300000
 573 +                       >;
 574 +               };
 575 +               cpu2: cpu@2 {
 576 +                       device_type = "cpu";
 577 +                       compatible = "arm,cortex-a7";
 578 +                       reg = <0x2>;
 579 +                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
 580 +                                <&apmixedsys CLK_APMIXED_MAINPLL>;
 581 +                       clock-names = "cpu", "intermediate";
 582 +                       operating-points = <
 583 +                               598000 1150000
 584 +                               747500 1150000
 585 +                               1040000 1150000
 586 +                               1196000 1200000
 587 +                               1300000 1300000
 588 +                       >;
 589 +               };
 590 +               cpu3: cpu@3 {
 591 +                       device_type = "cpu";
 592 +                       compatible = "arm,cortex-a7";
 593 +                       reg = <0x3>;
 594 +                       clocks = <&infracfg CLK_INFRA_CPUSEL>,
 595 +                                <&apmixedsys CLK_APMIXED_MAINPLL>;
 596 +                       clock-names = "cpu", "intermediate";
 597 +                       operating-points = <
 598 +                               598000 1150000
 599 +                               747500 1150000
 600 +                               1040000 1150000
 601 +                               1196000 1200000
 602 +                               1300000 1300000
 603 +                       >;
 604 +               };
 605 +       };
 606 +
 607 +       system_clk: dummy13m {
 608 +               compatible = "fixed-clock";
 609 +               clock-frequency = <13000000>;
 610 +               #clock-cells = <0>;
 611 +       };
 612 +
 613 +       rtc_clk: dummy32k {
 614 +               compatible = "fixed-clock";
 615 +               clock-frequency = <32000>;
 616 +               #clock-cells = <0>;
 617 +               clock-output-names = "clk32k";
 618 +       };
 619 +
 620 +       clk26m: dummy26m {
 621 +               compatible = "fixed-clock";
 622 +               clock-frequency = <26000000>;
 623 +               #clock-cells = <0>;
 624 +               clock-output-names = "clk26m";
 625 +       };
 626 +
 627 +       timer {
 628 +               compatible = "arm,armv7-timer";
 629 +               interrupt-parent = <&gic>;
 630 +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 631 +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 632 +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 633 +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 634 +               clock-frequency = <13000000>;
 635 +               arm,cpu-registers-not-fw-configured;
 636 +       };
 637 +
 638 +       topckgen: power-controller@10000000 {
 639 +               compatible = "mediatek,mt7623-topckgen",
 640 +                            "mediatek,mt2701-topckgen",
 641 +                            "syscon";
 642 +               reg = <0 0x10000000 0 0x1000>;
 643 +               #clock-cells = <1>;
 644 +       };
 645 +
 646 +       infracfg: power-controller@10001000 {
 647 +               compatible = "mediatek,mt7623-infracfg",
 648 +                            "mediatek,mt2701-infracfg",
 649 +                            "syscon";
 650 +               reg = <0 0x10001000 0 0x1000>;
 651 +               #clock-cells = <1>;
 652 +               #reset-cells = <1>;
 653 +       };
 654 +
 655 +       pericfg: pericfg@10003000 {
 656 +               compatible = "mediatek,mt7623-pericfg",
 657 +                            "mediatek,mt2701-pericfg",
 658 +                            "syscon";
 659 +               reg = <0 0x10003000 0 0x1000>;
 660 +               #clock-cells = <1>;
 661 +               #reset-cells = <1>;
 662 +       };
 663 +
 664 +       pio: pinctrl@10005000 {
 665 +               compatible = "mediatek,mt7623-pinctrl";
 666 +               reg = <0 0x1000b000 0 0x1000>;
 667 +               mediatek,pctl-regmap = <&syscfg_pctl_a>;
 668 +               pins-are-numbered;
 669 +               gpio-controller;
 670 +               #gpio-cells = <2>;
 671 +               interrupt-controller;
 672 +               interrupt-parent = <&gic>;
 673 +               #interrupt-cells = <2>;
 674 +               interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 675 +                            <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 676 +       };
 677 +
 678 +       syscfg_pctl_a: syscfg@10005000 {
 679 +               compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
 680 +               reg = <0 0x10005000 0 0x1000>;
 681 +       };
 682 +
 683 +       scpsys: scpsys@10006000 {
 684 +               #power-domain-cells = <1>;
 685 +               compatible = "mediatek,mt7623-scpsys",
 686 +                            "mediatek,mt2701-scpsys";
 687 +               reg = <0 0x10006000 0 0x1000>;
 688 +               infracfg = <&infracfg>;
 689 +               clocks = <&clk26m>,
 690 +                        <&topckgen CLK_TOP_MM_SEL>;
 691 +               clock-names = "mfg", "mm";
 692 +       };
 693 +
 694 +       watchdog: watchdog@10007000 {
 695 +               compatible = "mediatek,mt7623-wdt",
 696 +                            "mediatek,mt6589-wdt";
 697 +               reg = <0 0x10007000 0 0x100>;
 698 +       };
 699 +
 700 +       timer: timer@10008000 {
 701 +               compatible = "mediatek,mt7623-timer",
 702 +                            "mediatek,mt6577-timer";
 703 +               reg = <0 0x10008000 0 0x80>;
 704 +               interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 705 +               clocks = <&system_clk>, <&rtc_clk>;
 706 +               clock-names = "system-clk", "rtc-clk";
 707 +       };
 708 +
 709 +       pwrap: pwrap@1000d000 {
 710 +               compatible = "mediatek,mt7623-pwrap",
 711 +                            "mediatek,mt2701-pwrap";
 712 +               reg = <0 0x1000d000 0 0x1000>;
 713 +               reg-names = "pwrap";
 714 +               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 715 +               resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
 716 +               reset-names = "pwrap";
 717 +               clocks = <&infracfg CLK_INFRA_PMICSPI>,
 718 +                        <&infracfg CLK_INFRA_PMICWRAP>;
 719 +               clock-names = "spi", "wrap";
 720 +       };
 721 +
 722 +       sysirq: interrupt-controller@10200100 {
 723 +               compatible = "mediatek,mt7623-sysirq",
 724 +                            "mediatek,mt6577-sysirq";
 725 +               interrupt-controller;
 726 +               #interrupt-cells = <3>;
 727 +               interrupt-parent = <&gic>;
 728 +               reg = <0 0x10200100 0 0x1c>;
 729 +       };
 730 +
 731 +       apmixedsys: apmixedsys@10209000 {
 732 +               compatible = "mediatek,mt7623-apmixedsys",
 733 +                            "mediatek,mt2701-apmixedsys";
 734 +               reg = <0 0x10209000 0 0x1000>;
 735 +               #clock-cells = <1>;
 736 +       };
 737 +
 738 +       gic: interrupt-controller@10211000 {
 739 +               compatible = "arm,cortex-a7-gic";
 740 +               interrupt-controller;
 741 +               #interrupt-cells = <3>;
 742 +               interrupt-parent = <&gic>;
 743 +               reg = <0 0x10211000 0 0x1000>,
 744 +                     <0 0x10212000 0 0x1000>,
 745 +                     <0 0x10214000 0 0x2000>,
 746 +                     <0 0x10216000 0 0x2000>;
 747 +       };
 748 +
 749 +       i2c0: i2c@11007000 {
 750 +               compatible = "mediatek,mt7623-i2c",
 751 +                            "mediatek,mt6577-i2c";
 752 +               reg = <0 0x11007000 0 0x70>,
 753 +                     <0 0x11000200 0 0x80>;
 754 +               interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
 755 +               clock-div = <16>;
 756 +               clocks = <&pericfg CLK_PERI_I2C0>,
 757 +                        <&pericfg CLK_PERI_AP_DMA>;
 758 +               clock-names = "main", "dma";
 759 +               #address-cells = <1>;
 760 +               #size-cells = <0>;
 761 +               status = "disabled";
 762 +       };
 763 +
 764 +       i2c1: i2c@11008000 {
 765 +               compatible = "mediatek,mt7623-i2c",
 766 +                            "mediatek,mt6577-i2c";
 767 +               reg = <0 0x11008000 0 0x70>,
 768 +                     <0 0x11000280 0 0x80>;
 769 +               interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
 770 +               clock-div = <16>;
 771 +               clocks = <&pericfg CLK_PERI_I2C1>,
 772 +                        <&pericfg CLK_PERI_AP_DMA>;
 773 +               clock-names = "main", "dma";
 774 +               #address-cells = <1>;
 775 +               #size-cells = <0>;
 776 +               status = "disabled";
 777 +       };
 778 +
 779 +       i2c2: i2c@11009000 {
 780 +               compatible = "mediatek,mt7623-i2c",
 781 +                            "mediatek,mt6577-i2c";
 782 +               reg = <0 0x11009000 0 0x70>,
 783 +                     <0 0x11000300 0 0x80>;
 784 +               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
 785 +               clock-div = <16>;
 786 +               clocks = <&pericfg CLK_PERI_I2C2>,
 787 +                        <&pericfg CLK_PERI_AP_DMA>;
 788 +               clock-names = "main", "dma";
 789 +               #address-cells = <1>;
 790 +               #size-cells = <0>;
 791 +               status = "disabled";
 792 +       };
 793 +
 794 +       uart0: serial@11002000 {
 795 +               compatible = "mediatek,mt7623-uart",
 796 +                            "mediatek,mt6577-uart";
 797 +               reg = <0 0x11002000 0 0x400>;
 798 +               interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 799 +               clocks = <&pericfg CLK_PERI_UART0_SEL>,
 800 +                        <&pericfg CLK_PERI_UART0>;
 801 +               clock-names = "baud", "bus";
 802 +               status = "disabled";
 803 +       };
 804 +
 805 +       uart1: serial@11003000 {
 806 +               compatible = "mediatek,mt7623-uart",
 807 +                            "mediatek,mt6577-uart";
 808 +               reg = <0 0x11003000 0 0x400>;
 809 +               interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 810 +               clocks = <&pericfg CLK_PERI_UART1_SEL>,
 811 +                        <&pericfg CLK_PERI_UART1>;
 812 +               clock-names = "baud", "bus";
 813 +               status = "disabled";
 814 +       };
 815 +
 816 +       uart2: serial@11004000 {
 817 +               compatible = "mediatek,mt7623-uart",
 818 +                            "mediatek,mt6577-uart";
 819 +               reg = <0 0x11004000 0 0x400>;
 820 +               interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 821 +               clocks = <&pericfg CLK_PERI_UART2_SEL>,
 822 +                        <&pericfg CLK_PERI_UART2>;
 823 +               clock-names = "baud", "bus";
 824 +               status = "disabled";
 825 +       };
 826 +
 827 +       uart3: serial@11005000 {
 828 +               compatible = "mediatek,mt7623-uart",
 829 +                            "mediatek,mt6577-uart";
 830 +               reg = <0 0x11005000 0 0x400>;
 831 +               interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 832 +               clocks = <&pericfg CLK_PERI_UART3_SEL>,
 833 +                        <&pericfg CLK_PERI_UART3>;
 834 +               clock-names = "baud", "bus";
 835 +               status = "disabled";
 836 +       };
 837 +
 838 +       spi: spi@1100a000 {
 839 +               compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
 840 +               reg = <0 0x1100a000 0 0x1000>;
 841 +               interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 842 +               clocks = <&pericfg CLK_PERI_SPI0>;
 843 +               clock-names = "main";
 844 +
 845 +               status = "disabled";
 846 +       };
 847 +
 848 +       nandc: nfi@1100d000 {
 849 +               compatible = "mediatek,mt2701-nfc";
 850 +               reg = <0 0x1100d000 0 0x1000>;
 851 +               interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
 852 +               clocks = <&pericfg CLK_PERI_NFI>,
 853 +                        <&pericfg CLK_PERI_NFI_PAD>;
 854 +               clock-names = "nfi_clk", "pad_clk";
 855 +               status = "disabled";
 856 +               ecc-engine = <&bch>;
 857 +               #address-cells = <1>;
 858 +               #size-cells = <0>;
 859 +       };
 860 +
 861 +       bch: ecc@1100e000 {
 862 +               compatible = "mediatek,mt2701-ecc";
 863 +               reg = <0 0x1100e000 0 0x1000>;
 864 +               interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 865 +               clocks = <&pericfg CLK_PERI_NFI_ECC>;
 866 +               clock-names = "nfiecc_clk";
 867 +               status = "disabled";
 868 +       };
 869 +
 870 +       mmc0: mmc@11230000 {
 871 +               compatible = "mediatek,mt7623-mmc",
 872 +                            "mediatek,mt8135-mmc";
 873 +               reg = <0 0x11230000 0 0x1000>;
 874 +               interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
 875 +               clocks = <&pericfg CLK_PERI_MSDC30_0>,
 876 +                        <&topckgen CLK_TOP_MSDC30_0_SEL>;
 877 +               clock-names = "source", "hclk";
 878 +               status = "disabled";
 879 +       };
 880 +
 881 +       mmc1: mmc@11240000 {
 882 +               compatible = "mediatek,mt7623-mmc",
 883 +                            "mediatek,mt8135-mmc";
 884 +               reg = <0 0x11240000 0 0x1000>;
 885 +               interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 886 +               clocks = <&pericfg CLK_PERI_MSDC30_1>,
 887 +                        <&topckgen CLK_TOP_MSDC30_1_SEL>;
 888 +               clock-names = "source", "hclk";
 889 +               status = "disabled";
 890 +       };
 891 +
 892 +       usb1: usb@1a1c0000 {
 893 +               compatible = "mediatek,mt2701-xhci",
 894 +                            "mediatek,mt8173-xhci";
 895 +               reg = <0 0x1a1c0000 0 0x1000>,
 896 +                     <0 0x1a1c4700 0 0x0100>;
 897 +               interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 898 +               clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
 899 +                        <&topckgen CLK_TOP_ETHIF_SEL>;
 900 +               clock-names = "sys_ck", "ethif";
 901 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 902 +               phys = <&phy_port0 PHY_TYPE_USB3>;
 903 +               status = "disabled";
 904 +       };
 905 +
 906 +       u3phy1: usb-phy@1a1c4000 {
 907 +               compatible = "mediatek,mt2701-u3phy",
 908 +                            "mediatek,mt8173-u3phy";
 909 +               reg = <0 0x1a1c4000 0 0x0700>;
 910 +               clocks = <&clk26m>;
 911 +               clock-names = "u3phya_ref";
 912 +               #phy-cells = <1>;
 913 +               #address-cells = <2>;
 914 +               #size-cells = <2>;
 915 +               ranges;
 916 +               status = "disabled";
 917 +
 918 +               phy_port0: phy_port0: port@1a1c4800 {
 919 +                       reg = <0 0x1a1c4800 0 0x800>;
 920 +                       #phy-cells = <1>;
 921 +                       status = "okay";
 922 +               };
 923 +       };
 924 +
 925 +       usb2: usb@1a240000 {
 926 +               compatible = "mediatek,mt2701-xhci",
 927 +                            "mediatek,mt8173-xhci";
 928 +               reg = <0 0x1a240000 0 0x1000>,
 929 +                     <0 0x1a244700 0 0x0100>;
 930 +               interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 931 +               clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
 932 +                        <&topckgen CLK_TOP_ETHIF_SEL>;
 933 +               clock-names = "sys_ck", "ethif";
 934 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 935 +               phys = <&u3phy2 0>;
 936 +               status = "disabled";
 937 +       };
 938 +
 939 +       u3phy2: usb-phy@1a244000 {
 940 +               compatible = "mediatek,mt2701-u3phy",
 941 +                            "mediatek,mt8173-u3phy";
 942 +               reg = <0 0x1a244000 0 0x0700>,
 943 +                     <0 0x1a244800 0 0x0800>;
 944 +               clocks = <&clk26m>;
 945 +               clock-names = "u3phya_ref";
 946 +               #phy-cells = <1>;
 947 +               status = "disabled";
 948 +       };
 949 +
 950 +       hifsys: clock-controller@1a000000 {
 951 +               compatible = "mediatek,mt7623-hifsys",
 952 +                            "mediatek,mt2701-hifsys",
 953 +                            "syscon";
 954 +               reg = <0 0x1a000000 0 0x1000>;
 955 +               #clock-cells = <1>;
 956 +               #reset-cells = <1>;
 957 +       };
 958 +
 959 +       pcie: pcie@1a140000 {
 960 +               compatible = "mediatek,mt7623-pcie";
 961 +               device_type = "pci";
 962 +               reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
 963 +                     <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
 964 +                     <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
 965 +                     <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
 966 +               reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
 967 +               interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
 968 +                            <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
 969 +                            <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
 970 +               interrupt-names = "pcie0", "pcie1", "pcie2";
 971 +               clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
 972 +               clock-names = "pcie";
 973 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 974 +               resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
 975 +                        <&hifsys MT2701_HIFSYS_PCIE1_RST>,
 976 +                        <&hifsys MT2701_HIFSYS_PCIE2_RST>;
 977 +               reset-names = "pcie0", "pcie1", "pcie2";
 978 +
 979 +               mediatek,hifsys = <&hifsys>;
 980 +
 981 +               bus-range = <0x00 0xff>;
 982 +               #address-cells = <3>;
 983 +               #size-cells = <2>;
 984 +
 985 +               ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
 986 +                         0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
 987 +
 988 +               status = "disabled";
 989 +
 990 +               pcie@1,0 {
 991 +                       device_type = "pci";
 992 +                       reg = <0x0800 0 0 0 0>;
 993 +
 994 +                       #address-cells = <3>;
 995 +                       #size-cells = <2>;
 996 +                       ranges;
 997 +               };
 998 +
 999 +               pcie@2,0{
1000 +                       device_type = "pci";
1001 +                       reg = <0x1000 0 0 0 0>;
1002 +
1003 +                       #address-cells = <3>;
1004 +                       #size-cells = <2>;
1005 +                       ranges;
1006 +               };
1007 +
1008 +               pcie@3,0{
1009 +                       device_type = "pci";
1010 +                       reg = <0x1800 0 0 0 0>;
1011 +
1012 +                       #address-cells = <3>;
1013 +                       #size-cells = <2>;
1014 +                       ranges;
1015 +               };
1016 +       };
1017 +
1018 +       ethsys: syscon@1b000000 {
1019 +               compatible = "mediatek,mt2701-ethsys", "syscon";
1020 +               reg = <0 0x1b000000 0 0x1000>;
1021 +               #reset-cells = <1>;
1022 +               #clock-cells = <1>;
1023 +       };
1024 +
1025 +       eth: ethernet@1b100000 {
1026 +               compatible = "mediatek,mt7623-eth";
1027 +               reg = <0 0x1b100000 0 0x20000>;
1028 +
1029 +               clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
1030 +                        <&ethsys CLK_ETHSYS_ESW>,
1031 +                        <&ethsys CLK_ETHSYS_GP2>,
1032 +                        <&ethsys CLK_ETHSYS_GP1>;
1033 +               clock-names = "ethif", "esw", "gp2", "gp1";
1034 +               interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
1035 +                             GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
1036 +                             GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
1037 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1038 +
1039 +               resets = <&ethsys 6>;
1040 +               reset-names = "eth";
1041 +
1042 +               mediatek,ethsys = <&ethsys>;
1043 +               mediatek,pctl = <&syscfg_pctl_a>;
1044 +
1045 +               mediatek,switch = <&gsw>;
1046 +
1047 +               #address-cells = <1>;
1048 +               #size-cells = <0>;
1049 +
1050 +               status = "disabled";
1051 +
1052 +               gmac1: mac@0 {
1053 +                       compatible = "mediatek,eth-mac";
1054 +                       reg = <0>;
1055 +
1056 +                       status = "disabled";
1057 +
1058 +                       phy-mode = "rgmii";
1059 +
1060 +                       fixed-link {
1061 +                               speed = <1000>;
1062 +                               full-duplex;
1063 +                               pause;
1064 +                       };
1065 +               };
1066 +
1067 +               gmac2: mac@1 {
1068 +                       compatible = "mediatek,eth-mac";
1069 +                       reg = <1>;
1070 +
1071 +                       phy-handle = <&phy5>;
1072 +                       status = "disabled";
1073 +               };
1074 +
1075 +               mdio-bus {
1076 +                       #address-cells = <1>;
1077 +                       #size-cells = <0>;
1078 +
1079 +                       phy5: ethernet-phy@5 {
1080 +                               reg = <5>;
1081 +                               phy-mode = "rgmii-rxid";
1082 +                       };
1083 +
1084 +                       phy1f: ethernet-phy@1f {
1085 +                               reg = <0x1f>;
1086 +                               phy-mode = "rgmii";
1087 +                       };
1088 +               };
1089 +       };
1090 +
1091 +       gsw: switch@1b100000 {
1092 +               compatible = "mediatek,mt7623-gsw";
1093 +               interrupt-parent = <&pio>;
1094 +               interrupts = <168 IRQ_TYPE_EDGE_RISING>;
1095 +               resets = <&ethsys 2>;
1096 +               reset-names = "eth";
1097 +               clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
1098 +               clock-names = "trgpll";
1099 +               mt7530-supply = <&mt6323_vpa_reg>;
1100 +               mediatek,pctl-regmap = <&syscfg_pctl_a>;
1101 +               mediatek,ethsys = <&ethsys>;
1102 +               status = "disabled";
1103 +       };
1104 +};
1105 --- a/arch/arm/mach-mediatek/Kconfig
1106 +++ b/arch/arm/mach-mediatek/Kconfig
1107 @@ -21,6 +21,10 @@ config MACH_MT6592
1108         bool "MediaTek MT6592 SoCs support"
1109         default ARCH_MEDIATEK
1110
1111 +config MACH_MT7623
1112 +       bool "MediaTek MT7623 SoCs support"
1113 +       default ARCH_MEDIATEK
1114 +
1115  config MACH_MT8127
1116         bool "MediaTek MT8127 SoCs support"
1117         default ARCH_MEDIATEK
1118 --- a/arch/arm/mach-mediatek/mediatek.c
1119 +++ b/arch/arm/mach-mediatek/mediatek.c
1120 @@ -46,6 +46,7 @@ static void __init mediatek_timer_init(v
1121  static const char * const mediatek_board_dt_compat[] = {
1122         "mediatek,mt6589",
1123         "mediatek,mt6592",
1124 +       "mediatek,mt7623",
1125         "mediatek,mt8127",
1126         "mediatek,mt8135",
1127         NULL,