mediatek: update to latest kernel patchset from v4.13-rc
[openwrt/openwrt.git] / target / linux / mediatek / files / drivers / crypto / mediatek / mtk-platform.h
1 /*
2 * Driver for EIP97 cryptographic accelerator.
3 *
4 * Copyright (c) 2016 Ryder Lee <ryder.lee@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12 #ifndef __MTK_PLATFORM_H_
13 #define __MTK_PLATFORM_H_
14
15 #include <crypto/algapi.h>
16 #include <crypto/internal/aead.h>
17 #include <crypto/internal/hash.h>
18 #include <crypto/scatterwalk.h>
19 #include <crypto/skcipher.h>
20 #include <linux/crypto.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/interrupt.h>
23 #include <linux/scatterlist.h>
24 #include "mtk-regs.h"
25
26 #define MTK_RDR_PROC_THRESH BIT(0)
27 #define MTK_RDR_PROC_MODE BIT(23)
28 #define MTK_CNT_RST BIT(31)
29 #define MTK_IRQ_RDR0 BIT(1)
30 #define MTK_IRQ_RDR1 BIT(3)
31 #define MTK_IRQ_RDR2 BIT(5)
32 #define MTK_IRQ_RDR3 BIT(7)
33
34 #define SIZE_IN_WORDS(x) ((x) >> 2)
35
36 /**
37 * Ring 0/1 are used by AES encrypt and decrypt.
38 * Ring 2/3 are used by SHA.
39 */
40 enum {
41 MTK_RING0,
42 MTK_RING1,
43 MTK_RING2,
44 MTK_RING3,
45 MTK_RING_MAX
46 };
47
48 #define MTK_REC_NUM (MTK_RING_MAX / 2)
49 #define MTK_IRQ_NUM 5
50
51 /**
52 * struct mtk_desc - DMA descriptor
53 * @hdr: the descriptor control header
54 * @buf: DMA address of input buffer segment
55 * @ct: DMA address of command token that control operation flow
56 * @ct_hdr: the command token control header
57 * @tag: the user-defined field
58 * @tfm: DMA address of transform state
59 * @bound: align descriptors offset boundary
60 *
61 * Structure passed to the crypto engine to describe where source
62 * data needs to be fetched and how it needs to be processed.
63 */
64 struct mtk_desc {
65 __le32 hdr;
66 __le32 buf;
67 __le32 ct;
68 __le32 ct_hdr;
69 __le32 tag;
70 __le32 tfm;
71 __le32 bound[2];
72 };
73
74 #define MTK_DESC_NUM 512
75 #define MTK_DESC_OFF SIZE_IN_WORDS(sizeof(struct mtk_desc))
76 #define MTK_DESC_SZ (MTK_DESC_OFF - 2)
77 #define MTK_DESC_RING_SZ ((sizeof(struct mtk_desc) * MTK_DESC_NUM))
78 #define MTK_DESC_CNT(x) ((MTK_DESC_OFF * (x)) << 2)
79 #define MTK_DESC_LAST cpu_to_le32(BIT(22))
80 #define MTK_DESC_FIRST cpu_to_le32(BIT(23))
81 #define MTK_DESC_BUF_LEN(x) cpu_to_le32(x)
82 #define MTK_DESC_CT_LEN(x) cpu_to_le32((x) << 24)
83
84 /**
85 * struct mtk_ring - Descriptor ring
86 * @cmd_base: pointer to command descriptor ring base
87 * @cmd_next: pointer to the next command descriptor
88 * @cmd_dma: DMA address of command descriptor ring
89 * @res_base: pointer to result descriptor ring base
90 * @res_next: pointer to the next result descriptor
91 * @res_prev: pointer to the previous result descriptor
92 * @res_dma: DMA address of result descriptor ring
93 *
94 * A descriptor ring is a circular buffer that is used to manage
95 * one or more descriptors. There are two type of descriptor rings;
96 * the command descriptor ring and result descriptor ring.
97 */
98 struct mtk_ring {
99 struct mtk_desc *cmd_base;
100 struct mtk_desc *cmd_next;
101 dma_addr_t cmd_dma;
102 struct mtk_desc *res_base;
103 struct mtk_desc *res_next;
104 struct mtk_desc *res_prev;
105 dma_addr_t res_dma;
106 };
107
108 /**
109 * struct mtk_aes_dma - Structure that holds sg list info
110 * @sg: pointer to scatter-gather list
111 * @nents: number of entries in the sg list
112 * @remainder: remainder of sg list
113 * @sg_len: number of entries in the sg mapped list
114 */
115 struct mtk_aes_dma {
116 struct scatterlist *sg;
117 int nents;
118 u32 remainder;
119 u32 sg_len;
120 };
121
122 struct mtk_aes_base_ctx;
123 struct mtk_aes_rec;
124 struct mtk_cryp;
125
126 typedef int (*mtk_aes_fn)(struct mtk_cryp *cryp, struct mtk_aes_rec *aes);
127
128 /**
129 * struct mtk_aes_rec - AES operation record
130 * @cryp: pointer to Cryptographic device
131 * @queue: crypto request queue
132 * @areq: pointer to async request
133 * @done_task: the tasklet is use in AES interrupt
134 * @queue_task: the tasklet is used to dequeue request
135 * @ctx: pointer to current context
136 * @src: the structure that holds source sg list info
137 * @dst: the structure that holds destination sg list info
138 * @aligned_sg: the scatter list is use to alignment
139 * @real_dst: pointer to the destination sg list
140 * @resume: pointer to resume function
141 * @total: request buffer length
142 * @buf: pointer to page buffer
143 * @id: the current use of ring
144 * @flags: it's describing AES operation state
145 * @lock: the async queue lock
146 *
147 * Structure used to record AES execution state.
148 */
149 struct mtk_aes_rec {
150 struct mtk_cryp *cryp;
151 struct crypto_queue queue;
152 struct crypto_async_request *areq;
153 struct tasklet_struct done_task;
154 struct tasklet_struct queue_task;
155 struct mtk_aes_base_ctx *ctx;
156 struct mtk_aes_dma src;
157 struct mtk_aes_dma dst;
158
159 struct scatterlist aligned_sg;
160 struct scatterlist *real_dst;
161
162 mtk_aes_fn resume;
163
164 size_t total;
165 void *buf;
166
167 u8 id;
168 unsigned long flags;
169 /* queue lock */
170 spinlock_t lock;
171 };
172
173 /**
174 * struct mtk_sha_rec - SHA operation record
175 * @cryp: pointer to Cryptographic device
176 * @queue: crypto request queue
177 * @req: pointer to ahash request
178 * @done_task: the tasklet is use in SHA interrupt
179 * @queue_task: the tasklet is used to dequeue request
180 * @id: the current use of ring
181 * @flags: it's describing SHA operation state
182 * @lock: the async queue lock
183 *
184 * Structure used to record SHA execution state.
185 */
186 struct mtk_sha_rec {
187 struct mtk_cryp *cryp;
188 struct crypto_queue queue;
189 struct ahash_request *req;
190 struct tasklet_struct done_task;
191 struct tasklet_struct queue_task;
192
193 u8 id;
194 unsigned long flags;
195 /* queue lock */
196 spinlock_t lock;
197 };
198
199 /**
200 * struct mtk_cryp - Cryptographic device
201 * @base: pointer to mapped register I/O base
202 * @dev: pointer to device
203 * @clk_ethif: pointer to ethif clock
204 * @clk_cryp: pointer to crypto clock
205 * @irq: global system and rings IRQ
206 * @ring: pointer to descriptor rings
207 * @aes: pointer to operation record of AES
208 * @sha: pointer to operation record of SHA
209 * @aes_list: device list of AES
210 * @sha_list: device list of SHA
211 * @rec: it's used to select SHA record for tfm
212 *
213 * Structure storing cryptographic device information.
214 */
215 struct mtk_cryp {
216 void __iomem *base;
217 struct device *dev;
218 struct clk *clk_ethif;
219 struct clk *clk_cryp;
220 int irq[MTK_IRQ_NUM];
221
222 struct mtk_ring *ring[MTK_RING_MAX];
223 struct mtk_aes_rec *aes[MTK_REC_NUM];
224 struct mtk_sha_rec *sha[MTK_REC_NUM];
225
226 struct list_head aes_list;
227 struct list_head sha_list;
228
229 bool rec;
230 };
231
232 int mtk_cipher_alg_register(struct mtk_cryp *cryp);
233 void mtk_cipher_alg_release(struct mtk_cryp *cryp);
234 int mtk_hash_alg_register(struct mtk_cryp *cryp);
235 void mtk_hash_alg_release(struct mtk_cryp *cryp);
236
237 #endif /* __MTK_PLATFORM_H_ */