projects / openwrt / openwrt.git / blob
? search:


7093d3513179ef0e336d5052bb8ffdaecefdbb92
[openwrt/openwrt.git] / target / linux / mediatek / files / arch / arm / boot / dts / _mt7623.dtsi
1 /*
2 * Copyright (c) 2016 MediaTek Inc.
3 * Author: John Crispin <blogic@openwrt.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/clock/mt2701-clk.h>
18 #include <dt-bindings/power/mt2701-power.h>
19 #include <dt-bindings/phy/phy.h>
20 #include <dt-bindings/reset/mt2701-resets.h>
21 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
22 #include "skeleton64.dtsi"
23
24
25 / {
26 compatible = "mediatek,mt7623";
27 interrupt-parent = <&sysirq>;
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32 enable-method = "mediatek,mt6589-smp";
33
34 cpu0: cpu@0 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a7";
37 reg = <0x0>;
38 clocks = <&infracfg CLK_INFRA_CPUSEL>,
39 <&apmixedsys CLK_APMIXED_MAINPLL>;
40 clock-names = "cpu", "intermediate";
41 operating-points = <
42 598000 1150000
43 747500 1150000
44 1040000 1150000
45 1196000 1200000
46 1300000 1300000
47 >;
48 };
49 cpu1: cpu@1 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a7";
52 reg = <0x1>;
53 clocks = <&infracfg CLK_INFRA_CPUSEL>,
54 <&apmixedsys CLK_APMIXED_MAINPLL>;
55 clock-names = "cpu", "intermediate";
56 operating-points = <
57 598000 1150000
58 747500 1150000
59 1040000 1150000
60 1196000 1200000
61 1300000 1300000
62 >;
63 };
64 cpu2: cpu@2 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a7";
67 reg = <0x2>;
68 clocks = <&infracfg CLK_INFRA_CPUSEL>,
69 <&apmixedsys CLK_APMIXED_MAINPLL>;
70 clock-names = "cpu", "intermediate";
71 operating-points = <
72 598000 1150000
73 747500 1150000
74 1040000 1150000
75 1196000 1200000
76 1300000 1300000
77 >;
78 };
79 cpu3: cpu@3 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a7";
82 reg = <0x3>;
83 clocks = <&infracfg CLK_INFRA_CPUSEL>,
84 <&apmixedsys CLK_APMIXED_MAINPLL>;
85 clock-names = "cpu", "intermediate";
86 operating-points = <
87 598000 1150000
88 747500 1150000
89 1040000 1150000
90 1196000 1200000
91 1300000 1300000
92 >;
93 };
94 };
95
96 system_clk: dummy13m {
97 compatible = "fixed-clock";
98 clock-frequency = <13000000>;
99 #clock-cells = <0>;
100 };
101
102 rtc_clk: dummy32k {
103 compatible = "fixed-clock";
104 clock-frequency = <32000>;
105 #clock-cells = <0>;
106 clock-output-names = "clk32k";
107 };
108
109 clk26m: dummy26m {
110 compatible = "fixed-clock";
111 clock-frequency = <26000000>;
112 #clock-cells = <0>;
113 clock-output-names = "clk26m";
114 };
115
116 timer {
117 compatible = "arm,armv7-timer";
118 interrupt-parent = <&gic>;
119 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
120 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
121 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
122 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
123 clock-frequency = <13000000>;
124 arm,cpu-registers-not-fw-configured;
125 };
126
127 topckgen: power-controller@10000000 {
128 compatible = "mediatek,mt7623-topckgen",
129 "mediatek,mt2701-topckgen",
130 "syscon";
131 reg = <0 0x10000000 0 0x1000>;
132 #clock-cells = <1>;
133 };
134
135 infracfg: power-controller@10001000 {
136 compatible = "mediatek,mt7623-infracfg",
137 "mediatek,mt2701-infracfg",
138 "syscon";
139 reg = <0 0x10001000 0 0x1000>;
140 #clock-cells = <1>;
141 #reset-cells = <1>;
142 };
143
144 pericfg: pericfg@10003000 {
145 compatible = "mediatek,mt7623-pericfg",
146 "mediatek,mt2701-pericfg",
147 "syscon";
148 reg = <0 0x10003000 0 0x1000>;
149 #clock-cells = <1>;
150 #reset-cells = <1>;
151 };
152
153 pio: pinctrl@10005000 {
154 compatible = "mediatek,mt2701-pinctrl";
155 reg = <0 0x1000b000 0 0x1000>;
156 mediatek,pctl-regmap = <&syscfg_pctl_a>;
157 pins-are-numbered;
158 gpio-controller;
159 #gpio-cells = <2>;
160 interrupt-controller;
161 interrupt-parent = <&gic>;
162 #interrupt-cells = <2>;
163 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
165 };
166
167 syscfg_pctl_a: syscfg@10005000 {
168 compatible = "mediatek,mt7623-pctl-a-syscfg",
169 "mediatek,mt2701-pctl-a-syscfg",
170 "syscon";
171 reg = <0 0x10005000 0 0x1000>;
172 };
173
174 scpsys: scpsys@10006000 {
175 #power-domain-cells = <1>;
176 compatible = "mediatek,mt7623-scpsys",
177 "mediatek,mt2701-scpsys";
178 reg = <0 0x10006000 0 0x1000>;
179 infracfg = <&infracfg>;
180 clocks = <&clk26m>,
181 <&topckgen CLK_TOP_MM_SEL>,
182 <&topckgen CLK_TOP_ETHIF_SEL>;
183 clock-names = "mfg", "mm", "ethif";
184 };
185
186 watchdog: watchdog@10007000 {
187 compatible = "mediatek,mt7623-wdt",
188 "mediatek,mt6589-wdt";
189 reg = <0 0x10007000 0 0x100>;
190 };
191
192 timer: timer@10008000 {
193 compatible = "mediatek,mt7623-timer",
194 "mediatek,mt6577-timer";
195 reg = <0 0x10008000 0 0x80>;
196 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
197 clocks = <&system_clk>, <&rtc_clk>;
198 clock-names = "system-clk", "rtc-clk";
199 };
200
201 pwrap: pwrap@1000d000 {
202 compatible = "mediatek,mt7623-pwrap",
203 "mediatek,mt2701-pwrap";
204 reg = <0 0x1000d000 0 0x1000>;
205 reg-names = "pwrap";
206 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
207 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
208 reset-names = "pwrap";
209 clocks = <&infracfg CLK_INFRA_PMICSPI>,
210 <&infracfg CLK_INFRA_PMICWRAP>;
211 clock-names = "spi", "wrap";
212 };
213
214 sysirq: interrupt-controller@10200100 {
215 compatible = "mediatek,mt7623-sysirq",
216 "mediatek,mt6577-sysirq";
217 interrupt-controller;
218 #interrupt-cells = <3>;
219 interrupt-parent = <&gic>;
220 reg = <0 0x10200100 0 0x1c>;
221 };
222
223 efuse: efuse@10206000 {
224 compatible = "mediatek,mt7623-efuse",
225 "mediatek,efuse";
226 reg = <0 0x10206000 0 0x1000>;
227 #address-cells = <1>;
228 #size-cells = <1>;
229
230 /* Data cells */
231 thermal_calibration: calib@424 {
232 reg = <0x424 0xc>;
233 };
234 };
235
236 apmixedsys: apmixedsys@10209000 {
237 compatible = "mediatek,mt7623-apmixedsys",
238 "mediatek,mt2701-apmixedsys";
239 reg = <0 0x10209000 0 0x1000>;
240 #clock-cells = <1>;
241 };
242
243 gic: interrupt-controller@10211000 {
244 compatible = "arm,cortex-a7-gic";
245 interrupt-controller;
246 #interrupt-cells = <3>;
247 interrupt-parent = <&gic>;
248 reg = <0 0x10211000 0 0x1000>,
249 <0 0x10212000 0 0x1000>,
250 <0 0x10214000 0 0x2000>,
251 <0 0x10216000 0 0x2000>;
252 };
253
254 auxadc: adc@11001000 {
255 compatible = "mediatek,mt7623-auxadc",
256 "mediatek,mt2701-auxadc";
257 reg = <0 0x11001000 0 0x1000>;
258 clocks = <&pericfg CLK_PERI_AUXADC>;
259 clock-names = "main";
260 #io-channel-cells = <1>;
261 };
262
263 uart0: serial@11002000 {
264 compatible = "mediatek,mt7623-uart",
265 "mediatek,mt6577-uart";
266 reg = <0 0x11002000 0 0x400>;
267 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
268 clocks = <&pericfg CLK_PERI_UART0_SEL>,
269 <&pericfg CLK_PERI_UART0>;
270 clock-names = "baud", "bus";
271 status = "disabled";
272 };
273
274 uart1: serial@11003000 {
275 compatible = "mediatek,mt7623-uart",
276 "mediatek,mt6577-uart";
277 reg = <0 0x11003000 0 0x400>;
278 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
279 clocks = <&pericfg CLK_PERI_UART1_SEL>,
280 <&pericfg CLK_PERI_UART1>;
281 clock-names = "baud", "bus";
282 status = "disabled";
283 };
284
285 uart2: serial@11004000 {
286 compatible = "mediatek,mt7623-uart",
287 "mediatek,mt6577-uart";
288 reg = <0 0x11004000 0 0x400>;
289 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
290 clocks = <&pericfg CLK_PERI_UART2_SEL>,
291 <&pericfg CLK_PERI_UART2>;
292 clock-names = "baud", "bus";
293 status = "disabled";
294 };
295
296 uart3: serial@11005000 {
297 compatible = "mediatek,mt7623-uart",
298 "mediatek,mt6577-uart";
299 reg = <0 0x11005000 0 0x400>;
300 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
301 clocks = <&pericfg CLK_PERI_UART3_SEL>,
302 <&pericfg CLK_PERI_UART3>;
303 clock-names = "baud", "bus";
304 status = "disabled";
305 };
306
307 pwm: pwm@11006000 {
308 compatible = "mediatek,mt7623-pwm";
309
310 reg = <0 0x11006000 0 0x1000>;
311 resets = <&pericfg MT2701_PERI_PWM_SW_RST>;
312 reset-names = "pwm";
313
314 #pwm-cells = <2>;
315 clocks = <&topckgen CLK_TOP_PWM_SEL>,
316 <&pericfg CLK_PERI_PWM>,
317 <&pericfg CLK_PERI_PWM1>,
318 <&pericfg CLK_PERI_PWM2>,
319 <&pericfg CLK_PERI_PWM3>,
320 <&pericfg CLK_PERI_PWM4>,
321 <&pericfg CLK_PERI_PWM5>;
322 clock-names = "top", "main", "pwm1", "pwm2",
323 "pwm3", "pwm4", "pwm5";
324
325 status = "disabled";
326 };
327
328 i2c0: i2c@11007000 {
329 compatible = "mediatek,mt7623-i2c",
330 "mediatek,mt6577-i2c";
331 reg = <0 0x11007000 0 0x70>,
332 <0 0x11000200 0 0x80>;
333 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
334 clock-div = <16>;
335 clocks = <&pericfg CLK_PERI_I2C0>,
336 <&pericfg CLK_PERI_AP_DMA>;
337 clock-names = "main", "dma";
338 #address-cells = <1>;
339 #size-cells = <0>;
340 status = "disabled";
341 };
342
343 i2c1: i2c@11008000 {
344 compatible = "mediatek,mt7623-i2c",
345 "mediatek,mt6577-i2c";
346 reg = <0 0x11008000 0 0x70>,
347 <0 0x11000280 0 0x80>;
348 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
349 clock-div = <16>;
350 clocks = <&pericfg CLK_PERI_I2C1>,
351 <&pericfg CLK_PERI_AP_DMA>;
352 clock-names = "main", "dma";
353 #address-cells = <1>;
354 #size-cells = <0>;
355 status = "disabled";
356 };
357
358 i2c2: i2c@11009000 {
359 compatible = "mediatek,mt7623-i2c",
360 "mediatek,mt6577-i2c";
361 reg = <0 0x11009000 0 0x70>,
362 <0 0x11000300 0 0x80>;
363 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
364 clock-div = <16>;
365 clocks = <&pericfg CLK_PERI_I2C2>,
366 <&pericfg CLK_PERI_AP_DMA>;
367 clock-names = "main", "dma";
368 #address-cells = <1>;
369 #size-cells = <0>;
370 status = "disabled";
371 };
372
373 spi: spi@1100a000 {
374 compatible = "mediatek,mt7623-spi",
375 "mediatek,mt6589-spi";
376 reg = <0 0x1100a000 0 0x1000>;
377 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
378 clocks = <&pericfg CLK_PERI_SPI0>;
379 clock-names = "main";
380
381 status = "disabled";
382 };
383
384 thermal: thermal@1100b000 {
385 #thermal-sensor-cells = <1>;
386 compatible = "mediatek,mt2701-thermal",
387 "mediatek,mt2701-thermal";
388 reg = <0 0x1100b000 0 0x1000>;
389 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
390 clocks = <&pericfg CLK_PERI_THERM>,
391 <&pericfg CLK_PERI_AUXADC>;
392 clock-names = "therm", "auxadc";
393 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
394 reset-names = "therm";
395 mediatek,auxadc = <&auxadc>;
396 mediatek,apmixedsys = <&apmixedsys>;
397
398 nvmem-cells = <&thermal_calibration>;
399 nvmem-cell-names = "calibration-data";
400 };
401
402 nandc: nfi@1100d000 {
403 compatible = "mediatek,mt7623-nfc",
404 "mediatek,mt2701-nfc";
405 reg = <0 0x1100d000 0 0x1000>;
406 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
407 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
408 clocks = <&pericfg CLK_PERI_NFI>,
409 <&pericfg CLK_PERI_NFI_PAD>;
410 clock-names = "nfi_clk", "pad_clk";
411 status = "disabled";
412 ecc-engine = <&bch>;
413 #address-cells = <1>;
414 #size-cells = <0>;
415 };
416
417 bch: ecc@1100e000 {
418 compatible = "mediatek,mt7623-ecc",
419 "mediatek,mt2701-ecc";
420 reg = <0 0x1100e000 0 0x1000>;
421 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
422 clocks = <&pericfg CLK_PERI_NFI_ECC>;
423 clock-names = "nfiecc_clk";
424 status = "disabled";
425 };
426
427 mmc0: mmc@11230000 {
428 compatible = "mediatek,mt7623-mmc",
429 "mediatek,mt8135-mmc";
430 reg = <0 0x11230000 0 0x1000>;
431 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
432 clocks = <&pericfg CLK_PERI_MSDC30_0>,
433 <&topckgen CLK_TOP_MSDC30_0_SEL>;
434 clock-names = "source", "hclk";
435 status = "disabled";
436 };
437
438 mmc1: mmc@11240000 {
439 compatible = "mediatek,mt7623-mmc",
440 "mediatek,mt8135-mmc";
441 reg = <0 0x11240000 0 0x1000>;
442 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
443 clocks = <&pericfg CLK_PERI_MSDC30_1>,
444 <&topckgen CLK_TOP_MSDC30_1_SEL>;
445 clock-names = "source", "hclk";
446 status = "disabled";
447 };
448
449 usb1: usb@1a1c0000 {
450 compatible = "mediatek,mt7623-xhci",
451 "mediatek,mt8173-xhci";
452 reg = <0 0x1a1c0000 0 0x1000>,
453 <0 0x1a1c4700 0 0x0100>;
454 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
455 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
456 <&topckgen CLK_TOP_ETHIF_SEL>;
457 clock-names = "sys_ck", "ethif";
458 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
459 phys = <&phy_port0 PHY_TYPE_USB3>;
460 status = "disabled";
461 };
462
463 u3phy1: usb-phy@1a1c4000 {
464 compatible = "mediatek,mt2701-u3phy",
465 "mediatek,mt8173-u3phy";
466 reg = <0 0x1a1c4000 0 0x0700>;
467 clocks = <&clk26m>;
468 clock-names = "u3phya_ref";
469 #phy-cells = <1>;
470 #address-cells = <2>;
471 #size-cells = <2>;
472 ranges;
473 status = "disabled";
474
475 phy_port0: phy_port0: port@1a1c4800 {
476 reg = <0 0x1a1c4800 0 0x800>;
477 #phy-cells = <1>;
478 status = "okay";
479 };
480 };
481
482 usb2: usb@1a240000 {
483 compatible = "mediatek,mt2701-xhci",
484 "mediatek,mt8173-xhci";
485 reg = <0 0x1a240000 0 0x1000>,
486 <0 0x1a244700 0 0x0100>;
487 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
488 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
489 <&topckgen CLK_TOP_ETHIF_SEL>;
490 clock-names = "sys_ck", "ethif";
491 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
492 phys = <&u3phy2 0>;
493 status = "disabled";
494 };
495
496 u3phy2: usb-phy@1a244000 {
497 compatible = "mediatek,mt2701-u3phy",
498 "mediatek,mt8173-u3phy";
499 reg = <0 0x1a244000 0 0x0700>,
500 <0 0x1a244800 0 0x0800>;
501 clocks = <&clk26m>;
502 clock-names = "u3phya_ref";
503 #phy-cells = <1>;
504 status = "disabled";
505 };
506
507 hifsys: clock-controller@1a000000 {
508 compatible = "mediatek,mt7623-hifsys",
509 "mediatek,mt2701-hifsys",
510 "syscon";
511 reg = <0 0x1a000000 0 0x1000>;
512 #clock-cells = <1>;
513 #reset-cells = <1>;
514 };
515
516 pcie: pcie@1a140000 {
517 compatible = "mediatek,mt7623-pcie";
518 device_type = "pci";
519 reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
520 <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
521 <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
522 <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
523 reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
524 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
525 <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
526 <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
527 interrupt-names = "pcie0", "pcie1", "pcie2";
528 clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
529 clock-names = "pcie";
530 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
531 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
532 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
533 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
534 reset-names = "pcie0", "pcie1", "pcie2";
535
536 mediatek,hifsys = <&hifsys>;
537
538 bus-range = <0x00 0xff>;
539 #address-cells = <3>;
540 #size-cells = <2>;
541
542 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
543 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
544
545 status = "disabled";
546
547 pcie@1,0 {
548 device_type = "pci";
549 reg = <0x0800 0 0 0 0>;
550
551 #address-cells = <3>;
552 #size-cells = <2>;
553 ranges;
554 };
555
556 pcie@2,0{
557 device_type = "pci";
558 reg = <0x1000 0 0 0 0>;
559
560 #address-cells = <3>;
561 #size-cells = <2>;
562 ranges;
563 };
564
565 pcie@3,0{
566 device_type = "pci";
567 reg = <0x1800 0 0 0 0>;
568
569 #address-cells = <3>;
570 #size-cells = <2>;
571 ranges;
572 };
573 };
574
575 ethsys: syscon@1b000000 {
576 compatible = "mediatek,mt7623-ethsys",
577 "mediatek,mt2701-ethsys",
578 "syscon";
579 reg = <0 0x1b000000 0 0x1000>;
580 #reset-cells = <1>;
581 #clock-cells = <1>;
582 };
583
584 eth: ethernet@1b100000 {
585 compatible = "mediatek,mt7623-eth",
586 "mediatek,mt2701-eth",
587 "syscon";
588 reg = <0 0x1b100000 0 0x20000>;
589
590 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
591 <&ethsys CLK_ETHSYS_ESW>,
592 <&ethsys CLK_ETHSYS_GP2>,
593 <&ethsys CLK_ETHSYS_GP1>,
594 <&apmixedsys CLK_APMIXED_TRGPLL>;
595 clock-names = "ethif", "esw", "gp2", "gp1", "trgpll";
596 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
597 GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
598 GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
599 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
600
601 resets = <&ethsys 6>;
602 reset-names = "eth";
603
604 mediatek,ethsys = <&ethsys>;
605 mediatek,pctl = <&syscfg_pctl_a>;
606
607 #address-cells = <1>;
608 #size-cells = <0>;
609
610 status = "disabled";
611
612 gmac1: mac@0 {
613 compatible = "mediatek,eth-mac";
614 reg = <0>;
615
616 status = "disabled";
617
618 phy-mode = "trgmii";
619
620 fixed-link {
621 speed = <1000>;
622 full-duplex;
623 pause;
624 };
625 };
626
627 gmac2: mac@1 {
628 compatible = "mediatek,eth-mac";
629 reg = <1>;
630
631 status = "disabled";
632 };
633
634 mdio0: mdio-bus {
635 #address-cells = <1>;
636 #size-cells = <0>;
637 };
638 };
639 };
OpenWrt Source Repository